Lines Matching +full:pcie +full:- +full:mirror

1 /* SPDX-License-Identifier: GPL-2.0-only */
4  * Copyright 2005-2006 Fen Systems Ltd.
5  * Copyright 2006-2012 Solarflare Communications Inc.
15  *     F<type>_<min-rev><max-rev>_
20  * -------------------------------------------------------------
25  * <min-rev> is the first revision to which the definition applies:
32  * then <max-rev> is the last revision to which the definition applies;
191 /* EE_BASE_PAGE_REG: Expansion ROM base mirror register */
252 /* PCIE_CORE_INDIRECT_REG: Indirect Access to PCIE Core registers */
684 /* DRIVER_REG: Driver scratch register [0-7] */
707 /* PCIE_SD_CTL0123_REG: PCIE SerDes control register 0 to 3 */
764 /* PCIE_SD_CTL45_REG: PCIE SerDes control register 4 and 5 */
799 /* PCIE_PCS_CTL_STAT_REG: PCIE PCS control and status register */
1131 /* RX_DC_PF_WM_REG: Receive descriptor cache pre-fetch watermark register */
2781  * Falcon B0 PCIe core indirect registers
2802  * Pseudo-registers and fields
2807 /* Interrupt acknowledge work-around register (A0/A1 only) */
2844 #define	FRF_AZ_RX_DESC_WPTR_DWORD_LBN (FRF_AZ_RX_DESC_WPTR_LBN - 3 * 32)
2851 #define	FRF_AZ_TX_DESC_WPTR_DWORD_LBN (FRF_AZ_TX_DESC_WPTR_LBN - 3 * 32)
2879 /* XGXS all-lanes status fields */
2898 #define FRF_CZ_RMFT_DEST_MAC_HI_WIDTH (FRF_CZ_RMFT_DEST_MAC_WIDTH - 32)
2905 #define FRF_CZ_TMFT_SRC_MAC_HI_WIDTH (FRF_CZ_TMFT_SRC_MAC_WIDTH - 32)
2914 /* Sub-fields of an RX flush completion event */