Lines Matching +full:tx +full:- +full:ping +full:- +full:pong
1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
63 /* Checksum generation is a per-queue option in hardware, so each
64 * queue visible to the networking core is backed by two hardware TX
86 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
89 * of every buffer. Otherwise, we just need to ensure 4-byte
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
111 * struct efx_buffer - A general-purpose DMA buffer
126 * struct efx_tx_buffer - buffer state for a TX descriptor
131 * @option: When @flags & %EFX_TX_BUF_OPTION, an EF10-specific option
164 * struct efx_tx_queue - An Efx TX queue
166 * This is a ring buffer of TX fragments.
167 * Since the TX completion path always executes on the same
178 * @label: Label for TX completion events.
179 * Is our index within @channel->tx_queue array.
180 * @type: configuration type of this TX queue. A bitmask of %EFX_TXQ_TYPE_* flags.
184 * @core_txq: The networking core TX queue structure
187 * %EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
190 * @piobuf: PIO buffer region for this TX queue (shared with its partner).
195 * @xdp_tx: Is this an XDP tx queue?
200 * only get the up-to-date value of @write_count if this
202 * avoid cache-line ping-pong between the xmit path and the
204 * @merge_events: Number of TX merged completion events
205 * @completed_timestamp_major: Top part of the most recent tx timestamp.
206 * @completed_timestamp_minor: Low part of the most recent tx timestamp.
217 * Filled in iff @efx->type->option_descriptors; only used for PIO.
221 * only get the up-to-date value of read_count if this
223 * avoid cache-line ping-pong between the xmit path and the
230 * @pushes: Number of times the TX push feature has been used
231 * @pio_packets: Number of times the TX PIO feature has been used
233 * @cb_packets: Number of times the TX copybreak feature has been used
237 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
292 #define EFX_TX_CB_SIZE (1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
295 * struct efx_rx_buffer - An Efx RX data buffer
321 * struct efx_rx_page_state - Page-based rx buffer state
336 * struct efx_rx_queue - An Efx RX queue
367 * @min_fill: RX descriptor minimum non-zero fill level.
421 * struct efx_channel - An Efx channel
423 * A channel comprises an event queue, at least one TX queue, at least
432 * @irq: IRQ number (MSI and MSI-X only)
477 * @tx_queue: TX queues for this channel
550 * struct efx_msi_context - Context for each MSI
565 * struct efx_channel_type - distinguishes traffic and extra channels
577 * @want_txqs: Determine whether this channel should have TX queues
578 * created. If %NULL, TX queues are not created.
582 * channel's TX queues.
611 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
620 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
675 /* Pseudo bit-mask flow control field */
681 * struct efx_link_state - Current state of the link
683 * @fd: Link is full-duplex
697 return left->up == right->up && left->fd == right->fd &&
698 left->fc == right->fc && left->speed == right->speed;
702 * enum efx_phy_mode - PHY operating mode flags
704 * @PHY_MODE_TX_DISABLED: on with TX disabled
723 * struct efx_hw_stat_desc - Description of a hardware statistic
726 * @dma_width: Width in bits (0 for non-DMA statistics)
727 * @offset: Offset within stats (ignored for non-DMA statistics)
740 * struct efx_rss_context_priv - driver private data for an RSS context
743 * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
751 * struct efx_rss_context - an RSS context
752 * @priv: hardware-specific state
766 #define EFX_ARFS_FILTER_ID_PENDING -1
767 #define EFX_ARFS_FILTER_ID_ERROR -2
768 #define EFX_ARFS_FILTER_ID_REMOVING -3
770 * struct efx_arfs_rule - record of an ARFS filter and its IDs
772 * @spec: details of the filter (used as key for hash table). Use efx->type to
793 * struct efx_async_filter_insertion - Request to asynchronously insert a filter
798 * @flow_id: Identifies the kernel-side flow for which this request was made
821 * struct efx_nic - an Efx NIC
839 * @vi_stride: step between per-VI registers / memory regions
850 * @tx_queue: TX DMA queues
854 * @extra_channel_types: Types of extra (non-traffic) channels that
858 * @xdp_tx_queues: Array of pointers to tx queues used for XDP transmit.
859 * @xdp_txq_queues_mode: XDP TX queues sharing strategy.
862 * @txq_stop_thresh: TX queue fill level at or above which we stop it.
863 * @txq_wake_thresh: TX queue fill level at or below which we wake it.
864 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
869 * @n_tx_channels: Number of channels used for TX
870 * @n_extra_tx_channels: Number of extra channels with TX queues
871 * @tx_queues_per_channel: number of TX queues probed on each channel
872 * @n_xdp_channels: Number of channels used for XDP TX
873 * @xdp_channel_offset: Offset of zeroth channel used for XPD TX.
874 * @xdp_tx_per_channel: Max number of TX queues on an XDP TX channel.
887 * (valid only if channel->sync_timestamps_enabled; always negative)
894 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
899 * @selftest_work: Work item for asynchronous self-test
902 * @mcdi: Management-Controller-to-Driver Interface state
917 * @phy_data: PHY private data (including PHY-specific stats)
927 * @fc_disable: When non-zero flow control is disabled. Typically used to
933 * @loopback_selftest: Offline self-test private state
936 * @filter_state: Architecture-dependent filter table state
938 * @rps_slot_map: bitmap of in-flight entries in @rps_slot
944 * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
1164 * struct efx_probe_data - State after hardware probe
1178 return &probe_data->efx;
1183 return efx->net_dev->reg_state == NETREG_REGISTERED;
1188 return efx->port_num;
1206 * struct efx_nic_type - Efx device type definition
1223 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1237 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1248 * The SDU length may be any value from 0 up to the protocol-
1261 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
1267 * @tx_probe: Allocate resources for TX queue (and select TXQ type)
1268 * @tx_init: Initialise TX queue on the NIC
1269 * @tx_remove: Free resources for TX queue
1270 * @tx_write: Write TX descriptors and doorbell
1271 * @tx_enqueue: Add an SKB to TX queue
1313 * @mtd_sync: Wait for write-back to complete on MTD partition. This
1324 * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1328 * @print_additional_fwver: Dump NIC-specific additional FW version info
1332 * @txd_ptr_tbl_base: TX descriptor ring base address
1336 * @evq_rptr_tbl_base: Event queue read-pointer table base address
1344 * @option_descriptors: NIC supports TX option descriptors
1539 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels);
1540 return efx->channel[index];
1545 for (_channel = (_efx)->channel[0]; \
1547 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1548 (_efx)->channel[_channel->channel + 1] : NULL)
1552 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1554 _channel = _channel->channel ? \
1555 (_efx)->channel[_channel->channel - 1] : NULL)
1560 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels);
1561 return efx->channel[efx->tx_channel_offset + index];
1567 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_xdp_channels);
1568 return efx->channel[efx->xdp_channel_offset + index];
1573 return channel->channel - channel->efx->xdp_channel_offset <
1574 channel->efx->n_xdp_channels;
1579 return channel && channel->channel >= channel->efx->tx_channel_offset;
1585 return channel->efx->xdp_tx_per_channel;
1586 return channel->efx->tx_queues_per_channel;
1593 return channel->tx_queue_by_type[type];
1604 /* Iterate over all TX queues belonging to a channel */
1609 for (_tx_queue = (_channel)->tx_queue; \
1610 _tx_queue < (_channel)->tx_queue + \
1616 return channel->rx_queue.core_index >= 0;
1623 return &channel->rx_queue;
1631 for (_rx_queue = &(_channel)->rx_queue; \
1643 return efx_rx_queue_channel(rx_queue)->channel;
1652 return &rx_queue->buffer[index];
1658 if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))
1665 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1673 * The 10G MAC requires 8-byte alignment on the frame
1676 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1687 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1691 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1694 /* Get the max fill level of the TX queues on this channel */
1703 tx_queue->insert_count - tx_queue->read_count);
1717 tx_queue->insert_count - tx_queue->old_read_count);
1729 const struct net_device *net_dev = efx->net_dev;
1731 return net_dev->features | net_dev->hw_features;
1734 /* Get the current TX queue insert index. */
1738 return tx_queue->insert_count & tx_queue->ptr_mask;
1741 /* Get a TX buffer. */
1745 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
1748 /* Get a TX buffer, checking it's not currently in use. */
1755 EFX_WARN_ON_ONCE_PARANOID(buffer->len);
1756 EFX_WARN_ON_ONCE_PARANOID(buffer->flags);
1757 EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len);