Lines Matching +full:0 +full:xc02
36 #define MC_SMEM_P0_DOORBELL_OFST 0x000
37 #define MC_SMEM_P1_DOORBELL_OFST 0x004
39 #define MC_SMEM_P0_PDU_OFST 0x008
40 #define MC_SMEM_P1_PDU_OFST 0x108
41 #define MC_SMEM_PDU_LEN 0x100
42 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
43 #define MC_SMEM_P0_STATUS_OFST 0x7f8
44 #define MC_SMEM_P1_STATUS_OFST 0x7fc
48 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
49 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
52 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
57 * least every driver must support version 0 and MCDI_PCOL_VERSION
61 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
68 * 0 7 8 16 20 22 23 24 31
94 #define MCDI_HEADER_OFST 0
95 #define MCDI_HEADER_CODE_LBN 0
114 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
116 #define MCDI_HEADER_XFLAGS_DBRET 0x02
119 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
120 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400
132 * 0 32 33 36 44 52 60
142 * 0 8 16 24 32
146 * LEVEL==ERR, Datalen == 0 => Reboot
150 * examining the first byte which is 0xc0. This corresponds to the
153 * 0 7 8
154 * | command | Resync | = 0xc0
157 * providing bits 56-63 of the event are 0xc0.
160 * | Rsvd | Code | = 0xc0
162 * Which means for convenience the event code is 0xc for all MC
165 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
168 #define MC_CMD_ERR_CODE_OFST 0
174 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
175 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
176 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
177 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
178 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
179 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
180 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
181 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
185 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
186 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
187 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
189 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
190 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
191 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
193 #define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
194 #define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
195 #define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)
198 #define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)
206 0, 0, 0 }
229 #define EVB_STACK_ID(n) (((n) & 0xff) << 16)
233 * may be followed by the (0-based) number of the first argument that
240 * specific to Solarflare firmware should use values in the range 0x1000 -
241 * 0x10ff. The range 0x2000 - 0x20ff is reserved for private error codes (see
245 #define MC_CMD_ERR_EPERM 0x1
247 #define MC_CMD_ERR_ENOENT 0x2
249 #define MC_CMD_ERR_EINTR 0x4
251 #define MC_CMD_ERR_EIO 0x5
253 #define MC_CMD_ERR_EEXIST 0x6
255 #define MC_CMD_ERR_EAGAIN 0xb
257 #define MC_CMD_ERR_ENOMEM 0xc
259 #define MC_CMD_ERR_EACCES 0xd
261 #define MC_CMD_ERR_EBUSY 0x10
263 #define MC_CMD_ERR_ENODEV 0x13
265 #define MC_CMD_ERR_EINVAL 0x16
267 #define MC_CMD_ERR_ENOSPC 0x1c
269 #define MC_CMD_ERR_EROFS 0x1e
271 #define MC_CMD_ERR_EPIPE 0x20
273 #define MC_CMD_ERR_ERANGE 0x22
275 #define MC_CMD_ERR_EDEADLK 0x23
277 #define MC_CMD_ERR_ENOSYS 0x26
279 #define MC_CMD_ERR_ETIME 0x3e
281 #define MC_CMD_ERR_ENOLINK 0x43
283 #define MC_CMD_ERR_EPROTO 0x47
285 #define MC_CMD_ERR_EBADMSG 0x4a
287 #define MC_CMD_ERR_ENOTSUP 0x5f
289 #define MC_CMD_ERR_EADDRNOTAVAIL 0x63
291 #define MC_CMD_ERR_ENOTCONN 0x6b
293 #define MC_CMD_ERR_EALREADY 0x72
296 #define MC_CMD_ERR_ESTALE 0x74
298 #define MC_CMD_ERR_ALLOC_FAIL 0x1000
300 #define MC_CMD_ERR_NO_VADAPTOR 0x1001
302 #define MC_CMD_ERR_NO_EVB_PORT 0x1002
304 #define MC_CMD_ERR_NO_VSWITCH 0x1003
306 #define MC_CMD_ERR_VLAN_LIMIT 0x1004
308 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
310 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
312 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
314 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
316 #define MC_CMD_ERR_MAC_EXIST 0x1009
318 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
320 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
322 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c
327 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
329 #define MC_CMD_ERR_VLAN_EXIST 0x100e
331 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f
337 #define MC_CMD_ERR_PROXY_PENDING 0x1010
342 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
347 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
354 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013
360 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014
364 #define MC_CMD_ERR_NO_CLOCK 0x1015
368 #define MC_CMD_ERR_UNREACHABLE 0x1016
372 #define MC_CMD_ERR_QUEUE_FULL 0x1017
377 #define MC_CMD_ERR_NO_PCIE 0x1018
382 #define MC_CMD_ERR_NO_DATAPATH 0x1019
384 #define MC_CMD_ERR_VIS_PRESENT 0x101a
388 #define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
392 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
393 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */
396 #define MC_CMD_FPGA_FLASH_PRIMARY 0x0 /* enum */
397 #define MC_CMD_FPGA_FLASH_SECONDARY 0x1 /* enum */
401 #define MC_CMD_EXTERNAL_MAE_LINK_MODE_LEGACY 0x0
403 #define MC_CMD_EXTERNAL_MAE_LINK_MODE_SWITCHDEV 0x1
405 #define MC_CMD_EXTERNAL_MAE_LINK_MODE_BOOTSTRAP 0x2
407 #define MC_CMD_EXTERNAL_MAE_LINK_MODE_PENDING 0xf
422 #define PCIE_INTERFACE_HOST_PRIMARY 0x0
426 #define PCIE_INTERFACE_NIC_EMBEDDED 0x1
431 #define PCIE_INTERFACE_CALLER 0xffffffff
435 #define MC_CMD_CLIENT_ID_SELF 0xffffffff
449 #define MAE_FIELD_UNSUPPORTED 0x0
454 #define MAE_FIELD_SUPPORTED_MATCH_NEVER 0x1
459 #define MAE_FIELD_SUPPORTED_MATCH_ALWAYS 0x2
465 #define MAE_FIELD_SUPPORTED_MATCH_OPTIONAL 0x3
471 #define MAE_FIELD_SUPPORTED_MATCH_PREFIX 0x4
475 #define MAE_FIELD_SUPPORTED_MATCH_MASK 0x5
481 #define MAE_CT_VNI_MODE_ZERO 0x0
485 #define MAE_CT_VNI_MODE_VNI 0x1
489 #define MAE_CT_VNI_MODE_1VLAN 0x2
493 #define MAE_CT_VNI_MODE_2VLAN 0x3
498 #define MAE_FIELD_INGRESS_PORT 0x0
499 #define MAE_FIELD_MARK 0x1 /* enum */
503 #define MAE_FIELD_RECIRC_ID 0x2
504 #define MAE_FIELD_IS_IP_FRAG 0x3 /* enum */
505 #define MAE_FIELD_DO_CT 0x4 /* enum */
506 #define MAE_FIELD_CT_HIT 0x5 /* enum */
508 #define MAE_FIELD_CT_MARK 0x6
510 #define MAE_FIELD_CT_DOMAIN 0x7
512 #define MAE_FIELD_CT_PRIVATE_FLAGS 0x8
513 /* enum: 1 if the packet ingressed the NIC from one of the MACs, else 0. */
514 #define MAE_FIELD_IS_FROM_NETWORK 0x9
515 /* enum: 1 if the packet has 1 or more VLAN tags, else 0. */
516 #define MAE_FIELD_HAS_OVLAN 0xa
517 /* enum: 1 if the packet has 2 or more VLAN tags, else 0. */
518 #define MAE_FIELD_HAS_IVLAN 0xb
519 /* enum: 1 if the outer packet has 1 or more VLAN tags, else 0; only present
522 #define MAE_FIELD_ENC_HAS_OVLAN 0xc
523 /* enum: 1 if the outer packet has 2 or more VLAN tags, else 0; only present
526 #define MAE_FIELD_ENC_HAS_IVLAN 0xd
528 #define MAE_FIELD_ENC_IP_FRAG 0xe
529 #define MAE_FIELD_ETHER_TYPE 0x21 /* enum */
530 #define MAE_FIELD_VLAN0_TCI 0x22 /* enum */
531 #define MAE_FIELD_VLAN0_PROTO 0x23 /* enum */
532 #define MAE_FIELD_VLAN1_TCI 0x24 /* enum */
533 #define MAE_FIELD_VLAN1_PROTO 0x25 /* enum */
535 #define MAE_FIELD_ETH_SADDR 0x28
537 #define MAE_FIELD_ETH_DADDR 0x29
539 #define MAE_FIELD_SRC_IP4 0x2a
541 #define MAE_FIELD_SRC_IP6 0x2b
543 #define MAE_FIELD_DST_IP4 0x2c
545 #define MAE_FIELD_DST_IP6 0x2d
547 #define MAE_FIELD_IP_PROTO 0x2e
549 #define MAE_FIELD_IP_TOS 0x2f
551 #define MAE_FIELD_IP_TTL 0x30
560 #define MAE_FIELD_IP_FLAGS 0x31
562 #define MAE_FIELD_L4_SPORT 0x32
564 #define MAE_FIELD_L4_DPORT 0x33
566 #define MAE_FIELD_TCP_FLAGS 0x34
568 #define MAE_FIELD_TCP_SYN_FIN_RST 0x35
569 /* enum: Packet is IP fragment with fragment offset 0 */
570 #define MAE_FIELD_IP_FIRST_FRAG 0x36
574 #define MAE_FIELD_ENCAP_TYPE 0x3f
578 #define MAE_FIELD_OUTER_RULE_ID 0x40
580 #define MAE_FIELD_ENC_ETHER_TYPE 0x41
582 #define MAE_FIELD_ENC_VLAN0_TCI 0x42
584 #define MAE_FIELD_ENC_VLAN0_PROTO 0x43
586 #define MAE_FIELD_ENC_VLAN1_TCI 0x44
588 #define MAE_FIELD_ENC_VLAN1_PROTO 0x45
590 #define MAE_FIELD_ENC_ETH_SADDR 0x48
592 #define MAE_FIELD_ENC_ETH_DADDR 0x49
594 #define MAE_FIELD_ENC_SRC_IP4 0x4a
596 #define MAE_FIELD_ENC_SRC_IP6 0x4b
598 #define MAE_FIELD_ENC_DST_IP4 0x4c
600 #define MAE_FIELD_ENC_DST_IP6 0x4d
602 #define MAE_FIELD_ENC_IP_PROTO 0x4e
604 #define MAE_FIELD_ENC_IP_TOS 0x4f
606 #define MAE_FIELD_ENC_IP_TTL 0x50
608 #define MAE_FIELD_ENC_IP_FLAGS 0x51
610 #define MAE_FIELD_ENC_L4_SPORT 0x52
612 #define MAE_FIELD_ENC_L4_DPORT 0x53
616 #define MAE_FIELD_ENC_VNET_ID 0x54
623 #define MAE_MCDI_ENCAP_TYPE_NONE 0x0 /* enum */
625 #define MAE_MCDI_ENCAP_TYPE_VXLAN 0x1
626 #define MAE_MCDI_ENCAP_TYPE_NVGRE 0x2 /* enum */
627 #define MAE_MCDI_ENCAP_TYPE_GENEVE 0x3 /* enum */
628 #define MAE_MCDI_ENCAP_TYPE_L2GRE 0x4 /* enum */
634 #define MAE_MPORT_END_MAE 0x1
636 #define MAE_MPORT_END_VNIC 0x2
646 #define MAE_COUNTER_TYPE_AR 0x0
648 #define MAE_COUNTER_TYPE_CT 0x1
650 #define MAE_COUNTER_TYPE_OR 0x2
653 * structured with bits [31:24] reserved (0), [23:16] indicating which major
654 * block the tables belongs to (0=VNIC TX, none currently; 1=MAE; 2=VNIC RX),
655 * [15:8] a unique ID within the block, and [7:0] reserved for future
662 #define TABLE_ID_OUTER_RULE_TABLE 0x10000
664 #define TABLE_ID_OUTER_RULE_NO_CT_TABLE 0x10100
666 #define TABLE_ID_MGMT_FILTER_TABLE 0x10200
668 #define TABLE_ID_CONNTRACK_TABLE 0x10300
670 #define TABLE_ID_ACTION_RULE_TABLE 0x10400
672 #define TABLE_ID_MGROUP_DEFAULT_ACTION_SET_TABLE 0x10500
674 #define TABLE_ID_ENCAP_HDR_PART1_TABLE 0x10600
676 #define TABLE_ID_ENCAP_HDR_PART2_TABLE 0x10700
678 #define TABLE_ID_REPLACE_SRC_MAC_TABLE 0x10800
680 #define TABLE_ID_REPLACE_DST_MAC_TABLE 0x10900
682 #define TABLE_ID_DST_MPORT_VC_TABLE 0x10a00
684 #define TABLE_ID_LACP_LAG_CONFIG_TABLE 0x10b00
686 #define TABLE_ID_LACP_BALANCE_TABLE 0x10c00
688 #define TABLE_ID_DST_MPORT_HOST_CHAN_TABLE 0x10d00
690 #define TABLE_ID_VNIC_RX_ENCAP_TABLE 0x20000
692 #define TABLE_ID_STEERING_TABLE 0x20100
694 #define TABLE_ID_RSS_CONTEXT_TABLE 0x20200
696 #define TABLE_ID_INDIRECTION_TABLE 0x20300
699 * types; can be calculated by (((ether_type_msb >> 2) & 0x4) ^ 0x4) |
700 * (ether_type_msb & 0x3);
702 #define TABLE_COMPRESSED_VLAN_TPID_8100 0x5 /* enum */
703 #define TABLE_COMPRESSED_VLAN_TPID_88A8 0x4 /* enum */
704 #define TABLE_COMPRESSED_VLAN_TPID_9100 0x1 /* enum */
705 #define TABLE_COMPRESSED_VLAN_TPID_9200 0x2 /* enum */
706 #define TABLE_COMPRESSED_VLAN_TPID_9300 0x3 /* enum */
709 #define TABLE_NAT_DIR_SOURCE 0x0 /* enum */
710 #define TABLE_NAT_DIR_DEST 0x1 /* enum */
717 #define TABLE_RSS_KEY_MODE_SA_DA 0x0
719 #define TABLE_RSS_KEY_MODE_SA_DA_SP_DP 0x1
721 #define TABLE_RSS_KEY_MODE_SA 0x2
723 #define TABLE_RSS_KEY_MODE_DA 0x3
725 #define TABLE_RSS_KEY_MODE_SA_SP 0x4
727 #define TABLE_RSS_KEY_MODE_DA_DP 0x5
728 /* enum: Nothing (produces input of 0, resulting in output hash of 0) */
729 #define TABLE_RSS_KEY_MODE_NONE 0x7
733 #define TABLE_RSS_SPREAD_MODE_INDIRECTION 0x0
735 #define TABLE_RSS_SPREAD_MODE_EVEN 0x1
749 * the field is unused and should be set to 0 (or masked out if permitted by
752 #define TABLE_FIELD_ID_UNUSED 0x0
754 #define TABLE_FIELD_ID_SRC_MPORT 0x1
756 #define TABLE_FIELD_ID_DST_MPORT 0x2
758 #define TABLE_FIELD_ID_SRC_MGROUP_ID 0x3
762 #define TABLE_FIELD_ID_NETWORK_PORT_ID 0x4
765 #define TABLE_FIELD_ID_IS_FROM_NETWORK 0x5
767 #define TABLE_FIELD_ID_CH_VC 0x6
769 #define TABLE_FIELD_ID_CH_VC_LOW 0x7
771 #define TABLE_FIELD_ID_USER_MARK 0x8
773 #define TABLE_FIELD_ID_USER_FLAG 0x9
777 #define TABLE_FIELD_ID_COUNTER_ID 0xa
782 #define TABLE_FIELD_ID_DISCRIM 0xb
785 * AA:BB:CC:DD:EE:FF becomes a 48-bit value of 0xAABBCCDDEEFF.
787 #define TABLE_FIELD_ID_DST_MAC 0x14
789 #define TABLE_FIELD_ID_SRC_MAC 0x15
791 #define TABLE_FIELD_ID_OVLAN_TPID_COMPRESSED 0x16
793 #define TABLE_FIELD_ID_OVLAN 0x17
795 #define TABLE_FIELD_ID_OVLAN_VID 0x18
797 #define TABLE_FIELD_ID_IVLAN_TPID_COMPRESSED 0x19
799 #define TABLE_FIELD_ID_IVLAN 0x1a
801 #define TABLE_FIELD_ID_IVLAN_VID 0x1b
803 #define TABLE_FIELD_ID_ETHER_TYPE 0x1c
807 * [2345::6789:ABCD] is 0x2345000000000000000000006789ABCD; the IPv4 address
808 * 192.168.1.2 is 0xC0A80102000000000000000000000000.
810 #define TABLE_FIELD_ID_SRC_IP 0x1d
812 #define TABLE_FIELD_ID_DST_IP 0x1e
814 #define TABLE_FIELD_ID_IP_TOS 0x1f
816 #define TABLE_FIELD_ID_IP_PROTO 0x20
818 #define TABLE_FIELD_ID_SRC_PORT 0x21
820 #define TABLE_FIELD_ID_DST_PORT 0x22
822 #define TABLE_FIELD_ID_TCP_FLAGS 0x23
824 #define TABLE_FIELD_ID_VNI 0x24
826 #define TABLE_FIELD_ID_HAS_ENCAP 0x32
828 #define TABLE_FIELD_ID_HAS_ENC_OVLAN 0x33
830 #define TABLE_FIELD_ID_HAS_ENC_IVLAN 0x34
832 #define TABLE_FIELD_ID_HAS_ENC_IP 0x35
834 #define TABLE_FIELD_ID_HAS_ENC_IP4 0x36
836 #define TABLE_FIELD_ID_HAS_ENC_UDP 0x37
838 #define TABLE_FIELD_ID_HAS_OVLAN 0x38
840 #define TABLE_FIELD_ID_HAS_IVLAN 0x39
842 #define TABLE_FIELD_ID_HAS_IP 0x3a
845 #define TABLE_FIELD_ID_HAS_L4 0x3b
847 #define TABLE_FIELD_ID_IP_FRAG 0x3c
848 /* enum: True if only/inner frame is the first IP fragment (fragment offset 0).
850 #define TABLE_FIELD_ID_IP_FIRST_FRAG 0x3d
853 * with TTL=0 - which we shouldn't be seeing! - as well.)
855 #define TABLE_FIELD_ID_IP_TTL_LE_ONE 0x3e
857 #define TABLE_FIELD_ID_TCP_INTERESTING_FLAGS 0x3f
859 #define TABLE_FIELD_ID_RDP_PL_CHAN 0x50
861 #define TABLE_FIELD_ID_RDP_C_PL_EN 0x51
863 #define TABLE_FIELD_ID_RDP_C_PL 0x52
865 #define TABLE_FIELD_ID_RDP_D_PL_EN 0x53
867 #define TABLE_FIELD_ID_RDP_D_PL 0x54
869 #define TABLE_FIELD_ID_RDP_OUT_HOST_CHAN_EN 0x55
871 #define TABLE_FIELD_ID_RDP_OUT_HOST_CHAN 0x56
873 #define TABLE_FIELD_ID_RECIRC_ID 0x64
875 #define TABLE_FIELD_ID_DOMAIN 0x65
877 #define TABLE_FIELD_ID_CT_VNI_MODE 0x66
880 #define TABLE_FIELD_ID_CT_TCP_FLAGS_INHIBIT 0x67
882 #define TABLE_FIELD_ID_DO_CT_IP4_TCP 0x68
884 #define TABLE_FIELD_ID_DO_CT_IP4_UDP 0x69
886 #define TABLE_FIELD_ID_DO_CT_IP6_TCP 0x6a
888 #define TABLE_FIELD_ID_DO_CT_IP6_UDP 0x6b
890 #define TABLE_FIELD_ID_OUTER_RULE_ID 0x6c
892 #define TABLE_FIELD_ID_ENCAP_TYPE 0x6d
893 /* enum: Encap tunnel ID for conntrack lookups from VNI, VLAN tag(s), or 0,
896 #define TABLE_FIELD_ID_ENCAP_TUNNEL_ID 0x78
898 #define TABLE_FIELD_ID_CT_ENTRY_ID 0x79
900 #define TABLE_FIELD_ID_NAT_PORT 0x7a
904 * 192.168.1.2 is the value 0xC0A80102.
906 #define TABLE_FIELD_ID_NAT_IP 0x7b
907 /* enum: NAT direction: 0=>source, 1=>destination. */
908 #define TABLE_FIELD_ID_NAT_DIR 0x7c
912 #define TABLE_FIELD_ID_CT_MARK 0x7d
914 #define TABLE_FIELD_ID_CT_PRIV_FLAGS 0x7e
916 #define TABLE_FIELD_ID_CT_HIT 0x7f
919 #define TABLE_FIELD_ID_SUPPRESS_SELF_DELIVERY 0x8c
921 #define TABLE_FIELD_ID_DO_DECAP 0x8d
923 #define TABLE_FIELD_ID_DECAP_DSCP_COPY 0x8e
925 #define TABLE_FIELD_ID_DECAP_ECN_RFC6040 0x8f
927 #define TABLE_FIELD_ID_DO_REPLACE_DSCP 0x90
929 #define TABLE_FIELD_ID_DO_REPLACE_ECN 0x91
931 #define TABLE_FIELD_ID_DO_DECR_IP_TTL 0x92
933 #define TABLE_FIELD_ID_DO_SRC_MAC 0x93
935 #define TABLE_FIELD_ID_DO_DST_MAC 0x94
936 /* enum: Number of VLAN tags to pop. Valid values are 0, 1, or 2. */
937 #define TABLE_FIELD_ID_DO_VLAN_POP 0x95
938 /* enum: Number of VLANs tags to push. Valid values are 0, 1, or 2. */
939 #define TABLE_FIELD_ID_DO_VLAN_PUSH 0x96
941 #define TABLE_FIELD_ID_DO_COUNT 0x97
943 #define TABLE_FIELD_ID_DO_ENCAP 0x98
945 #define TABLE_FIELD_ID_ENCAP_DSCP_COPY 0x99
947 #define TABLE_FIELD_ID_ENCAP_ECN_COPY 0x9a
949 #define TABLE_FIELD_ID_DO_DELIVER 0x9b
951 #define TABLE_FIELD_ID_DO_FLAG 0x9c
953 #define TABLE_FIELD_ID_DO_MARK 0x9d
956 #define TABLE_FIELD_ID_DO_SET_NET_CHAN 0x9e
958 #define TABLE_FIELD_ID_DO_SET_SRC_MPORT 0x9f
960 #define TABLE_FIELD_ID_ENCAP_HDR_ID 0xaa
962 #define TABLE_FIELD_ID_DSCP_VALUE 0xab
964 * DO_REPLACE_ECN is not set, ECN_CONTROL[0] and ECN_CONTROL[1] are set to
967 #define TABLE_FIELD_ID_ECN_CONTROL 0xac
969 #define TABLE_FIELD_ID_SRC_MAC_ID 0xad
971 #define TABLE_FIELD_ID_DST_MAC_ID 0xae
975 #define TABLE_FIELD_ID_REPORTED_SRC_MPORT_OR_NET_CHAN 0xaf
977 #define TABLE_FIELD_ID_CHUNK64 0xb4
979 #define TABLE_FIELD_ID_CHUNK32 0xb5
981 #define TABLE_FIELD_ID_CHUNK16 0xb6
983 #define TABLE_FIELD_ID_CHUNK8 0xb7
985 #define TABLE_FIELD_ID_CHUNK4 0xb8
987 #define TABLE_FIELD_ID_CHUNK2 0xb9
989 #define TABLE_FIELD_ID_HDR_LEN_W 0xba
991 #define TABLE_FIELD_ID_ENC_LACP_HASH_L23 0xbb
993 #define TABLE_FIELD_ID_ENC_LACP_HASH_L4 0xbc
998 #define TABLE_FIELD_ID_USE_ENC_LACP_HASHES 0xbd
1002 #define TABLE_FIELD_ID_DO_CT 0xc8
1005 #define TABLE_FIELD_ID_DO_NAT 0xc9
1007 #define TABLE_FIELD_ID_DO_RECIRC 0xca
1010 #define TABLE_FIELD_ID_NEXT_ACTION_SET_PAYLOAD 0xcb
1012 #define TABLE_FIELD_ID_NEXT_ACTION_SET_ROW 0xcc
1016 #define TABLE_FIELD_ID_MC_ACTION_SET_PAYLOAD 0xcd
1020 #define TABLE_FIELD_ID_MC_ACTION_SET_ROW 0xce
1022 #define TABLE_FIELD_ID_LACP_INC_L4 0xdc
1024 #define TABLE_FIELD_ID_LACP_PLUGIN 0xdd
1026 #define TABLE_FIELD_ID_BAL_TBL_BASE_DIV64 0xde
1027 /* enum: Length of balance table region: 0=>64, 1=>128, 2=>256. */
1028 #define TABLE_FIELD_ID_BAL_TBL_LEN_ID 0xdf
1029 /* enum: UDP port to match for UDP-based encapsulations; required to be 0 for
1032 #define TABLE_FIELD_ID_UDP_PORT 0xe6
1034 #define TABLE_FIELD_ID_RSS_ON_OUTER 0xe7
1038 #define TABLE_FIELD_ID_STEER_ON_OUTER 0xe8
1040 #define TABLE_FIELD_ID_DST_QID 0xf0
1042 #define TABLE_FIELD_ID_DROP 0xf1
1044 #define TABLE_FIELD_ID_VLAN_STRIP 0xf2
1048 #define TABLE_FIELD_ID_MARK_OVERRIDE 0xf3
1052 #define TABLE_FIELD_ID_FLAG_OVERRIDE 0xf4
1054 #define TABLE_FIELD_ID_RSS_CTX_ID 0xfa
1056 #define TABLE_FIELD_ID_RSS_EN 0xfb
1058 #define TABLE_FIELD_ID_KEY 0xfc
1060 #define TABLE_FIELD_ID_TCP_V4_KEY_MODE 0xfd
1062 #define TABLE_FIELD_ID_TCP_V6_KEY_MODE 0xfe
1064 #define TABLE_FIELD_ID_UDP_V4_KEY_MODE 0xff
1066 #define TABLE_FIELD_ID_UDP_V6_KEY_MODE 0x100
1068 #define TABLE_FIELD_ID_OTHER_V4_KEY_MODE 0x101
1070 #define TABLE_FIELD_ID_OTHER_V6_KEY_MODE 0x102
1071 /* enum: Spreading mode - 0=>indirection; 1=>even. */
1072 #define TABLE_FIELD_ID_SPREAD_MODE 0x103
1077 #define TABLE_FIELD_ID_INDIR_TBL_BASE 0x104
1079 * within the Indirection_Table, where length = 32 << len_id. Must be set to 0
1082 #define TABLE_FIELD_ID_INDIR_TBL_LEN_ID 0x105
1084 #define TABLE_FIELD_ID_INDIR_OFFSET 0x106
1095 #define MCDI_EVENT_LEVEL_INFO 0x0
1097 #define MCDI_EVENT_LEVEL_WARN 0x1
1099 #define MCDI_EVENT_LEVEL_ERR 0x2
1101 #define MCDI_EVENT_LEVEL_FATAL 0x3
1102 #define MCDI_EVENT_DATA_OFST 0
1104 #define MCDI_EVENT_CMDDONE_SEQ_OFST 0
1105 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0
1107 #define MCDI_EVENT_CMDDONE_DATALEN_OFST 0
1110 #define MCDI_EVENT_CMDDONE_ERRNO_OFST 0
1113 #define MCDI_EVENT_LINKCHANGE_LP_CAP_OFST 0
1114 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
1116 #define MCDI_EVENT_LINKCHANGE_SPEED_OFST 0
1120 #define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
1122 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
1124 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
1126 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
1128 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
1130 #define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
1132 #define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
1134 #define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
1135 #define MCDI_EVENT_LINKCHANGE_FCNTL_OFST 0
1138 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0
1141 #define MCDI_EVENT_SENSOREVT_MONITOR_OFST 0
1142 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
1144 #define MCDI_EVENT_SENSOREVT_STATE_OFST 0
1147 #define MCDI_EVENT_SENSOREVT_VALUE_OFST 0
1150 #define MCDI_EVENT_FWALERT_DATA_OFST 0
1153 #define MCDI_EVENT_FWALERT_REASON_OFST 0
1154 #define MCDI_EVENT_FWALERT_REASON_LBN 0
1157 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
1158 #define MCDI_EVENT_FLR_VF_OFST 0
1159 #define MCDI_EVENT_FLR_VF_LBN 0
1161 #define MCDI_EVENT_TX_ERR_TXQ_OFST 0
1162 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0
1164 #define MCDI_EVENT_TX_ERR_TYPE_OFST 0
1168 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
1172 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2
1174 #define MCDI_EVENT_TX_ERR_2BIG 0x3
1176 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5
1180 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8
1182 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
1183 #define MCDI_EVENT_TX_ERR_INFO_OFST 0
1186 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 0
1189 #define MCDI_EVENT_TX_FLUSH_TXQ_OFST 0
1190 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
1192 #define MCDI_EVENT_PTP_ERR_TYPE_OFST 0
1193 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
1196 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
1198 #define MCDI_EVENT_PTP_ERR_FILTER 0x2
1200 #define MCDI_EVENT_PTP_ERR_FIFO 0x3
1202 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4
1203 #define MCDI_EVENT_AOE_ERR_TYPE_OFST 0
1204 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0
1207 #define MCDI_EVENT_AOE_NO_LOAD 0x1
1209 #define MCDI_EVENT_AOE_FC_ASSERT 0x2
1211 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3
1213 #define MCDI_EVENT_AOE_FC_NO_START 0x4
1217 #define MCDI_EVENT_AOE_FAULT 0x5
1219 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
1221 #define MCDI_EVENT_AOE_LOAD 0x7
1223 #define MCDI_EVENT_AOE_DMA 0x8
1227 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9
1229 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
1231 #define MCDI_EVENT_AOE_PTP_STATUS 0xb
1233 #define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc
1235 #define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd
1237 #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe
1239 #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf
1241 #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10
1243 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11
1245 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12
1247 #define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
1249 #define MCDI_EVENT_AOE_FC_RUNNING 0x14
1250 #define MCDI_EVENT_AOE_ERR_DATA_OFST 0
1253 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 0
1257 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0
1260 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
1261 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0
1265 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0
1267 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1
1269 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2
1271 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3
1273 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4
1275 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5
1277 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6
1279 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
1281 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
1282 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 0
1286 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
1288 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
1289 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 0
1292 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 0
1295 #define MCDI_EVENT_RX_ERR_RXQ_OFST 0
1296 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0
1298 #define MCDI_EVENT_RX_ERR_TYPE_OFST 0
1301 #define MCDI_EVENT_RX_ERR_INFO_OFST 0
1304 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 0
1307 #define MCDI_EVENT_RX_FLUSH_RXQ_OFST 0
1308 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
1310 #define MCDI_EVENT_MC_REBOOT_COUNT_OFST 0
1311 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
1313 #define MCDI_EVENT_MUM_ERR_TYPE_OFST 0
1314 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0
1317 #define MCDI_EVENT_MUM_NO_LOAD 0x1
1319 #define MCDI_EVENT_MUM_ASSERT 0x2
1321 #define MCDI_EVENT_MUM_WATCHDOG 0x3
1322 #define MCDI_EVENT_MUM_ERR_DATA_OFST 0
1325 #define MCDI_EVENT_DBRET_SEQ_OFST 0
1326 #define MCDI_EVENT_DBRET_SEQ_LBN 0
1328 #define MCDI_EVENT_SUC_ERR_TYPE_OFST 0
1329 #define MCDI_EVENT_SUC_ERR_TYPE_LBN 0
1332 #define MCDI_EVENT_SUC_BAD_APP 0x1
1334 #define MCDI_EVENT_SUC_ASSERT 0x2
1336 #define MCDI_EVENT_SUC_EXCEPTION 0x3
1338 #define MCDI_EVENT_SUC_WATCHDOG 0x4
1339 #define MCDI_EVENT_SUC_ERR_ADDRESS_OFST 0
1342 #define MCDI_EVENT_SUC_ERR_DATA_OFST 0
1345 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 0
1346 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 0
1348 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 0
1353 #define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 0
1356 #define MCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 0
1361 #define MCDI_EVENT_MODULECHANGE_LD_CAP_OFST 0
1362 #define MCDI_EVENT_MODULECHANGE_LD_CAP_LBN 0
1364 #define MCDI_EVENT_MODULECHANGE_SEQ_OFST 0
1367 #define MCDI_EVENT_DATA_LBN 0
1386 #define MCDI_EVENT_SW_EVENT 0x0
1388 #define MCDI_EVENT_CODE_BADSSERT 0x1
1390 #define MCDI_EVENT_CODE_PMNOTICE 0x2
1392 #define MCDI_EVENT_CODE_CMDDONE 0x3
1394 #define MCDI_EVENT_CODE_LINKCHANGE 0x4
1396 #define MCDI_EVENT_CODE_SENSOREVT 0x5
1398 #define MCDI_EVENT_CODE_SCHEDERR 0x6
1400 #define MCDI_EVENT_CODE_REBOOT 0x7
1402 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
1404 #define MCDI_EVENT_CODE_FWALERT 0x9
1406 #define MCDI_EVENT_CODE_FLR 0xa
1408 #define MCDI_EVENT_CODE_TX_ERR 0xb
1410 #define MCDI_EVENT_CODE_TX_FLUSH 0xc
1412 #define MCDI_EVENT_CODE_PTP_RX 0xd
1414 #define MCDI_EVENT_CODE_PTP_FAULT 0xe
1416 #define MCDI_EVENT_CODE_PTP_PPS 0xf
1418 #define MCDI_EVENT_CODE_RX_FLUSH 0x10
1420 #define MCDI_EVENT_CODE_RX_ERR 0x11
1422 #define MCDI_EVENT_CODE_AOE 0x12
1424 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13
1426 #define MCDI_EVENT_CODE_HW_PPS 0x14
1430 #define MCDI_EVENT_CODE_MC_REBOOT 0x15
1432 #define MCDI_EVENT_CODE_PAR_ERR 0x16
1434 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
1436 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
1438 #define MCDI_EVENT_CODE_MC_BIST 0x19
1440 #define MCDI_EVENT_CODE_PTP_TIME 0x1a
1442 #define MCDI_EVENT_CODE_MUM 0x1b
1444 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
1448 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
1452 #define MCDI_EVENT_CODE_DBRET 0x1e
1454 #define MCDI_EVENT_CODE_SUC 0x1f
1458 #define MCDI_EVENT_CODE_LINKCHANGE_V2 0x20
1463 #define MCDI_EVENT_CODE_MODULECHANGE 0x21
1469 #define MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x22
1475 #define MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23
1482 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x24
1487 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x25
1491 * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0
1492 * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy
1496 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x26
1502 #define MCDI_EVENT_CODE_MPORT_JOURNAL_CHANGE 0x27
1506 #define MCDI_EVENT_CODE_TESTGEN 0xfa
1507 #define MCDI_EVENT_CMDDONE_DATA_OFST 0
1509 #define MCDI_EVENT_CMDDONE_DATA_LBN 0
1511 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
1513 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
1515 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0
1517 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0
1519 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
1521 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
1523 #define MCDI_EVENT_TX_ERR_DATA_OFST 0
1525 #define MCDI_EVENT_TX_ERR_DATA_LBN 0
1530 #define MCDI_EVENT_PTP_SECONDS_OFST 0
1532 #define MCDI_EVENT_PTP_SECONDS_LBN 0
1537 #define MCDI_EVENT_PTP_MAJOR_OFST 0
1539 #define MCDI_EVENT_PTP_MAJOR_LBN 0
1544 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
1546 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
1551 #define MCDI_EVENT_PTP_MINOR_OFST 0
1553 #define MCDI_EVENT_PTP_MINOR_LBN 0
1557 #define MCDI_EVENT_PTP_UUID_OFST 0
1559 #define MCDI_EVENT_PTP_UUID_LBN 0
1561 #define MCDI_EVENT_RX_ERR_DATA_OFST 0
1563 #define MCDI_EVENT_RX_ERR_DATA_LBN 0
1565 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0
1567 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0
1569 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
1571 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
1573 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
1575 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
1578 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
1580 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
1610 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
1612 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
1614 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
1616 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
1624 #define MCDI_EVENT_DBRET_DATA_OFST 0
1626 #define MCDI_EVENT_DBRET_DATA_LBN 0
1628 #define MCDI_EVENT_LINKCHANGE_V2_DATA_OFST 0
1630 #define MCDI_EVENT_LINKCHANGE_V2_DATA_LBN 0
1632 #define MCDI_EVENT_MODULECHANGE_DATA_OFST 0
1634 #define MCDI_EVENT_MODULECHANGE_DATA_LBN 0
1637 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 0
1639 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 0
1642 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 0
1644 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 0
1647 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 0
1649 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 0
1654 #define MCDI_EVENT_DESC_PROXY_DATA_OFST 0
1656 #define MCDI_EVENT_DESC_PROXY_DATA_LBN 0
1659 #define MCDI_EVENT_DESC_PROXY_GENERATION_OFST 0
1661 #define MCDI_EVENT_DESC_PROXY_GENERATION_LBN 0
1664 * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63.
1666 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 0
1668 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0
1678 #define FCDI_EVENT_LEVEL_INFO 0x0
1680 #define FCDI_EVENT_LEVEL_WARN 0x1
1682 #define FCDI_EVENT_LEVEL_ERR 0x2
1684 #define FCDI_EVENT_LEVEL_FATAL 0x3
1685 #define FCDI_EVENT_DATA_OFST 0
1687 #define FCDI_EVENT_LINK_STATE_STATUS_OFST 0
1688 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0
1690 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */
1691 #define FCDI_EVENT_LINK_UP 0x1 /* enum */
1692 #define FCDI_EVENT_DATA_LBN 0
1701 #define FCDI_EVENT_CODE_REBOOT 0x1
1703 #define FCDI_EVENT_CODE_ASSERT 0x2
1705 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
1707 #define FCDI_EVENT_CODE_LINK_STATE 0x4
1709 #define FCDI_EVENT_CODE_TIMED_READ 0x5
1711 #define FCDI_EVENT_CODE_PPS_IN 0x6
1713 #define FCDI_EVENT_CODE_PTP_TICK 0x7
1715 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8
1717 #define FCDI_EVENT_CODE_PTP_STATUS 0x9
1719 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa
1721 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb
1724 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */
1725 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */
1726 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
1728 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
1734 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
1736 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
1738 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0
1740 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0
1742 #define FCDI_EVENT_PTP_STATE_OFST 0
1744 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */
1745 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */
1746 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */
1747 #define FCDI_EVENT_PTP_STATE_LBN 0
1751 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
1753 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
1759 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0
1761 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0
1763 #define FCDI_EVENT_BOOT_RESULT_OFST 0
1767 #define FCDI_EVENT_BOOT_RESULT_LBN 0
1782 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
1784 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
1820 #define MUM_EVENT_LEVEL_INFO 0x0
1822 #define MUM_EVENT_LEVEL_WARN 0x1
1824 #define MUM_EVENT_LEVEL_ERR 0x2
1826 #define MUM_EVENT_LEVEL_FATAL 0x3
1827 #define MUM_EVENT_DATA_OFST 0
1829 #define MUM_EVENT_SENSOR_ID_OFST 0
1830 #define MUM_EVENT_SENSOR_ID_LBN 0
1834 #define MUM_EVENT_SENSOR_STATE_OFST 0
1837 #define MUM_EVENT_PORT_PHY_READY_OFST 0
1838 #define MUM_EVENT_PORT_PHY_READY_LBN 0
1840 #define MUM_EVENT_PORT_PHY_LINK_UP_OFST 0
1843 #define MUM_EVENT_PORT_PHY_TX_LOL_OFST 0
1846 #define MUM_EVENT_PORT_PHY_RX_LOL_OFST 0
1849 #define MUM_EVENT_PORT_PHY_TX_LOS_OFST 0
1852 #define MUM_EVENT_PORT_PHY_RX_LOS_OFST 0
1855 #define MUM_EVENT_PORT_PHY_TX_FAULT_OFST 0
1858 #define MUM_EVENT_DATA_LBN 0
1867 #define MUM_EVENT_CODE_REBOOT 0x1
1869 #define MUM_EVENT_CODE_ASSERT 0x2
1871 #define MUM_EVENT_CODE_SENSOR 0x3
1873 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4
1874 #define MUM_EVENT_SENSOR_DATA_OFST 0
1876 #define MUM_EVENT_SENSOR_DATA_LBN 0
1878 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0
1880 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0
1882 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0
1884 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0
1886 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0
1888 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0
1890 #define MUM_EVENT_PORT_PHY_TECH_OFST 0
1892 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */
1893 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */
1894 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */
1895 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */
1896 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */
1897 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */
1898 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */
1899 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */
1900 #define MUM_EVENT_PORT_PHY_TECH_LBN 0
1904 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */
1905 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */
1906 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */
1907 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */
1908 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */
1919 #define MC_CMD_READ32 0x1
1926 #define MC_CMD_READ32_IN_ADDR_OFST 0
1935 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1936 #define MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
1937 #define MC_CMD_READ32_OUT_BUFFER_OFST 0
1948 #define MC_CMD_WRITE32 0x2
1959 #define MC_CMD_WRITE32_IN_ADDR_OFST 0
1968 #define MC_CMD_WRITE32_OUT_LEN 0
1977 #define MC_CMD_COPYCODE 0x3
1990 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
1993 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000
1997 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
2002 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
2003 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_OFST 0
2006 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_OFST 0
2009 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_OFST 0
2012 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_OFST 0
2015 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_OFST 0
2018 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_OFST 0
2030 #define MC_CMD_COPYCODE_JUMP_NONE 0x1
2033 #define MC_CMD_COPYCODE_OUT_LEN 0
2040 #define MC_CMD_SET_FUNC 0x4
2048 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0
2052 #define MC_CMD_SET_FUNC_OUT_LEN 0
2059 #define MC_CMD_GET_BOOT_STATUS 0x5
2065 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
2070 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
2073 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
2077 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
2093 #define MC_CMD_GET_ASSERTS 0x6
2101 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
2107 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
2110 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
2112 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
2114 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
2116 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
2118 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
2129 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
2141 #define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 0
2144 /* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
2146 /* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
2148 /* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
2150 /* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
2152 /* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
2163 /* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
2179 #define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 0
2182 /* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
2184 /* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
2186 /* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
2188 /* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
2190 /* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
2201 /* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
2252 #define MC_CMD_LOG_CTRL 0x7
2260 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
2263 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
2265 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
2271 #define MC_CMD_LOG_CTRL_OUT_LEN 0
2278 #define MC_CMD_GET_VERSION 0x8
2284 #define MC_CMD_GET_VERSION_IN_LEN 0
2288 /* placeholder, set to 0 */
2289 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
2294 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
2297 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
2299 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
2301 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
2303 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002
2307 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2329 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2359 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2385 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2472 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2498 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2524 #define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2611 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2644 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2670 #define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2757 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2806 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2832 #define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2919 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2963 /* Board version as four numbers - a.b.c.d. BOARD_VERSION[0] duplicates the
2979 #define MC_CMD_PTP 0xb
2987 #define MC_CMD_PTP_IN_OP_OFST 0
2990 #define MC_CMD_PTP_OP_ENABLE 0x1
2992 #define MC_CMD_PTP_OP_DISABLE 0x2
2997 #define MC_CMD_PTP_OP_TRANSMIT 0x3
2999 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4
3003 #define MC_CMD_PTP_OP_STATUS 0x5
3005 #define MC_CMD_PTP_OP_ADJUST 0x6
3007 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7
3009 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
3011 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
3013 #define MC_CMD_PTP_OP_RESET_STATS 0xa
3015 #define MC_CMD_PTP_OP_DEBUG 0xb
3017 #define MC_CMD_PTP_OP_FPGAREAD 0xc
3019 #define MC_CMD_PTP_OP_FPGAWRITE 0xd
3021 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
3023 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
3027 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
3031 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
3035 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
3039 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13
3041 #define MC_CMD_PTP_OP_RST_CLK 0x14
3043 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15
3045 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
3049 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
3053 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
3057 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
3059 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
3063 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
3067 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
3069 #define MC_CMD_PTP_OP_MAX 0x1c
3073 #define MC_CMD_PTP_IN_CMD_OFST 0
3077 /* Not used, initialize to 0. Events are always sent to function relative queue
3078 * 0.
3086 #define MC_CMD_PTP_MODE_V1 0x0
3088 #define MC_CMD_PTP_MODE_V1_VLAN 0x1
3090 #define MC_CMD_PTP_MODE_V2 0x2
3092 #define MC_CMD_PTP_MODE_V2_VLAN 0x3
3094 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4
3096 #define MC_CMD_PTP_MODE_FCOE 0x5
3100 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3111 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3127 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3134 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3141 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3148 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3164 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28
3169 #define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c
3185 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3201 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
3206 /* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */
3225 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3248 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3255 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3265 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3272 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3282 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3297 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3311 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3330 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3352 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3372 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3376 /* Number of VLAN tags, 0 if not VLAN */
3386 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3390 /* 1 to enable UUID filtering, 0 to disable */
3407 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3411 /* 1 to enable Domain filtering, 0 to disable */
3420 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3428 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
3430 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
3434 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3441 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3447 #define MC_CMD_PTP_ENABLE_PPS 0x0
3449 #define MC_CMD_PTP_DISABLE_PPS 0x1
3450 /* Not used, initialize to 0. Events are always sent to function relative queue
3451 * 0.
3458 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3465 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3472 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3479 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3487 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
3495 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3503 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
3505 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
3512 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3516 /* 1 to enable PPS test mode, 0 to disable and return result. */
3522 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3530 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
3532 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
3544 #define MC_CMD_PTP_OUT_LEN 0
3549 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
3552 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
3562 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
3565 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
3570 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
3573 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
3585 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0
3588 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0
3603 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
3655 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
3656 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)
3658 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
3664 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
3688 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
3691 #define MC_CMD_PTP_MANF_SUCCESS 0x0
3693 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1
3695 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2
3697 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
3699 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4
3701 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5
3703 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6
3705 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7
3707 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
3709 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
3711 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
3713 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb
3715 #define MC_CMD_PTP_MANF_PPS_NS 0xc
3717 #define MC_CMD_PTP_MANF_REGISTERS 0xd
3719 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe
3727 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
3740 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
3741 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)
3742 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
3756 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
3759 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
3761 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
3763 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
3772 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
3775 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
3777 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
3779 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
3782 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3
3796 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
3821 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_OFST 0
3824 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_NANOSECONDS 0x0
3826 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_16SECONDS_8NANOSECONDS 0x1
3828 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_27FRACTION 0x2
3831 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_QTR_NANOSECONDS 0x3
3845 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_LBN 0
3898 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
3913 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0
3934 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
3940 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0
3947 #define MC_CMD_CSR_READ32 0xc
3955 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0
3966 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
3967 #define MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
3969 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
3980 #define MC_CMD_CSR_WRITE32 0xd
3992 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
4004 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
4013 #define MC_CMD_HP 0x54
4022 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
4026 #define MC_CMD_HP_IN_SUBCMD_OFST 0
4029 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0
4031 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0
4052 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
4055 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1
4057 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2
4059 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3
4066 #define MC_CMD_STACKINFO 0xf
4072 #define MC_CMD_STACKINFO_IN_LEN 0
4078 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
4079 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12)
4081 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
4092 #define MC_CMD_MDIO_READ 0x10
4102 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0
4105 #define MC_CMD_MDIO_BUS_INTERNAL 0x0
4107 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1
4117 #define MC_CMD_MDIO_CLAUSE22 0x20
4125 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
4133 #define MC_CMD_MDIO_STATUS_GOOD 0x8
4140 #define MC_CMD_MDIO_WRITE 0x11
4150 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
4153 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */
4155 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
4165 /* MC_CMD_MDIO_CLAUSE22 0x20 */
4178 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
4181 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */
4188 #define MC_CMD_DBI_WRITE 0x12
4197 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
4198 #define MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12)
4199 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
4202 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
4209 #define MC_CMD_DBI_WRITE_OUT_LEN 0
4213 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
4215 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
4241 #define MC_CMD_PORT_READ32 0x14
4246 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0
4252 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
4264 #define MC_CMD_PORT_WRITE32 0x15
4269 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
4278 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
4287 #define MC_CMD_PORT_READ128 0x16
4292 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0
4298 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
4310 #define MC_CMD_PORT_WRITE128 0x17
4315 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
4324 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
4330 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0
4358 #define MC_CMD_GET_BOARD_CFG 0x18
4364 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0
4372 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
4433 #define MC_CMD_DBI_READX 0x19
4442 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
4443 #define MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8)
4444 /* Each Read op consists of an address (offset 0), VF/CS2) */
4445 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
4447 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
4449 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LBN 0
4463 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
4464 #define MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4)
4466 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0
4474 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0
4476 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0
4497 #define MC_CMD_SET_RAND_SEED 0x1a
4505 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
4509 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0
4516 #define MC_CMD_LTSSM_HIST 0x1b
4519 #define MC_CMD_LTSSM_HIST_IN_LEN 0
4522 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0
4525 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
4526 #define MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4)
4528 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
4530 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
4544 #define MC_CMD_DRV_ATTACH 0x1c
4552 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
4554 #define MC_CMD_DRV_ATTACH_OFST 0
4555 #define MC_CMD_DRV_ATTACH_LBN 0
4557 #define MC_CMD_DRV_ATTACH_IN_ATTACH_OFST 0
4558 #define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
4560 #define MC_CMD_DRV_PREBOOT_OFST 0
4563 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 0
4566 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 0
4569 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 0
4572 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 0
4575 #define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
4578 #define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 0
4581 /* 1 to set new state, or 0 to just report the existing state */
4588 #define MC_CMD_FW_FULL_FEATURED 0x0
4590 #define MC_CMD_FW_LOW_LATENCY 0x1
4592 #define MC_CMD_FW_PACKED_STREAM 0x2
4596 #define MC_CMD_FW_HIGH_TX_RATE 0x3
4598 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
4602 #define MC_CMD_FW_RULES_ENGINE 0x5
4604 #define MC_CMD_FW_DPDK 0x6
4608 #define MC_CMD_FW_L3XUDP 0x7
4614 #define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe
4616 #define MC_CMD_FW_DONT_CARE 0xffffffff
4623 #define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 0
4625 /* MC_CMD_DRV_ATTACH_OFST 0 */
4626 /* MC_CMD_DRV_ATTACH_LBN 0 */
4628 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 0
4629 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 0
4631 /* MC_CMD_DRV_PREBOOT_OFST 0 */
4634 #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 0
4637 #define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 0
4640 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 0
4643 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 0
4646 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
4649 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 0
4652 /* 1 to set new state, or 0 to just report the existing state */
4659 /* MC_CMD_FW_FULL_FEATURED 0x0 */
4661 /* MC_CMD_FW_LOW_LATENCY 0x1 */
4663 /* MC_CMD_FW_PACKED_STREAM 0x2 */
4667 /* MC_CMD_FW_HIGH_TX_RATE 0x3 */
4669 /* MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 */
4673 /* MC_CMD_FW_RULES_ENGINE 0x5 */
4675 /* MC_CMD_FW_DPDK 0x6 */
4679 /* MC_CMD_FW_L3XUDP 0x7 */
4685 /* MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe */
4687 /* MC_CMD_FW_DONT_CARE 0xffffffff */
4697 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
4703 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
4709 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
4713 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
4715 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
4719 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
4724 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
4726 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x5
4731 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x5
4738 #define MC_CMD_SHMUART 0x1f
4743 #define MC_CMD_SHMUART_IN_FLAG_OFST 0
4747 #define MC_CMD_SHMUART_OUT_LEN 0
4753 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
4756 #define MC_CMD_PORT_RESET 0x20
4762 #define MC_CMD_PORT_RESET_IN_LEN 0
4765 #define MC_CMD_PORT_RESET_OUT_LEN 0
4771 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
4774 #define MC_CMD_ENTITY_RESET 0x20
4782 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
4784 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_OFST 0
4785 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
4789 #define MC_CMD_ENTITY_RESET_OUT_LEN 0
4796 #define MC_CMD_PCIE_CREDITS 0x21
4800 /* poll period. 0 is disabled */
4801 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
4809 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
4831 #define MC_CMD_RXD_MONITOR 0x22
4835 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0
4844 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
4890 #define MC_CMD_PUTS 0x23
4901 #define MC_CMD_PUTS_IN_DEST_OFST 0
4903 #define MC_CMD_PUTS_IN_UART_OFST 0
4904 #define MC_CMD_PUTS_IN_UART_LBN 0
4906 #define MC_CMD_PUTS_IN_PORT_OFST 0
4918 #define MC_CMD_PUTS_OUT_LEN 0
4926 #define MC_CMD_GET_PHY_CFG 0x24
4932 #define MC_CMD_GET_PHY_CFG_IN_LEN 0
4937 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
4939 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_OFST 0
4940 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
4942 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_OFST 0
4945 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_OFST 0
4948 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_OFST 0
4951 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_OFST 0
4954 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_OFST 0
4957 #define MC_CMD_GET_PHY_CFG_OUT_BIST_OFST 0
5045 #define MC_CMD_MEDIA_XAUI 0x1
5047 #define MC_CMD_MEDIA_CX4 0x2
5049 #define MC_CMD_MEDIA_KX4 0x3
5051 #define MC_CMD_MEDIA_XFP 0x4
5053 #define MC_CMD_MEDIA_SFP_PLUS 0x5
5055 #define MC_CMD_MEDIA_BASE_T 0x6
5057 #define MC_CMD_MEDIA_QSFP_PLUS 0x7
5059 #define MC_CMD_MEDIA_DSFP 0x8
5063 #define MC_CMD_MMD_CLAUSE22 0x0
5064 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
5065 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
5066 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
5067 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
5068 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
5069 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
5070 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
5072 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
5073 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
5074 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
5082 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
5084 #define MC_CMD_START_BIST 0x25
5092 #define MC_CMD_START_BIST_IN_TYPE_OFST 0
5095 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1
5097 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2
5099 #define MC_CMD_BPX_SERDES_BIST 0x3
5101 #define MC_CMD_MC_LOOPBACK_BIST 0x4
5103 #define MC_CMD_PHY_BIST 0x5
5105 #define MC_CMD_MC_MEM_BIST 0x6
5107 #define MC_CMD_PORT_MEM_BIST 0x7
5109 #define MC_CMD_REG_BIST 0x8
5112 #define MC_CMD_START_BIST_OUT_LEN 0
5121 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
5124 #define MC_CMD_POLL_BIST 0x26
5130 #define MC_CMD_POLL_BIST_IN_LEN 0
5135 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
5138 #define MC_CMD_POLL_BIST_RUNNING 0x1
5140 #define MC_CMD_POLL_BIST_PASSED 0x2
5142 #define MC_CMD_POLL_BIST_FAILED 0x3
5144 #define MC_CMD_POLL_BIST_TIMEOUT 0x4
5151 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
5167 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
5169 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
5171 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
5173 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
5175 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
5195 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
5202 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
5204 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
5206 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
5208 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
5210 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
5212 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
5214 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
5216 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
5218 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
5223 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
5230 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
5232 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
5234 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
5236 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
5238 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
5240 #define MC_CMD_POLL_BIST_MEM_REG 0x5
5242 #define MC_CMD_POLL_BIST_MEM_ECC 0x6
5250 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
5252 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
5254 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
5256 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
5258 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
5260 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
5262 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
5264 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7
5266 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8
5293 #define MC_CMD_FLUSH_RX_QUEUES 0x27
5299 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
5300 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4)
5301 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
5308 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
5315 #define MC_CMD_GET_LOOPBACK_MODES 0x28
5321 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
5326 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
5328 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
5330 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LBN 0
5337 #define MC_CMD_LOOPBACK_NONE 0x0
5339 #define MC_CMD_LOOPBACK_DATA 0x1
5341 #define MC_CMD_LOOPBACK_GMAC 0x2
5343 #define MC_CMD_LOOPBACK_XGMII 0x3
5345 #define MC_CMD_LOOPBACK_XGXS 0x4
5347 #define MC_CMD_LOOPBACK_XAUI 0x5
5349 #define MC_CMD_LOOPBACK_GMII 0x6
5351 #define MC_CMD_LOOPBACK_SGMII 0x7
5353 #define MC_CMD_LOOPBACK_XGBR 0x8
5355 #define MC_CMD_LOOPBACK_XFI 0x9
5357 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa
5359 #define MC_CMD_LOOPBACK_GMII_FAR 0xb
5361 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc
5363 #define MC_CMD_LOOPBACK_XFI_FAR 0xd
5365 #define MC_CMD_LOOPBACK_GPHY 0xe
5367 #define MC_CMD_LOOPBACK_PHYXS 0xf
5369 #define MC_CMD_LOOPBACK_PCS 0x10
5371 #define MC_CMD_LOOPBACK_PMAPMD 0x11
5373 #define MC_CMD_LOOPBACK_XPORT 0x12
5375 #define MC_CMD_LOOPBACK_XGMII_WS 0x13
5377 #define MC_CMD_LOOPBACK_XAUI_WS 0x14
5379 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
5381 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
5383 #define MC_CMD_LOOPBACK_GMII_WS 0x17
5385 #define MC_CMD_LOOPBACK_XFI_WS 0x18
5387 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
5389 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
5391 #define MC_CMD_LOOPBACK_PMA_INT 0x1b
5393 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c
5395 #define MC_CMD_LOOPBACK_SD_FAR 0x1d
5397 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
5399 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
5401 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
5403 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
5405 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22
5407 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
5409 #define MC_CMD_LOOPBACK_DATA_WS 0x24
5413 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
5472 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
5474 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
5476 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LBN 0
5483 /* MC_CMD_LOOPBACK_NONE 0x0 */
5485 /* MC_CMD_LOOPBACK_DATA 0x1 */
5487 /* MC_CMD_LOOPBACK_GMAC 0x2 */
5489 /* MC_CMD_LOOPBACK_XGMII 0x3 */
5491 /* MC_CMD_LOOPBACK_XGXS 0x4 */
5493 /* MC_CMD_LOOPBACK_XAUI 0x5 */
5495 /* MC_CMD_LOOPBACK_GMII 0x6 */
5497 /* MC_CMD_LOOPBACK_SGMII 0x7 */
5499 /* MC_CMD_LOOPBACK_XGBR 0x8 */
5501 /* MC_CMD_LOOPBACK_XFI 0x9 */
5503 /* MC_CMD_LOOPBACK_XAUI_FAR 0xa */
5505 /* MC_CMD_LOOPBACK_GMII_FAR 0xb */
5507 /* MC_CMD_LOOPBACK_SGMII_FAR 0xc */
5509 /* MC_CMD_LOOPBACK_XFI_FAR 0xd */
5511 /* MC_CMD_LOOPBACK_GPHY 0xe */
5513 /* MC_CMD_LOOPBACK_PHYXS 0xf */
5515 /* MC_CMD_LOOPBACK_PCS 0x10 */
5517 /* MC_CMD_LOOPBACK_PMAPMD 0x11 */
5519 /* MC_CMD_LOOPBACK_XPORT 0x12 */
5521 /* MC_CMD_LOOPBACK_XGMII_WS 0x13 */
5523 /* MC_CMD_LOOPBACK_XAUI_WS 0x14 */
5525 /* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
5527 /* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
5529 /* MC_CMD_LOOPBACK_GMII_WS 0x17 */
5531 /* MC_CMD_LOOPBACK_XFI_WS 0x18 */
5533 /* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
5535 /* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
5537 /* MC_CMD_LOOPBACK_PMA_INT 0x1b */
5539 /* MC_CMD_LOOPBACK_SD_NEAR 0x1c */
5541 /* MC_CMD_LOOPBACK_SD_FAR 0x1d */
5543 /* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
5545 /* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
5547 /* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
5549 /* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
5551 /* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
5553 /* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
5555 /* MC_CMD_LOOPBACK_DATA_WS 0x24 */
5559 /* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
5654 #define AN_TYPE_TYPE_OFST 0
5657 #define MC_CMD_AN_NONE 0x0
5659 #define MC_CMD_AN_CLAUSE28 0x1
5661 #define MC_CMD_AN_CLAUSE37 0x2
5665 #define MC_CMD_AN_CLAUSE73 0x3
5666 #define AN_TYPE_TYPE_LBN 0
5672 #define FEC_TYPE_TYPE_OFST 0
5675 #define MC_CMD_FEC_NONE 0x0
5677 #define MC_CMD_FEC_BASER 0x1
5679 #define MC_CMD_FEC_RS 0x2
5680 #define FEC_TYPE_TYPE_LBN 0
5686 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
5689 #define MC_CMD_GET_LINK 0x29
5695 #define MC_CMD_GET_LINK_IN_LEN 0
5702 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0
5722 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
5753 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
5770 #define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0
5790 #define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0
5821 /* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */
5835 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal
5854 #define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0
5888 * code: 0, EINVAL, ETIME, EAGAIN
5890 #define MC_CMD_SET_LINK 0x2a
5900 #define MC_CMD_SET_LINK_IN_CAP_OFST 0
5906 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
5922 /* A loopback speed of "0" is supported, and means (choose any available
5936 #define MC_CMD_SET_LINK_IN_V2_CAP_OFST 0
5942 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_LBN 0
5958 /* A loopback speed of "0" is supported, and means (choose any available
5966 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_LBN 0
5973 #define MC_CMD_SET_LINK_OUT_LEN 0
5978 * Set identification LED state. Locks required: None. Return code: 0, EINVAL
5980 #define MC_CMD_SET_ID_LED 0x2b
5988 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
5990 #define MC_CMD_LED_OFF 0x0 /* enum */
5991 #define MC_CMD_LED_ON 0x1 /* enum */
5992 #define MC_CMD_LED_DEFAULT 0x2 /* enum */
5995 #define MC_CMD_SET_ID_LED_OUT_LEN 0
6000 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
6002 #define MC_CMD_SET_MAC 0x2c
6012 #define MC_CMD_SET_MAC_IN_MTU_OFST 0
6029 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
6037 #define MC_CMD_FCNTL_OFF 0x0
6039 #define MC_CMD_FCNTL_RESPOND 0x1
6041 #define MC_CMD_FCNTL_BIDIR 0x2
6043 #define MC_CMD_FCNTL_AUTO 0x3
6045 #define MC_CMD_FCNTL_QBB 0x4
6047 #define MC_CMD_FCNTL_GENERATE 0x5
6051 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
6059 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
6076 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
6084 /* MC_CMD_FCNTL_OFF 0x0 */
6086 /* MC_CMD_FCNTL_RESPOND 0x1 */
6088 /* MC_CMD_FCNTL_BIDIR 0x2 */
6090 /* MC_CMD_FCNTL_AUTO 0x3 */
6092 /* MC_CMD_FCNTL_QBB 0x4 */
6094 /* MC_CMD_FCNTL_GENERATE 0x5 */
6098 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
6108 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
6128 #define MC_CMD_SET_MAC_V3_IN_MTU_OFST 0
6145 #define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_LBN 0
6153 /* MC_CMD_FCNTL_OFF 0x0 */
6155 /* MC_CMD_FCNTL_RESPOND 0x1 */
6157 /* MC_CMD_FCNTL_BIDIR 0x2 */
6159 /* MC_CMD_FCNTL_AUTO 0x3 */
6161 /* MC_CMD_FCNTL_QBB 0x4 */
6163 /* MC_CMD_FCNTL_GENERATE 0x5 */
6167 #define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_LBN 0
6177 #define MC_CMD_SET_MAC_V3_IN_CFG_MTU_LBN 0
6247 #define MC_CMD_SET_MAC_OUT_LEN 0
6253 * to 0.
6255 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
6263 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
6264 * statistics may be read from the message response. If DMA_ADDR != 0, then the
6266 * Returns: 0, ETIME
6268 #define MC_CMD_PHY_STATS 0x2d
6276 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
6278 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
6280 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LBN 0
6288 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
6292 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
6296 #define MC_CMD_OUI 0x0
6298 #define MC_CMD_PMA_PMD_LINK_UP 0x1
6300 #define MC_CMD_PMA_PMD_RX_FAULT 0x2
6302 #define MC_CMD_PMA_PMD_TX_FAULT 0x3
6304 #define MC_CMD_PMA_PMD_SIGNAL 0x4
6306 #define MC_CMD_PMA_PMD_SNR_A 0x5
6308 #define MC_CMD_PMA_PMD_SNR_B 0x6
6310 #define MC_CMD_PMA_PMD_SNR_C 0x7
6312 #define MC_CMD_PMA_PMD_SNR_D 0x8
6314 #define MC_CMD_PCS_LINK_UP 0x9
6316 #define MC_CMD_PCS_RX_FAULT 0xa
6318 #define MC_CMD_PCS_TX_FAULT 0xb
6320 #define MC_CMD_PCS_BER 0xc
6322 #define MC_CMD_PCS_BLOCK_ERRORS 0xd
6324 #define MC_CMD_PHYXS_LINK_UP 0xe
6326 #define MC_CMD_PHYXS_RX_FAULT 0xf
6328 #define MC_CMD_PHYXS_TX_FAULT 0x10
6330 #define MC_CMD_PHYXS_ALIGN 0x11
6332 #define MC_CMD_PHYXS_SYNC 0x12
6334 #define MC_CMD_AN_LINK_UP 0x13
6336 #define MC_CMD_AN_COMPLETE 0x14
6338 #define MC_CMD_AN_10GBT_STATUS 0x15
6340 #define MC_CMD_CL22_LINK_UP 0x16
6342 #define MC_CMD_PHY_NSTATS 0x17
6350 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
6352 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
6354 * effect. Returns: 0, ETIME
6356 #define MC_CMD_MAC_STATS 0x2e
6364 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
6366 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
6368 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LBN 0
6377 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0
6409 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
6413 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
6415 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
6417 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LBN 0
6424 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
6425 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
6426 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
6427 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
6428 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
6429 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
6430 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
6431 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
6432 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
6433 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
6434 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
6435 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
6436 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
6437 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
6438 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
6439 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
6440 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
6441 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
6442 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
6443 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
6444 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
6445 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
6446 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
6447 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
6448 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
6449 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
6450 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
6451 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
6452 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
6453 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
6454 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
6455 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
6456 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
6457 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
6458 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
6459 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
6460 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
6461 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
6462 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
6463 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
6464 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
6465 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
6466 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
6467 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
6468 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
6469 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
6470 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
6471 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
6472 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
6473 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
6474 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
6475 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
6476 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
6477 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
6478 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
6479 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
6480 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
6481 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
6482 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
6483 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
6484 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
6488 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
6492 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
6496 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
6500 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
6504 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40
6508 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41
6512 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
6516 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
6520 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
6524 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
6528 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
6532 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
6533 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
6534 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
6535 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
6536 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
6537 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
6538 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
6539 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
6540 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
6541 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
6542 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
6543 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
6544 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
6545 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
6546 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
6547 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
6548 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
6549 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
6550 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
6551 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
6552 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
6554 #define MC_CMD_GMAC_DMABUF_START 0x40
6556 #define MC_CMD_GMAC_DMABUF_END 0x5f
6567 #define MC_CMD_MAC_GENERATION_END 0x60
6568 #define MC_CMD_MAC_NSTATS 0x61 /* enum */
6571 #define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0
6575 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
6577 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
6579 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LBN 0
6587 #define MC_CMD_MAC_FEC_DMABUF_START 0x61
6590 #define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
6593 #define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
6594 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
6595 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
6597 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
6599 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
6601 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
6605 #define MC_CMD_MAC_NSTATS_V2 0x68
6610 #define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0
6614 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
6616 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
6618 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LBN 0
6626 #define MC_CMD_MAC_CTPIO_DMABUF_START 0x68
6630 #define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
6634 #define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
6638 #define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
6640 #define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
6644 #define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
6648 #define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
6652 #define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
6656 #define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
6660 #define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
6664 #define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
6667 #define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
6671 #define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
6673 #define MC_CMD_MAC_CTPIO_SUCCESS 0x74
6675 #define MC_CMD_MAC_CTPIO_FALLBACK 0x75
6679 #define MC_CMD_MAC_CTPIO_POISON 0x76
6681 #define MC_CMD_MAC_CTPIO_ERASE 0x77
6685 #define MC_CMD_MAC_NSTATS_V3 0x79
6690 #define MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 0
6694 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0
6696 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0
6698 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LBN 0
6706 #define MC_CMD_MAC_V4_DMABUF_START 0x79
6710 #define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79
6714 #define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a
6718 #define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b
6722 #define MC_CMD_MAC_NSTATS_V4 0x7d
6731 #define MC_CMD_SRIOV 0x30
6735 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0
6744 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
6752 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
6754 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
6774 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
6808 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and
6813 * Returns: 0, EINVAL (invalid RID)
6815 #define MC_CMD_MEMCPY 0x31
6821 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
6822 #define MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32)
6824 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0
6831 #define MC_CMD_MEMCPY_OUT_LEN 0
6838 #define MC_CMD_WOL_FILTER_SET 0x32
6845 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
6847 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
6848 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
6853 #define MC_CMD_WOL_TYPE_MAGIC 0x0
6855 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
6857 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
6859 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
6861 #define MC_CMD_WOL_TYPE_BITMAP 0x5
6863 #define MC_CMD_WOL_TYPE_LINK 0x6
6865 #define MC_CMD_WOL_TYPE_MAX 0x7
6872 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6889 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6904 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6919 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6936 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6943 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
6951 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
6957 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
6959 #define MC_CMD_WOL_FILTER_REMOVE 0x33
6966 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
6970 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
6975 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
6978 #define MC_CMD_WOL_FILTER_RESET 0x34
6985 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
6987 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
6988 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
6991 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
6998 #define MC_CMD_SET_MCAST_HASH 0x35
7002 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
7008 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0
7014 * Locks required: none. Returns: 0
7016 #define MC_CMD_NVRAM_TYPES 0x36
7022 #define MC_CMD_NVRAM_TYPES_IN_LEN 0
7027 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
7030 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
7032 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1
7034 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
7036 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
7038 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
7040 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
7042 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
7044 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
7046 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
7048 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
7050 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
7052 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
7054 #define MC_CMD_NVRAM_TYPE_LOG 0xc
7056 #define MC_CMD_NVRAM_TYPE_FPGA 0xd
7058 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
7060 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf
7062 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
7064 #define MC_CMD_NVRAM_TYPE_CPLD 0x11
7066 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12
7068 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13
7070 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14
7075 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
7078 #define MC_CMD_NVRAM_INFO 0x37
7085 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
7092 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
7103 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
7130 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0
7141 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
7168 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
7175 #define MC_CMD_NVRAM_UPDATE_START 0x38
7184 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
7195 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0
7202 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
7206 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
7212 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7215 #define MC_CMD_NVRAM_READ 0x39
7222 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
7234 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0
7257 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0
7261 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1
7265 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2
7271 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
7272 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)
7273 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
7283 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7286 #define MC_CMD_NVRAM_WRITE 0x3a
7297 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
7312 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0
7318 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7321 #define MC_CMD_NVRAM_ERASE 0x3b
7328 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
7338 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0
7344 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/
7351 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
7360 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
7373 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0
7382 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
7397 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
7419 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
7424 #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0
7426 #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1
7428 #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2
7430 #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3
7432 #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4
7436 #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5
7438 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6
7440 #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7
7442 #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8
7444 #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9
7446 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa
7450 #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb
7454 #define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
7456 #define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
7460 #define MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe
7462 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf
7465 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10
7469 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11
7473 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12
7477 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13
7481 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14
7485 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15
7489 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16
7491 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17
7495 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18
7499 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19
7501 #define MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a
7517 * REBOOT_ON_ASSERT=0.
7520 * DATALEN=0
7522 #define MC_CMD_REBOOT 0x3d
7529 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0
7531 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
7534 #define MC_CMD_REBOOT_OUT_LEN 0
7543 #define MC_CMD_SCHEDINFO 0x3e
7549 #define MC_CMD_SCHEDINFO_IN_LEN 0
7555 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
7556 #define MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4)
7557 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
7569 #define MC_CMD_REBOOT_MODE 0x3f
7576 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
7579 #define MC_CMD_REBOOT_MODE_NORMAL 0x0
7581 #define MC_CMD_REBOOT_MODE_POR 0x2
7583 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3
7585 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
7586 #define MC_CMD_REBOOT_MODE_IN_FAKE_OFST 0
7592 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
7614 * backward compatibility, older host software can only use sensors in page 0.
7619 * page 0 of sensor information, with bit 31 in the sensor mask cleared.
7625 * Locks required: None Returns: 0
7627 #define MC_CMD_SENSOR_INFO 0x41
7633 #define MC_CMD_SENSOR_INFO_IN_LEN 0
7639 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
7643 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
7650 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
7654 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_OFST 0
7660 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 0
7669 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
7672 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
7674 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
7676 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
7677 /* enum: Phy 0 temperature: degC */
7678 #define MC_CMD_SENSOR_PHY0_TEMP 0x3
7679 /* enum: Phy 0 cooling: bool */
7680 #define MC_CMD_SENSOR_PHY0_COOLING 0x4
7682 #define MC_CMD_SENSOR_PHY1_TEMP 0x5
7684 #define MC_CMD_SENSOR_PHY1_COOLING 0x6
7686 #define MC_CMD_SENSOR_IN_1V0 0x7
7688 #define MC_CMD_SENSOR_IN_1V2 0x8
7690 #define MC_CMD_SENSOR_IN_1V8 0x9
7692 #define MC_CMD_SENSOR_IN_2V5 0xa
7694 #define MC_CMD_SENSOR_IN_3V3 0xb
7696 #define MC_CMD_SENSOR_IN_12V0 0xc
7698 #define MC_CMD_SENSOR_IN_1V2A 0xd
7700 #define MC_CMD_SENSOR_IN_VREF 0xe
7702 #define MC_CMD_SENSOR_OUT_VAOE 0xf
7704 #define MC_CMD_SENSOR_AOE_TEMP 0x10
7706 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
7708 #define MC_CMD_SENSOR_PSU_TEMP 0x12
7709 /* enum: Fan 0 speed: RPM */
7710 #define MC_CMD_SENSOR_FAN_0 0x13
7712 #define MC_CMD_SENSOR_FAN_1 0x14
7714 #define MC_CMD_SENSOR_FAN_2 0x15
7716 #define MC_CMD_SENSOR_FAN_3 0x16
7718 #define MC_CMD_SENSOR_FAN_4 0x17
7720 #define MC_CMD_SENSOR_IN_VAOE 0x18
7722 #define MC_CMD_SENSOR_OUT_IAOE 0x19
7724 #define MC_CMD_SENSOR_IN_IAOE 0x1a
7726 #define MC_CMD_SENSOR_NIC_POWER 0x1b
7728 #define MC_CMD_SENSOR_IN_0V9 0x1c
7730 #define MC_CMD_SENSOR_IN_I0V9 0x1d
7732 #define MC_CMD_SENSOR_IN_I1V2 0x1e
7734 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
7736 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20
7738 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
7740 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
7742 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
7744 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
7746 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
7748 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
7750 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
7752 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
7754 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
7756 #define MC_CMD_SENSOR_AIRFLOW 0x2a
7758 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
7760 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
7762 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
7763 /* enum: Port 0 PHY power switch over-current: bool */
7764 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
7766 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
7768 #define MC_CMD_SENSOR_MUM_VCC 0x30
7770 #define MC_CMD_SENSOR_IN_0V9_A 0x31
7772 #define MC_CMD_SENSOR_IN_I0V9_A 0x32
7774 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
7776 #define MC_CMD_SENSOR_IN_0V9_B 0x34
7778 #define MC_CMD_SENSOR_IN_I0V9_B 0x35
7780 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
7782 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
7784 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
7786 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
7788 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
7790 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
7792 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f
7796 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
7798 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
7802 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
7804 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
7808 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
7810 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
7814 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
7816 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
7818 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49
7819 /* enum: Temperature of SODIMM 0 (if installed): degC */
7820 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
7822 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
7823 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
7824 #define MC_CMD_SENSOR_PHY0_VCC 0x4c
7826 #define MC_CMD_SENSOR_PHY1_VCC 0x4d
7828 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
7830 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
7832 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
7834 #define MC_CMD_SENSOR_IN_I1V8 0x51
7836 #define MC_CMD_SENSOR_IN_I2V5 0x52
7838 #define MC_CMD_SENSOR_IN_I3V3 0x53
7840 #define MC_CMD_SENSOR_IN_I12V0 0x54
7842 #define MC_CMD_SENSOR_IN_1V3 0x55
7844 #define MC_CMD_SENSOR_IN_I1V3 0x56
7846 #define MC_CMD_SENSOR_ENGINEERING_1 0x57
7848 #define MC_CMD_SENSOR_ENGINEERING_2 0x58
7850 #define MC_CMD_SENSOR_ENGINEERING_3 0x59
7852 #define MC_CMD_SENSOR_ENGINEERING_4 0x5a
7854 #define MC_CMD_SENSOR_ENGINEERING_5 0x5b
7856 #define MC_CMD_SENSOR_ENGINEERING_6 0x5c
7858 #define MC_CMD_SENSOR_ENGINEERING_7 0x5d
7860 #define MC_CMD_SENSOR_ENGINEERING_8 0x5e
7862 #define MC_CMD_SENSOR_PAGE2_NEXT 0x5f
7874 #define MC_CMD_SENSOR_ENTRY_MINNUM 0
7884 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
7888 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_OFST 0
7902 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
7908 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
7910 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
7933 * If the request does not contain the LENGTH field then only sensors 0 to 30
7943 #define MC_CMD_READ_SENSORS 0x42
7952 * If the address is 0xffffffffffffffff send the readings in the response (used
7955 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
7957 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
7959 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LBN 0
7970 * If the address is 0xffffffffffffffff send the readings in the response (used
7973 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
7975 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
7977 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LBN 0
7991 * If the address is 0xffffffffffffffff send the readings in the response (used
7994 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0
7996 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0
7998 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LBN 0
8011 #define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 0
8015 #define MC_CMD_READ_SENSORS_OUT_LEN 0
8018 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
8022 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
8024 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
8029 #define MC_CMD_SENSOR_STATE_OK 0x0
8031 #define MC_CMD_SENSOR_STATE_WARNING 0x1
8033 #define MC_CMD_SENSOR_STATE_FATAL 0x2
8035 #define MC_CMD_SENSOR_STATE_BROKEN 0x3
8037 #define MC_CMD_SENSOR_STATE_NO_READING 0x4
8039 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
8054 * code: 0
8056 #define MC_CMD_GET_PHY_STATE 0x43
8062 #define MC_CMD_GET_PHY_STATE_IN_LEN 0
8066 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
8069 #define MC_CMD_PHY_STATE_OK 0x1
8071 #define MC_CMD_PHY_STATE_ZOMBIE 0x2
8076 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
8079 #define MC_CMD_SETUP_8021QBB 0x44
8083 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
8087 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0
8092 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
8094 #define MC_CMD_WOL_FILTER_GET 0x45
8100 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0
8104 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
8111 * Returns: 0, ENOSYS
8113 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
8124 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
8126 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
8127 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
8136 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
8145 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
8156 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
8163 * None. Returns: 0, ENOSYS
8165 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
8172 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
8178 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
8183 * Restore MAC after block reset. Locks required: None. Returns: 0.
8185 #define MC_CMD_MAC_RESET_RESTORE 0x48
8188 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
8191 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
8198 * required: None Returns: 0
8200 #define MC_CMD_TESTASSERT 0x49
8206 #define MC_CMD_TESTASSERT_IN_LEN 0
8209 #define MC_CMD_TESTASSERT_OUT_LEN 0
8214 #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0
8219 #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0
8220 /* enum: Assert using assert(0); */
8221 #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1
8223 #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2
8225 #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3
8227 #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4
8229 #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5
8232 #define MC_CMD_TESTASSERT_V2_OUT_LEN 0
8241 * basis. Locks required: None. Returns: 0, EINVAL .
8243 #define MC_CMD_WORKAROUND 0x4a
8251 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
8254 #define MC_CMD_WORKAROUND_BUG17230 0x1
8256 #define MC_CMD_WORKAROUND_BUG35388 0x2
8258 #define MC_CMD_WORKAROUND_BUG35017 0x3
8260 #define MC_CMD_WORKAROUND_BUG41750 0x4
8266 #define MC_CMD_WORKAROUND_BUG42008 0x5
8274 #define MC_CMD_WORKAROUND_BUG26807 0x6
8276 #define MC_CMD_WORKAROUND_BUG61265 0x7
8277 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
8284 #define MC_CMD_WORKAROUND_OUT_LEN 0
8290 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
8292 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 0
8293 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
8302 * output data, are interpreted on a per-type basis. For SFP+, PAGE=0 or 1
8303 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
8308 * of "0xffff:0xffff" retrieves the lower (unbanked) page. Locks required -
8309 * None. Return code - 0.
8311 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
8318 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
8320 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_OFST 0
8321 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_LBN 0
8323 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_OFST 0
8334 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
8348 #define MC_CMD_NVRAM_TEST 0x4c
8355 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
8362 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
8365 #define MC_CMD_NVRAM_TEST_PASS 0x0
8367 #define MC_CMD_NVRAM_TEST_FAIL 0x1
8369 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2
8376 * they are configured first. Locks required: None. Return code: 0, EINVAL.
8378 #define MC_CMD_MRSFP_TWEAK 0x4d
8382 /* 0-6 low->high de-emph. */
8383 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
8385 /* 0-8 low->high ref.V */
8388 /* 0-8 0-8 low->high boost */
8391 /* 0-8 low->high ref.V */
8396 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
8401 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
8410 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0
8412 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1
8421 #define MC_CMD_SENSOR_SET_LIMS 0x4e
8428 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
8446 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
8452 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f
8455 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
8459 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
8472 * none. Returns: 0, EINVAL (bad type).
8474 #define MC_CMD_NVRAM_PARTITIONS 0x51
8480 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
8489 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
8494 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
8502 * none. Returns: 0, EINVAL (bad type).
8504 #define MC_CMD_NVRAM_METADATA 0x52
8512 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
8522 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
8527 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
8553 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
8562 #define MC_CMD_GET_MAC_ADDRESSES 0x55
8568 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
8573 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
8593 #define MC_CMD_CLP 0x56
8601 #define MC_CMD_CLP_IN_OP_OFST 0
8604 #define MC_CMD_CLP_OP_DEFAULT 0x1
8606 #define MC_CMD_CLP_OP_SET_MAC 0x2
8608 #define MC_CMD_CLP_OP_GET_MAC 0x3
8610 #define MC_CMD_CLP_OP_SET_BOOT 0x4
8612 #define MC_CMD_CLP_OP_GET_BOOT 0x5
8615 #define MC_CMD_CLP_OUT_LEN 0
8619 /* MC_CMD_CLP_IN_OP_OFST 0 */
8623 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0
8627 /* MC_CMD_CLP_IN_OP_OFST 0 */
8640 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0
8644 /* MC_CMD_CLP_IN_OP_OFST 0 */
8658 #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_LBN 0
8663 /* MC_CMD_CLP_IN_OP_OFST 0 */
8668 /* MC_CMD_CLP_IN_OP_OFST 0 */
8673 #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_LBN 0
8679 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0
8687 /* MC_CMD_CLP_IN_OP_OFST 0 */
8694 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0
8698 /* MC_CMD_CLP_IN_OP_OFST 0 */
8704 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0
8715 #define MC_CMD_MUM 0x57
8722 #define MC_CMD_MUM_IN_OP_HDR_OFST 0
8724 #define MC_CMD_MUM_IN_OP_OFST 0
8725 #define MC_CMD_MUM_IN_OP_LBN 0
8728 #define MC_CMD_MUM_OP_NULL 0x1
8730 #define MC_CMD_MUM_OP_GET_VERSION 0x2
8732 #define MC_CMD_MUM_OP_RAW_CMD 0x3
8734 #define MC_CMD_MUM_OP_READ 0x4
8736 #define MC_CMD_MUM_OP_WRITE 0x5
8738 #define MC_CMD_MUM_OP_LOG 0x6
8740 #define MC_CMD_MUM_OP_GPIO 0x7
8742 #define MC_CMD_MUM_OP_READ_SENSORS 0x8
8744 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9
8746 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa
8750 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb
8754 #define MC_CMD_MUM_OP_QSFP 0xc
8758 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd
8763 #define MC_CMD_MUM_IN_CMD_OFST 0
8769 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8775 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8781 #define MC_CMD_MUM_DEV_HITTITE 0x1
8783 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2
8798 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8804 /* MC_CMD_MUM_DEV_HITTITE 0x1 */
8822 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8843 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8847 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */
8851 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8862 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8867 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0
8869 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */
8870 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */
8871 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */
8872 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */
8873 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */
8874 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */
8878 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8885 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8898 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8905 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8918 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8925 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8932 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */
8933 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */
8934 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */
8935 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */
8942 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8949 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8959 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8969 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8980 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8985 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0
8994 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8999 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */
9000 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */
9001 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */
9006 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0
9018 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9027 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9033 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9038 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0
9040 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */
9041 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */
9042 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */
9043 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */
9044 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */
9045 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */
9051 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9062 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9077 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9086 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9097 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9106 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9116 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9120 #define MC_CMD_MUM_OUT_LEN 0
9123 #define MC_CMD_MUM_OUT_NULL_LEN 0
9127 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0
9144 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
9145 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1)
9147 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0
9157 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
9158 #define MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4)
9159 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0
9166 #define MC_CMD_MUM_OUT_WRITE_LEN 0
9169 #define MC_CMD_MUM_OUT_LOG_LEN 0
9172 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0
9177 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0
9184 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0
9189 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0
9196 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0
9200 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0
9207 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0
9211 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0
9214 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0
9217 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0
9223 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
9224 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4)
9225 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0
9230 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_OFST 0
9231 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0
9233 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_OFST 0
9236 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_OFST 0
9242 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0
9246 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0
9250 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0
9254 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0
9258 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0
9263 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0
9271 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0
9281 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0
9291 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0
9298 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0
9308 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0
9310 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_OFST 0
9311 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0
9313 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_OFST 0
9334 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0
9337 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0
9339 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1
9341 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2
9351 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */
9352 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */
9353 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */
9354 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */
9356 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4
9367 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0
9369 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1
9371 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2
9373 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3
9375 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4
9377 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5
9380 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6
9390 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 0
9392 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 0
9428 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 0
9430 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 0
9444 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x0
9446 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x1
9448 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x2
9450 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x3
9452 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x4
9467 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 0
9469 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 0
9480 #define MC_CMD_DYNAMIC_SENSORS_READING_OK 0x0
9482 #define MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x1
9484 #define MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x2
9486 #define MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x3
9488 #define MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x4
9490 #define MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x5
9492 #define MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x6
9525 #define MC_CMD_DYNAMIC_SENSORS_LIST 0x66
9531 #define MC_CMD_DYNAMIC_SENSORS_LIST_IN_LEN 0
9542 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 0
9552 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 0
9570 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67
9576 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMIN 0
9579 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))
9580 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)
9582 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_OFST 0
9584 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MINNUM 0
9589 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMIN 0
9592 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LEN(num) (0+64*(num))
9593 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)
9595 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_OFST 0
9597 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MINNUM 0
9619 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68
9625 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMIN 0
9628 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))
9629 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)
9631 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_OFST 0
9633 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MINNUM 0
9638 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMIN 0
9641 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LEN(num) (0+12*(num))
9642 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)
9644 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_OFST 0
9646 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MINNUM 0
9656 #define MC_CMD_EVENT_CTRL 0x69
9662 #define MC_CMD_EVENT_CTRL_IN_LENMIN 0
9665 #define MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num))
9666 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4)
9668 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_OFST 0
9670 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MINNUM 0
9674 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_LINKCHANGE 0x0
9677 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_SENSOREVT 0x1
9679 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_RX_ERR 0x2
9681 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_TX_ERR 0x3
9683 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_FWALERT 0x4
9685 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_MC_REBOOT 0x5
9688 #define MC_CMD_EVENT_CTRL_OUT_LEN 0
9692 #define EVB_PORT_ID_PORT_ID_OFST 0
9695 #define EVB_PORT_ID_NULL 0x0
9697 #define EVB_PORT_ID_ASSIGNED 0x1000000
9698 /* enum: External network port 0 */
9699 #define EVB_PORT_ID_MAC0 0x2000000
9701 #define EVB_PORT_ID_MAC1 0x2000001
9703 #define EVB_PORT_ID_MAC2 0x2000002
9705 #define EVB_PORT_ID_MAC3 0x2000003
9706 #define EVB_PORT_ID_PORT_ID_LBN 0
9712 #define EVB_VLAN_TAG_VLAN_ID_LBN 0
9717 #define EVB_VLAN_TAG_INSERT 0x0
9719 #define EVB_VLAN_TAG_REPLACE 0x1
9724 #define BUFTBL_ENTRY_OID_OFST 0
9726 #define BUFTBL_ENTRY_OID_LBN 0
9749 #define NVRAM_PARTITION_TYPE_ID_OFST 0
9752 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
9755 #define NVRAM_PARTITION_TYPE_NMC_FIRMWARE 0x100
9757 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
9759 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
9761 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
9765 #define NVRAM_PARTITION_TYPE_FACTORY_CONFIG 0x400
9767 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
9771 #define NVRAM_PARTITION_TYPE_USER_CONFIG 0x500
9772 /* enum: Expansion ROM configuration data for port 0 */
9773 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
9775 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
9777 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
9779 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
9781 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
9783 #define NVRAM_PARTITION_TYPE_LOG 0x700
9787 #define NVRAM_PARTITION_TYPE_NMC_LOG 0x700
9789 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
9791 #define NVRAM_PARTITION_TYPE_DUMP 0x800
9793 #define NVRAM_PARTITION_TYPE_NMC_CRASH_LOG 0x801
9795 #define NVRAM_PARTITION_TYPE_LICENSE 0x900
9797 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
9799 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
9801 #define NVRAM_PARTITION_TYPE_FPGA 0xb00
9803 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
9805 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
9807 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
9809 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
9811 #define NVRAM_PARTITION_TYPE_FPGA_STAGE1 0xb05
9813 #define NVRAM_PARTITION_TYPE_FPGA_STAGE2 0xb06
9814 /* enum: FPGA User XCLBIN / Programmable Region 0 bitstream */
9815 #define NVRAM_PARTITION_TYPE_FPGA_REGION0 0xb07
9817 #define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_USER 0xb07
9821 #define NVRAM_PARTITION_TYPE_FPGA_JUMP 0xb08
9823 #define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_VALIDATE 0xb09
9825 #define NVRAM_PARTITION_TYPE_FPGA_XOCL_CONFIG 0xb0a
9827 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
9831 #define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
9833 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
9837 #define NVRAM_PARTITION_TYPE_SUC_LOG 0xc01
9839 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
9841 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
9843 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
9845 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
9847 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
9849 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
9851 #define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
9855 #define NVRAM_PARTITION_TYPE_EXPROM_LOG 0x1000
9857 #define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
9859 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200
9863 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
9867 #define NVRAM_PARTITION_TYPE_DEPLOYMENT_CONFIG 0x1300
9869 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
9871 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500
9875 #define NVRAM_PARTITION_TYPE_STATUS 0x1600
9877 #define NVRAM_PARTITION_TYPE_SPARE_13 0x1700
9879 #define NVRAM_PARTITION_TYPE_SPARE_14 0x1800
9881 #define NVRAM_PARTITION_TYPE_SPARE_15 0x1900
9883 #define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
9885 #define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
9887 #define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
9892 #define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00
9894 #define NVRAM_PARTITION_TYPE_BUNDLE 0x1e00
9898 #define NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e01
9900 #define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
9902 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03
9904 #define NVRAM_PARTITION_TYPE_BUNDLE_SIGNATURE 0x1e04
9906 #define NVRAM_PARTITION_TYPE_SUC_TEST 0x1f00
9908 #define NVRAM_PARTITION_TYPE_SUC_FPGA_PRIMARY 0x1f01
9910 #define NVRAM_PARTITION_TYPE_SUC_FPGA_SECONDARY 0x1f02
9912 #define NVRAM_PARTITION_TYPE_SUC_SOC_PRIMARY 0x1f03
9916 #define NVRAM_PARTITION_TYPE_SUC_SOC_SECONDARY 0x1f04
9921 #define NVRAM_PARTITION_TYPE_SUC_FAILURE_LOG 0x1f05
9923 #define NVRAM_PARTITION_TYPE_SUC_SOC_CONFIG 0x1f07
9925 #define NVRAM_PARTITION_TYPE_SOC_UPDATE 0x2003
9927 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
9929 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
9931 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
9935 #define NVRAM_PARTITION_TYPE_RECOVERY_FPT 0xfffe
9937 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
9941 #define NVRAM_PARTITION_TYPE_FPT 0xffff
9942 #define NVRAM_PARTITION_TYPE_ID_LBN 0
9947 #define LICENSED_APP_ID_ID_OFST 0
9950 #define LICENSED_APP_ID_ONLOAD 0x1
9952 #define LICENSED_APP_ID_PTP 0x2
9954 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
9956 #define LICENSED_APP_ID_SOLARSECURE 0x8
9958 #define LICENSED_APP_ID_PERF_MONITOR 0x10
9960 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
9962 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
9964 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
9966 #define LICENSED_APP_ID_TCP_DIRECT 0x100
9968 #define LICENSED_APP_ID_LOW_LATENCY 0x200
9970 #define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
9972 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800
9974 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
9976 #define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000
9978 #define LICENSED_APP_ID_DSHBRD 0x4000
9980 #define LICENSED_APP_ID_SCATRD 0x8000
9981 #define LICENSED_APP_ID_ID_LBN 0
9987 #define LICENSED_FEATURES_MASK_OFST 0
9989 #define LICENSED_FEATURES_MASK_LO_OFST 0
9991 #define LICENSED_FEATURES_MASK_LO_LBN 0
9997 #define LICENSED_FEATURES_RX_CUT_THROUGH_OFST 0
9998 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
10000 #define LICENSED_FEATURES_PIO_OFST 0
10003 #define LICENSED_FEATURES_EVQ_TIMER_OFST 0
10006 #define LICENSED_FEATURES_CLOCK_OFST 0
10009 #define LICENSED_FEATURES_RX_TIMESTAMPS_OFST 0
10012 #define LICENSED_FEATURES_TX_TIMESTAMPS_OFST 0
10015 #define LICENSED_FEATURES_RX_SNIFF_OFST 0
10018 #define LICENSED_FEATURES_TX_SNIFF_OFST 0
10021 #define LICENSED_FEATURES_PROXY_FILTER_OPS_OFST 0
10024 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_OFST 0
10027 #define LICENSED_FEATURES_MASK_LBN 0
10033 #define LICENSED_V3_APPS_MASK_OFST 0
10035 #define LICENSED_V3_APPS_MASK_LO_OFST 0
10037 #define LICENSED_V3_APPS_MASK_LO_LBN 0
10043 #define LICENSED_V3_APPS_ONLOAD_OFST 0
10044 #define LICENSED_V3_APPS_ONLOAD_LBN 0
10046 #define LICENSED_V3_APPS_PTP_OFST 0
10049 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_OFST 0
10052 #define LICENSED_V3_APPS_SOLARSECURE_OFST 0
10055 #define LICENSED_V3_APPS_PERF_MONITOR_OFST 0
10058 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_OFST 0
10061 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_OFST 0
10064 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_OFST 0
10067 #define LICENSED_V3_APPS_TCP_DIRECT_OFST 0
10070 #define LICENSED_V3_APPS_LOW_LATENCY_OFST 0
10073 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_OFST 0
10076 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_OFST 0
10079 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_OFST 0
10082 #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_OFST 0
10085 #define LICENSED_V3_APPS_DSHBRD_OFST 0
10088 #define LICENSED_V3_APPS_SCATRD_OFST 0
10091 #define LICENSED_V3_APPS_MASK_LBN 0
10097 #define LICENSED_V3_FEATURES_MASK_OFST 0
10099 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0
10101 #define LICENSED_V3_FEATURES_MASK_LO_LBN 0
10107 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0
10108 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
10110 #define LICENSED_V3_FEATURES_PIO_OFST 0
10113 #define LICENSED_V3_FEATURES_EVQ_TIMER_OFST 0
10116 #define LICENSED_V3_FEATURES_CLOCK_OFST 0
10119 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_OFST 0
10122 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_OFST 0
10125 #define LICENSED_V3_FEATURES_RX_SNIFF_OFST 0
10128 #define LICENSED_V3_FEATURES_TX_SNIFF_OFST 0
10131 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_OFST 0
10134 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_OFST 0
10137 #define LICENSED_V3_FEATURES_MASK_LBN 0
10143 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0
10145 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0
10152 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
10156 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11
10160 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12
10164 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13
10166 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
10168 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
10179 /* The RSS mode for a particular packet type is a value from 0 - 15 which can
10181 * value 0 effectively disables RSS spreading for the packet type.) The YAML
10185 #define RSS_MODE_HASH_SELECTOR_OFST 0
10187 #define RSS_MODE_HASH_SRC_ADDR_OFST 0
10188 #define RSS_MODE_HASH_SRC_ADDR_LBN 0
10190 #define RSS_MODE_HASH_DST_ADDR_OFST 0
10193 #define RSS_MODE_HASH_SRC_PORT_OFST 0
10196 #define RSS_MODE_HASH_DST_PORT_OFST 0
10199 #define RSS_MODE_HASH_SELECTOR_LBN 0
10205 #define CTPIO_STATS_MAP_VI_OFST 0
10207 #define CTPIO_STATS_MAP_VI_LBN 0
10220 #define MC_CMD_READ_REGS 0x50
10226 #define MC_CMD_READ_REGS_IN_LEN 0
10231 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0
10246 #define MC_CMD_INIT_EVQ 0x80
10258 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
10277 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
10300 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
10302 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
10304 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
10306 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
10320 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
10322 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
10324 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
10326 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
10348 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
10358 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
10377 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
10401 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0
10407 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1
10413 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2
10418 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
10425 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0
10427 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1
10429 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2
10431 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3
10445 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0
10447 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1
10449 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2
10451 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3
10473 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0
10479 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
10496 #define MC_CMD_INIT_EVQ_V3_IN_SIZE_OFST 0
10515 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_INTERRUPTING_LBN 0
10539 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_MANUAL 0x0
10545 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_LOW_LATENCY 0x1
10551 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_THROUGHPUT 0x2
10556 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_AUTO 0x3
10563 #define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_DIS 0x0
10565 #define MC_CMD_INIT_EVQ_V3_IN_TMR_IMMED_START 0x1
10567 #define MC_CMD_INIT_EVQ_V3_IN_TMR_TRIG_START 0x2
10569 #define MC_CMD_INIT_EVQ_V3_IN_TMR_INT_HLDOFF 0x3
10583 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_DIS 0x0
10585 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_RX 0x1
10587 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_TX 0x2
10589 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_RXTX 0x3
10608 * and granularity are device specific. Specify 0 to use the firmware's default
10615 * and granularity are device specific. Specify 0 to use the firmware's default
10625 #define MC_CMD_INIT_EVQ_V3_OUT_IRQ_OFST 0
10631 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_LBN 0
10645 #define QUEUE_CRC_MODE_MODE_LBN 0
10648 #define QUEUE_CRC_MODE_NONE 0x0
10650 #define QUEUE_CRC_MODE_FCOE 0x1
10652 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2
10654 #define QUEUE_CRC_MODE_ISCSI 0x3
10656 #define QUEUE_CRC_MODE_FCOIPOE 0x4
10658 #define QUEUE_CRC_MODE_MPA 0x5
10669 #define MC_CMD_INIT_RXQ 0x81
10683 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
10702 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
10751 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
10774 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
10798 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
10800 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
10807 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
10809 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
10816 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
10817 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
10818 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
10819 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
10820 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
10847 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_MINNUM 0
10857 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0
10880 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0
10904 #define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0
10906 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1
10913 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
10915 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
10922 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
10923 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
10924 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
10925 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
10926 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
10953 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_MINNUM 0
10980 * are still no descriptors then the packet will be dropped. A timeout of 0
10992 #define MC_CMD_INIT_RXQ_V4_IN_SIZE_OFST 0
11015 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_LBN 0
11039 #define MC_CMD_INIT_RXQ_V4_IN_SINGLE_PACKET 0x0
11041 #define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM 0x1
11048 #define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11050 #define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11057 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_1M 0x0 /* enum */
11058 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_512K 0x1 /* enum */
11059 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_256K 0x2 /* enum */
11060 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_128K 0x3 /* enum */
11061 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_64K 0x4 /* enum */
11088 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_MINNUM 0
11115 * are still no descriptors then the packet will be dropped. A timeout of 0
11140 #define MC_CMD_INIT_RXQ_V5_IN_SIZE_OFST 0
11163 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 0
11187 #define MC_CMD_INIT_RXQ_V5_IN_SINGLE_PACKET 0x0
11189 #define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM 0x1
11196 #define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11198 #define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11205 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */
11206 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_512K 0x1 /* enum */
11207 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */
11208 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */
11209 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */
11236 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_MINNUM 0
11263 * are still no descriptors then the packet will be dropped. A timeout of 0
11291 #define MC_CMD_INIT_RXQ_OUT_LEN 0
11294 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
11297 #define MC_CMD_INIT_RXQ_V3_OUT_LEN 0
11300 #define MC_CMD_INIT_RXQ_V4_OUT_LEN 0
11303 #define MC_CMD_INIT_RXQ_V5_OUT_LEN 0
11309 #define MC_CMD_INIT_TXQ 0x82
11323 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
11343 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
11395 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0
11415 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
11476 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 0
11483 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
11490 #define MC_CMD_INIT_TXQ_OUT_LEN 0
11500 #define MC_CMD_FINI_EVQ 0x83
11510 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
11514 #define MC_CMD_FINI_EVQ_OUT_LEN 0
11521 #define MC_CMD_FINI_RXQ 0x84
11529 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
11533 #define MC_CMD_FINI_RXQ_OUT_LEN 0
11540 #define MC_CMD_FINI_TXQ 0x85
11548 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
11552 #define MC_CMD_FINI_TXQ_OUT_LEN 0
11559 #define MC_CMD_DRIVER_EVENT 0x86
11567 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
11569 /* Bits 0 - 63 of event */
11582 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0
11592 #define MC_CMD_PROXY_CMD 0x5b
11600 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
11602 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_OFST 0
11603 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0
11605 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_OFST 0
11608 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
11611 #define MC_CMD_PROXY_CMD_OUT_LEN 0
11618 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0
11621 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0
11622 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0
11660 #define MC_CMD_PROXY_CONFIGURE 0x58
11667 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0
11669 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_OFST 0
11670 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0
11730 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0
11732 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_OFST 0
11733 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0
11794 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0
11804 #define MC_CMD_PROXY_COMPLETE 0x5f
11811 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0
11818 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0
11822 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1
11824 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2
11828 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3
11833 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0
11842 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
11850 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
11860 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
11873 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
11884 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
11908 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
11914 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89
11921 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
11925 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
11932 #define MC_CMD_FILTER_OP 0x8a
11940 #define MC_CMD_FILTER_OP_IN_OP_OFST 0
11943 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
11945 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
11947 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
11949 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
11953 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
11973 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
12021 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
12023 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
12025 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
12026 /* enum: loop back to TXDP 0 */
12027 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
12029 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
12037 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
12039 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
12041 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
12044 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12051 /* transmit domain (reserved; set to 0) */
12061 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
12063 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
12089 /* IP protocol to match (in low byte; set high byte to 0) */
12092 /* Firmware defined register 0 to match (reserved; set to 0) */
12095 /* Firmware defined register 1 to match (reserved; set to 0) */
12099 * 0 for IPv4 address)
12104 * bytes to 0 for IPv4 address)
12115 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0
12138 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
12228 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
12230 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
12232 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
12233 /* enum: loop back to TXDP 0 */
12234 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
12236 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
12244 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
12246 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
12248 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
12251 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12258 /* transmit domain (reserved; set to 0) */
12268 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
12270 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
12296 /* IP protocol to match (in low byte; set high byte to 0) */
12299 /* Firmware defined register 0 to match (reserved; set to 0) */
12303 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
12309 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
12315 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
12317 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
12319 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
12321 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
12327 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
12329 * 0 for IPv4 address)
12334 * bytes to 0 for IPv4 address)
12369 * 0)
12373 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
12374 * to 0)
12379 * to 0)
12384 * order; set last 12 bytes to 0 for IPv4 address)
12389 * order; set last 12 bytes to 0 for IPv4 address)
12403 #define MC_CMD_FILTER_OP_V3_IN_OP_OFST 0
12426 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0
12516 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0
12518 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1
12520 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2
12521 /* enum: loop back to TXDP 0 */
12522 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3
12524 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4
12532 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0
12534 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1
12536 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2
12539 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12546 /* transmit domain (reserved; set to 0) */
12556 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
12558 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0
12584 /* IP protocol to match (in low byte; set high byte to 0) */
12587 /* Firmware defined register 0 to match (reserved; set to 0) */
12591 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
12597 #define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0
12603 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0
12605 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
12607 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
12609 #define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0
12615 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0
12617 * 0 for IPv4 address)
12622 * bytes to 0 for IPv4 address)
12657 * 0)
12661 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
12662 * to 0)
12667 * to 0)
12672 * order; set last 12 bytes to 0 for IPv4 address)
12677 * order; set last 12 bytes to 0 for IPv4 address)
12684 * else user_flag = req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark
12685 * = 0; else if (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK
12694 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_LBN 0
12721 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0
12726 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1
12731 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
12742 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0
12748 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
12761 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
12763 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
12768 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0
12774 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
12794 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4
12802 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
12805 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
12809 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
12813 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
12818 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
12822 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5
12824 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_TYPES 0x6
12833 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
12845 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
12852 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0
12860 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0
12875 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_OFST 0
12887 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MINNUM 0
12896 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_OP_OFST 0
12903 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_LBN 0
12925 #define MC_CMD_PARSER_DISP_RW 0xe5
12933 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0
12936 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0
12938 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1
12944 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2
12946 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3
12948 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0
12950 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4
12952 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5
12957 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0
12961 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1
12965 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2
12973 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1
12993 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0
12996 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0
13004 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0
13007 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */
13008 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */
13015 #define MC_CMD_GET_PF_COUNT 0xb6
13021 #define MC_CMD_GET_PF_COUNT_IN_LEN 0
13026 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0
13034 #define MC_CMD_SET_PF_COUNT 0xb7
13039 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0
13043 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0
13050 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
13056 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
13065 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
13068 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_NULL_PORT 0xffffffff
13075 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
13083 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
13087 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
13094 #define MC_CMD_ALLOC_VIS 0x8b
13102 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
13113 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
13124 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0
13131 /* Function's port vi_shift value (always 0 on Huntington) */
13141 #define MC_CMD_FREE_VIS 0x8c
13147 #define MC_CMD_FREE_VIS_IN_LEN 0
13150 #define MC_CMD_FREE_VIS_OUT_LEN 0
13157 #define MC_CMD_GET_SRIOV_CFG 0xba
13163 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0
13168 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
13176 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
13190 #define MC_CMD_SET_SRIOV_CFG 0xbb
13198 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
13206 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
13208 /* RID offset of first VF from PF, or 0 for no change, or
13213 /* RID offset of each subsequent VF from the previous, 0 for no change, or
13220 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
13229 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d
13235 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0
13240 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0
13247 /* Function's port vi_shift value (always 0 on Huntington) */
13258 #define MC_CMD_DUMP_VI_STATE 0x8e
13266 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0
13272 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
13315 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0
13368 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
13404 /* Reserved, currently 0. */
13427 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
13447 #define MC_CMD_ALLOC_PIOBUF 0x8f
13453 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0
13458 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
13466 #define MC_CMD_FREE_PIOBUF 0x90
13474 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
13478 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0
13487 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
13495 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
13501 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0
13518 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0
13528 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
13536 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
13560 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
13567 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
13574 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
13577 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
13579 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
13581 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
13583 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3
13587 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0
13595 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0
13601 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0
13616 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0
13628 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0
13651 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
13658 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
13666 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0
13669 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0
13681 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0
13690 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0
13709 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0
13716 #define MC_CMD_SATELLITE_DOWNLOAD 0x91
13724 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.
13726 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download
13734 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.
13747 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0
13749 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */
13750 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */
13751 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */
13752 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */
13753 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */
13760 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0
13762 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1
13764 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2
13766 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3
13768 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4
13770 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5
13772 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6
13774 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7
13776 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8
13778 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9
13780 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa
13782 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb
13784 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc
13786 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd
13788 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe
13790 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf
13792 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff
13797 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff
13799 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe
13812 /* Same as MC_CMD_ERR field, but included as 0 in success cases */
13813 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0
13819 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0
13821 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1
13823 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2
13825 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100
13827 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101
13829 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200
13831 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201
13833 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300
13843 #define MC_CMD_GET_CAPABILITIES 0xbe
13849 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0
13854 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
13856 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_OFST 0
13859 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_OFST 0
13862 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_OFST 0
13865 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
13868 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_OFST 0
13871 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_OFST 0
13874 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_OFST 0
13877 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
13880 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
13883 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
13886 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_OFST 0
13889 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_OFST 0
13892 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
13895 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_OFST 0
13898 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_OFST 0
13901 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_OFST 0
13904 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_OFST 0
13907 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_OFST 0
13910 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_OFST 0
13913 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_OFST 0
13916 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_OFST 0
13919 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_OFST 0
13922 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_OFST 0
13925 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_OFST 0
13928 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_OFST 0
13931 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_OFST 0
13934 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
13937 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_OFST 0
13940 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_OFST 0
13947 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
13949 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
13951 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
13953 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
13955 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6
13957 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
13959 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
13961 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
13963 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
13965 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
13967 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
13969 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
13971 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
13973 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
13975 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
13977 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c
13982 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
13984 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
13986 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
13988 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
13990 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6
13992 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
13994 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
13996 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
13998 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
14002 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
14010 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
14014 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14017 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14021 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14023 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14025 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14029 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14031 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14033 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14037 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14039 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14041 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14043 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa
14045 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14049 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14053 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
14061 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
14065 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14068 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14072 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14074 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14076 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14080 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14081 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14085 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14087 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14089 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14091 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa
14093 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14102 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0
14107 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0
14109 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_OFST 0
14112 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_OFST 0
14115 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_OFST 0
14118 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14121 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_OFST 0
14124 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14127 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_OFST 0
14130 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14133 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14136 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14139 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_OFST 0
14142 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_OFST 0
14145 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14148 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_OFST 0
14151 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_OFST 0
14154 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_OFST 0
14157 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_OFST 0
14160 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_OFST 0
14163 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_OFST 0
14166 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_OFST 0
14169 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_OFST 0
14172 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_OFST 0
14175 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_OFST 0
14178 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_OFST 0
14181 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14184 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_OFST 0
14187 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14190 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_OFST 0
14193 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_OFST 0
14200 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
14202 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
14204 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
14206 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
14208 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6
14210 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
14212 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14214 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14216 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14218 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14220 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
14222 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14224 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14226 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14228 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14230 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c
14235 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
14237 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
14239 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
14241 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
14243 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6
14245 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
14247 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14249 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14251 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
14255 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
14263 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
14267 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14270 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14274 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14276 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14278 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14282 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14284 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14286 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14290 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14292 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14294 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14296 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa
14298 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14302 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14306 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
14314 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
14318 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14321 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14325 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14327 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14329 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14333 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14334 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14338 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14340 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14342 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14344 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa
14346 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14357 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0
14471 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
14473 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
14475 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
14482 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14490 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
14492 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
14517 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0
14519 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_OFST 0
14522 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_OFST 0
14525 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_OFST 0
14528 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14531 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_OFST 0
14534 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14537 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_OFST 0
14540 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14543 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14546 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14549 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_OFST 0
14552 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_OFST 0
14555 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14558 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_OFST 0
14561 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_OFST 0
14564 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_OFST 0
14567 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_OFST 0
14570 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_OFST 0
14573 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_OFST 0
14576 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_OFST 0
14579 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_OFST 0
14582 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_OFST 0
14585 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_OFST 0
14588 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_OFST 0
14591 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14594 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_OFST 0
14597 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14600 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_OFST 0
14603 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_OFST 0
14610 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0
14612 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1
14614 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
14616 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
14618 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6
14620 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
14622 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14624 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14626 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14628 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14630 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105
14632 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14634 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14636 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14638 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14640 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c
14645 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0
14647 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1
14649 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
14651 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
14653 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6
14655 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
14657 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14659 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14661 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
14665 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0
14673 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0
14677 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14680 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14684 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14686 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14688 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14692 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14694 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14696 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14700 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14702 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14704 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14706 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa
14708 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14712 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14716 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0
14724 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0
14728 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14731 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14735 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14737 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14739 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14743 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14744 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14748 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14750 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14752 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14754 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa
14756 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14767 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0
14881 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff
14883 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe
14885 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd
14892 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14900 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
14902 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
14933 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0
14935 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1
14937 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2
14952 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0
14954 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_OFST 0
14957 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_OFST 0
14960 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_OFST 0
14963 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14966 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_OFST 0
14969 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14972 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_OFST 0
14975 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14978 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14981 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14984 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_OFST 0
14987 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_OFST 0
14990 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14993 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_OFST 0
14996 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_OFST 0
14999 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_OFST 0
15002 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_OFST 0
15005 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_OFST 0
15008 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_OFST 0
15011 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_OFST 0
15014 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_OFST 0
15017 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_OFST 0
15020 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_OFST 0
15023 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_OFST 0
15026 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15029 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_OFST 0
15032 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15035 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_OFST 0
15038 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_OFST 0
15045 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0
15047 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1
15049 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
15051 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
15053 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6
15055 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
15057 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15059 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15061 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15063 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15065 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105
15067 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15069 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15071 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15073 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15075 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c
15080 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0
15082 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1
15084 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
15086 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
15088 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6
15090 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
15092 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15094 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15096 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
15100 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0
15108 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0
15112 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
15115 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15119 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
15121 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
15123 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3
15127 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15129 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
15131 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
15135 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
15137 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
15139 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9
15141 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa
15143 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15147 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
15151 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0
15159 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0
15163 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
15166 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15170 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
15172 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
15174 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3
15178 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15179 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
15183 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
15185 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
15187 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9
15189 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa
15191 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15202 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0
15316 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff
15318 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe
15320 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd
15327 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
15335 /* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
15337 /* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
15368 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0
15370 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1
15372 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2
15395 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 0
15397 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_OFST 0
15400 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_OFST 0
15403 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_OFST 0
15406 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
15409 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_OFST 0
15412 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_OFST 0
15415 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_OFST 0
15418 #define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
15421 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
15424 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
15427 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_OFST 0
15430 #define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_OFST 0
15433 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
15436 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_OFST 0
15439 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_OFST 0
15442 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_OFST 0
15445 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_OFST 0
15448 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_OFST 0
15451 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_OFST 0
15454 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_OFST 0
15457 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_OFST 0
15460 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_OFST 0
15463 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_OFST 0
15466 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_OFST 0
15469 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15472 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_OFST 0
15475 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15478 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_OFST 0
15481 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_OFST 0
15488 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x0
15490 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x1
15492 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x2
15494 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x5
15496 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x6
15498 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a
15500 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15502 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15504 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15506 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15508 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x105
15510 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15512 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15514 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15516 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15518 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c
15523 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x0
15525 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x1
15527 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x3
15529 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x5
15531 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x6
15533 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d
15535 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15537 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15539 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x103
15543 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 0
15551 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x0
15555 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
15558 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15562 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
15564 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
15566 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x3
15570 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15572 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
15574 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
15578 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
15580 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
15582 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x9
15584 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa
15586 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15590 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
15594 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 0
15602 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x0
15606 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
15609 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15613 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
15615 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
15617 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x3
15621 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15622 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
15626 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
15628 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
15630 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x9
15632 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa
15634 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15645 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 0
15759 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff
15761 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe
15763 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd
15770 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
15778 /* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */
15780 /* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */
15811 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x0
15813 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x1
15815 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x2
15843 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_OFST 0
15845 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_OFST 0
15848 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_OFST 0
15851 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_OFST 0
15854 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
15857 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_OFST 0
15860 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_OFST 0
15863 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_OFST 0
15866 #define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
15869 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
15872 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
15875 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_OFST 0
15878 #define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_OFST 0
15881 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
15884 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_OFST 0
15887 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_OFST 0
15890 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_OFST 0
15893 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_OFST 0
15896 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_OFST 0
15899 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_OFST 0
15902 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_OFST 0
15905 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_OFST 0
15908 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_OFST 0
15911 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_OFST 0
15914 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_OFST 0
15917 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15920 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_OFST 0
15923 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15926 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_OFST 0
15929 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_OFST 0
15936 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP 0x0
15938 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_LOW_LATENCY 0x1
15940 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_PACKED_STREAM 0x2
15942 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_RULES_ENGINE 0x5
15944 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_DPDK 0x6
15946 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_BIST 0x10a
15948 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15950 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15952 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15954 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15956 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_BACKPRESSURE 0x105
15958 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15960 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15962 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15964 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15966 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_SLOW 0x10c
15971 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP 0x0
15973 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_LOW_LATENCY 0x1
15975 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_HIGH_PACKET_RATE 0x3
15977 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_RULES_ENGINE 0x5
15979 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_DPDK 0x6
15981 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_BIST 0x12d
15983 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15985 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15987 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_CSR 0x103
15991 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_LBN 0
15999 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RESERVED 0x0
16003 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
16006 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16010 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
16012 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
16014 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_VSWITCH 0x3
16018 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16020 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
16022 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
16026 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
16028 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
16030 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_L3XUDP 0x9
16032 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_DPDK 0xa
16034 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16038 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
16042 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_LBN 0
16050 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RESERVED 0x0
16054 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
16057 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16061 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
16063 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
16065 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_VSWITCH 0x3
16069 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16070 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
16074 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
16076 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
16078 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_L3XUDP 0x9
16080 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_DPDK 0xa
16082 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16093 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_LBN 0
16207 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff
16209 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe
16211 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_ASSIGNED 0xfd
16218 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
16226 /* MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */
16228 /* MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */
16259 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_8K 0x0
16261 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_16K 0x1
16263 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_64K 0x2
16302 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_OFST 0
16304 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_OFST 0
16307 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_OFST 0
16310 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_OFST 0
16313 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
16316 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_OFST 0
16319 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_OFST 0
16322 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_OFST 0
16325 #define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
16328 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
16331 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
16334 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_OFST 0
16337 #define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_OFST 0
16340 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
16343 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_OFST 0
16346 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_OFST 0
16349 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_OFST 0
16352 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_OFST 0
16355 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_OFST 0
16358 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_OFST 0
16361 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_OFST 0
16364 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_OFST 0
16367 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_OFST 0
16370 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_OFST 0
16373 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_OFST 0
16376 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_OFST 0
16379 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_OFST 0
16382 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
16385 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_OFST 0
16388 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_OFST 0
16395 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP 0x0
16397 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_LOW_LATENCY 0x1
16399 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_PACKED_STREAM 0x2
16401 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_RULES_ENGINE 0x5
16403 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_DPDK 0x6
16405 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_BIST 0x10a
16407 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
16409 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
16411 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
16413 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
16415 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_BACKPRESSURE 0x105
16417 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
16419 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
16421 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
16423 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
16425 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_SLOW 0x10c
16430 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP 0x0
16432 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_LOW_LATENCY 0x1
16434 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_HIGH_PACKET_RATE 0x3
16436 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_RULES_ENGINE 0x5
16438 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_DPDK 0x6
16440 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_BIST 0x12d
16442 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
16444 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
16446 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_CSR 0x103
16450 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_LBN 0
16458 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RESERVED 0x0
16462 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
16465 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16469 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
16471 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
16473 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_VSWITCH 0x3
16477 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16479 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
16481 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
16485 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
16487 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
16489 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_L3XUDP 0x9
16491 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_DPDK 0xa
16493 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16497 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
16501 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_LBN 0
16509 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RESERVED 0x0
16513 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
16516 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16520 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
16522 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
16524 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_VSWITCH 0x3
16528 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16529 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
16533 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
16535 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
16537 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_L3XUDP 0x9
16539 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_DPDK 0xa
16541 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16552 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_LBN 0
16666 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff
16668 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe
16670 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_ASSIGNED 0xfd
16677 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
16685 /* MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */
16687 /* MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */
16718 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_8K 0x0
16720 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_16K 0x1
16722 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_64K 0x2
16761 #define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_LBN 0
16806 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST 0
16808 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_OFST 0
16811 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_OFST 0
16814 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_OFST 0
16817 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
16820 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_OFST 0
16823 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_OFST 0
16826 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_OFST 0
16829 #define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
16832 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
16835 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
16838 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_OFST 0
16841 #define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_OFST 0
16844 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
16847 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_OFST 0
16850 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_OFST 0
16853 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_OFST 0
16856 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_OFST 0
16859 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_OFST 0
16862 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_OFST 0
16865 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_OFST 0
16868 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_OFST 0
16871 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_OFST 0
16874 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_OFST 0
16877 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_OFST 0
16880 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_OFST 0
16883 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_OFST 0
16886 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
16889 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_OFST 0
16892 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_OFST 0
16899 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP 0x0
16901 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_LOW_LATENCY 0x1
16903 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_PACKED_STREAM 0x2
16905 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_RULES_ENGINE 0x5
16907 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_DPDK 0x6
16909 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_BIST 0x10a
16911 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
16913 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
16915 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
16917 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
16919 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_BACKPRESSURE 0x105
16921 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
16923 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
16925 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
16927 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
16929 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_SLOW 0x10c
16934 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP 0x0
16936 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_LOW_LATENCY 0x1
16938 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_HIGH_PACKET_RATE 0x3
16940 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_RULES_ENGINE 0x5
16942 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_DPDK 0x6
16944 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_BIST 0x12d
16946 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
16948 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
16950 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_CSR 0x103
16954 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_LBN 0
16962 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RESERVED 0x0
16966 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
16969 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16973 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
16975 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
16977 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_VSWITCH 0x3
16981 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16983 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
16985 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
16989 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
16991 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
16993 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_L3XUDP 0x9
16995 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_DPDK 0xa
16997 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17001 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
17005 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_LBN 0
17013 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RESERVED 0x0
17017 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
17020 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17024 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
17026 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
17028 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_VSWITCH 0x3
17032 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17033 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
17037 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
17039 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
17041 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_L3XUDP 0x9
17043 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_DPDK 0xa
17045 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17056 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_LBN 0
17170 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff
17172 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe
17174 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_ASSIGNED 0xfd
17181 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
17189 /* MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */
17191 /* MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */
17222 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_8K 0x0
17224 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_16K 0x1
17226 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_64K 0x2
17265 #define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_LBN 0
17324 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_OFST 0
17326 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_OFST 0
17329 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_OFST 0
17332 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_OFST 0
17335 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
17338 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_OFST 0
17341 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_OFST 0
17344 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_OFST 0
17347 #define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
17350 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
17353 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
17356 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_OFST 0
17359 #define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_OFST 0
17362 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
17365 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_OFST 0
17368 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_OFST 0
17371 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_OFST 0
17374 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_OFST 0
17377 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_OFST 0
17380 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_OFST 0
17383 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_OFST 0
17386 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_OFST 0
17389 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_OFST 0
17392 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_OFST 0
17395 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_OFST 0
17398 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_OFST 0
17401 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_OFST 0
17404 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
17407 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_OFST 0
17410 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_OFST 0
17417 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP 0x0
17419 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_LOW_LATENCY 0x1
17421 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_PACKED_STREAM 0x2
17423 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_RULES_ENGINE 0x5
17425 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_DPDK 0x6
17427 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_BIST 0x10a
17429 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
17431 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
17433 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
17435 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
17437 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_BACKPRESSURE 0x105
17439 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
17441 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
17443 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
17445 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
17447 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_SLOW 0x10c
17452 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP 0x0
17454 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_LOW_LATENCY 0x1
17456 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_HIGH_PACKET_RATE 0x3
17458 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_RULES_ENGINE 0x5
17460 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_DPDK 0x6
17462 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_BIST 0x12d
17464 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
17466 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
17468 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_CSR 0x103
17472 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_LBN 0
17480 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RESERVED 0x0
17484 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
17487 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17491 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
17493 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
17495 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_VSWITCH 0x3
17499 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17501 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
17503 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
17507 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
17509 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
17511 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_L3XUDP 0x9
17513 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_DPDK 0xa
17515 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17519 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
17523 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_LBN 0
17531 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RESERVED 0x0
17535 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
17538 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17542 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
17544 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
17546 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_VSWITCH 0x3
17550 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17551 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
17555 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
17557 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
17559 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_L3XUDP 0x9
17561 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_DPDK 0xa
17563 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17574 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_LBN 0
17688 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff
17690 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe
17692 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_ASSIGNED 0xfd
17699 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
17707 /* MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */
17709 /* MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */
17740 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_8K 0x0
17742 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_16K 0x1
17744 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_64K 0x2
17783 #define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_LBN 0
17877 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_OFST 0
17879 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_OFST 0
17882 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_OFST 0
17885 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_OFST 0
17888 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
17891 #define MC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_OFST 0
17894 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_OFST 0
17897 #define MC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_OFST 0
17900 …efine MC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
17903 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
17906 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
17909 #define MC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_OFST 0
17912 #define MC_CMD_GET_CAPABILITIES_V10_OUT_QBB_OFST 0
17915 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
17918 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_OFST 0
17921 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_OFST 0
17924 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_OFST 0
17927 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_OFST 0
17930 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_OFST 0
17933 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_OFST 0
17936 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_OFST 0
17939 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_OFST 0
17942 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_OFST 0
17945 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_OFST 0
17948 #define MC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_OFST 0
17951 #define MC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_OFST 0
17954 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_OFST 0
17957 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
17960 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_OFST 0
17963 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_OFST 0
17970 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP 0x0
17972 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_LOW_LATENCY 0x1
17974 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_PACKED_STREAM 0x2
17976 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_RULES_ENGINE 0x5
17978 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_DPDK 0x6
17980 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_BIST 0x10a
17982 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
17984 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
17986 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
17988 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
17990 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_BACKPRESSURE 0x105
17992 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
17994 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
17996 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
17998 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
18000 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_SLOW 0x10c
18005 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP 0x0
18007 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_LOW_LATENCY 0x1
18009 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_HIGH_PACKET_RATE 0x3
18011 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_RULES_ENGINE 0x5
18013 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_DPDK 0x6
18015 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_BIST 0x12d
18017 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
18019 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
18021 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_CSR 0x103
18025 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_LBN 0
18033 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RESERVED 0x0
18037 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
18040 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
18044 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
18046 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
18048 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_VSWITCH 0x3
18052 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
18054 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
18056 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
18060 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
18062 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
18064 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_L3XUDP 0x9
18066 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_DPDK 0xa
18068 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
18072 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
18076 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_LBN 0
18084 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RESERVED 0x0
18088 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
18091 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
18095 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
18097 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
18099 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_VSWITCH 0x3
18103 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
18104 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
18108 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
18110 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
18112 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_L3XUDP 0x9
18114 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_DPDK 0xa
18116 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
18127 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_LBN 0
18241 #define MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff
18243 #define MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe
18245 #define MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_ASSIGNED 0xfd
18252 #define MC_CMD_GET_CAPABILITIES_V10_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
18260 /* MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff */
18262 /* MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe */
18293 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_8K 0x0
18295 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_16K 0x1
18297 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_64K 0x2
18336 #define MC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_LBN 0
18446 #define MC_CMD_V2_EXTN 0x7f
18451 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
18466 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
18470 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1
18477 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2
18483 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0
18488 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0
18496 #define MC_CMD_TCM_BUCKET_FREE 0xb3
18504 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0
18508 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0
18515 #define MC_CMD_TCM_BUCKET_INIT 0xb4
18523 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0
18532 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0
18542 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0
18549 #define MC_CMD_TCM_TXQ_INIT 0xb5
18557 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0
18566 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0
18594 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0
18603 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0
18632 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0
18639 #define MC_CMD_LINK_PIOBUF 0x92
18647 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
18654 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0
18661 #define MC_CMD_UNLINK_PIOBUF 0x93
18669 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
18673 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
18680 #define MC_CMD_VSWITCH_ALLOC 0x94
18688 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
18694 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
18696 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
18698 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
18700 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
18702 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
18707 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
18720 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
18727 #define MC_CMD_VSWITCH_FREE 0x95
18735 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
18739 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0
18748 #define MC_CMD_VSWITCH_QUERY 0x63
18756 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
18760 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0
18767 #define MC_CMD_VPORT_ALLOC 0x96
18775 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
18781 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
18783 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
18785 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
18789 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
18793 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
18797 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
18802 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
18817 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
18826 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
18834 #define MC_CMD_VPORT_FREE 0x97
18842 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
18846 #define MC_CMD_VPORT_FREE_OUT_LEN 0
18853 #define MC_CMD_VADAPTOR_ALLOC 0x98
18861 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
18867 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
18882 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
18891 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
18894 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
18901 #define MC_CMD_VADAPTOR_FREE 0x99
18909 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
18913 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0
18920 #define MC_CMD_VADAPTOR_SET_MAC 0x5d
18928 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
18935 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0
18942 #define MC_CMD_VADAPTOR_GET_MAC 0x5e
18950 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
18956 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0
18964 #define MC_CMD_VADAPTOR_QUERY 0x61
18972 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
18978 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0
18992 #define MC_CMD_EVB_PORT_ASSIGN 0x9a
19000 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
19006 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
19013 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
19020 #define MC_CMD_RDWR_A64_REGIONS 0x9b
19027 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0
19035 /* Write enable bits 0-3, set to write, clear to read. */
19045 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0
19059 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
19067 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19073 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0
19081 #define MC_CMD_ONLOAD_STACK_FREE 0x9d
19089 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0
19093 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0
19100 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
19108 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19116 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
19121 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
19126 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EVEN_SPREADING 0x2
19131 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
19143 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_OFST 0
19151 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EXCLUSIVE 0x0
19156 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_SHARED 0x1
19161 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EVEN_SPREADING 0x2
19166 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
19187 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
19190 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
19193 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff
19200 #define MC_CMD_RSS_CONTEXT_FREE 0x9f
19208 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
19212 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
19219 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
19227 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
19234 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
19241 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
19249 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
19265 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
19273 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
19280 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
19289 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
19297 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
19313 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e
19325 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_OFST 0
19337 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT_LEN 0
19342 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_OFST 0
19344 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LBN 0
19359 #define MC_CMD_RSS_CONTEXT_READ_TABLE 0x13f
19371 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_OFST 0
19384 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LEN(num) (0+2*(num))
19385 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_NUM(len) (((len)-0)/2)
19387 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_OFST 0
19398 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
19406 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
19414 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In
19423 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
19457 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
19464 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
19472 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
19493 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
19531 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
19539 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19542 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and
19551 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
19554 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0
19557 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff
19564 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5
19572 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0
19576 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0
19583 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
19591 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
19600 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0
19607 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
19615 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
19631 #define MC_CMD_GET_VECTOR_CFG 0xbf
19637 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0
19642 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0
19656 #define MC_CMD_SET_VECTOR_CFG 0xc0
19666 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0
19676 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0
19683 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
19691 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
19698 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
19705 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
19713 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
19720 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
19727 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
19735 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
19745 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
19750 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
19761 #define MC_CMD_VPORT_RECONFIGURE 0xeb
19769 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0
19775 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0
19790 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0
19805 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0
19807 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_OFST 0
19808 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0
19816 #define MC_CMD_EVB_PORT_QUERY 0x62
19824 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0
19830 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0
19846 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
19854 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0
19864 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))
19865 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_NUM(len) (((len)-0)/12)
19867 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0
19878 #define MC_CMD_SET_RXDP_CONFIG 0xc1
19885 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0
19887 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_OFST 0
19888 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0
19890 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_OFST 0
19894 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0
19896 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1
19898 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2
19901 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0
19908 #define MC_CMD_GET_RXDP_CONFIG 0xc2
19914 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0
19918 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0
19920 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_OFST 0
19921 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0
19923 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_OFST 0
19934 #define MC_CMD_GET_CLOCK 0xac
19940 #define MC_CMD_GET_CLOCK_IN_LEN 0
19945 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
19956 #define MC_CMD_SET_CLOCK 0xad
19964 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0
19967 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0
19972 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0
19977 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0
19982 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0
19987 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0
19992 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0
19997 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0
20002 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0
20005 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0
20010 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0
20015 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0
20020 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0
20025 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0
20030 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0
20035 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0
20042 #define MC_CMD_DPCPU_RPC 0xae
20049 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0
20052 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0
20054 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1
20056 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2
20058 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3
20062 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80
20066 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81
20075 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
20076 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */
20077 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */
20078 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */
20079 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */
20080 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */
20081 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
20082 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
20083 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
20099 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
20100 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */
20101 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
20102 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
20103 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
20116 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
20117 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
20118 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
20133 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0
20160 #define MC_CMD_TRIGGER_INTERRUPT 0xe3
20168 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
20172 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
20179 #define MC_CMD_SHMBOOT_OP 0xe6
20187 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0
20190 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0
20193 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0
20200 #define MC_CMD_CAP_BLK_READ 0xe7
20207 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0
20218 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num))
20219 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_NUM(len) (((len)-0)/8)
20220 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
20222 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
20224 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LBN 0
20239 #define MC_CMD_DUMP_DO 0xe8
20246 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0
20250 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
20251 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
20254 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
20255 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
20256 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
20257 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
20268 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
20273 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
20279 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff
20284 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
20285 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
20311 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0
20319 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
20326 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0
20388 #define MC_CMD_SET_PSU 0xea
20395 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0
20397 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
20400 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
20401 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
20407 #define MC_CMD_SET_PSU_OUT_LEN 0
20414 #define MC_CMD_GET_FUNCTION_INFO 0xec
20420 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
20424 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
20431 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_PF_OFST 0
20448 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed
20454 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
20457 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
20466 #define MC_CMD_UART_SEND_DATA 0xee
20478 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0
20491 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0
20496 #define MC_CMD_UART_SEND_DATA_IN_LEN 0
20504 #define MC_CMD_UART_RECV_DATA 0xef
20512 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0
20531 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0
20544 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0
20553 #define MC_CMD_READ_FUSES 0xf0
20561 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0
20574 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
20579 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0
20588 #define MC_CMD_KR_TUNE 0xf1
20600 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
20603 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
20605 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
20607 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
20609 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
20611 #define MC_CMD_KR_TUNE_IN_RECAL 0x4
20615 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5
20620 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
20622 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7
20624 #define MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8
20626 #define MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9
20633 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0
20638 #define MC_CMD_KR_TUNE_OUT_LEN 0
20643 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0
20653 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
20654 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
20656 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
20661 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0
20662 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
20664 /* enum: Attenuation (0-15, Huntington) */
20665 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
20666 /* enum: CTLE Boost (0-15, Huntington) */
20667 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
20668 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
20669 * positive, Medford - 0-31)
20671 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
20672 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
20673 * positive, Medford - 0-31)
20675 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
20676 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
20677 * positive, Medford - 0-16)
20679 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
20680 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
20681 * positive, Medford - 0-16)
20683 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
20684 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
20685 * positive, Medford - 0-16)
20687 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
20688 /* enum: Edge DFE DLEV (0-128 for Medford) */
20689 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7
20690 /* enum: Variable Gain Amplifier (0-15, Medford) */
20691 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8
20692 /* enum: CTLE EQ Capacitor (0-15, Medford) */
20693 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
20694 /* enum: CTLE EQ Resistor (0-7, Medford) */
20695 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
20696 /* enum: CTLE gain (0-31, Medford2) */
20697 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb
20698 /* enum: CTLE pole (0-31, Medford2) */
20699 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc
20700 /* enum: CTLE peaking (0-31, Medford2) */
20701 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd
20703 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe
20705 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf
20707 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10
20709 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11
20711 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12
20713 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13
20715 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14
20717 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15
20719 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16
20721 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17
20723 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18
20725 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19
20727 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a
20729 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b
20733 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c
20737 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d
20741 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e
20745 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f
20747 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20
20749 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21
20753 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_LS 0x22
20756 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_LS 0x23
20759 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_LS 0x24
20762 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_LS 0x25
20765 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_LS 0x26
20768 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_LS 0x27
20772 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_HS 0x28
20775 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_HS 0x29
20778 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_HS 0x2a
20781 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_HS 0x2b
20784 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_HS 0x2c
20787 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_HS 0x2d
20788 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0
20791 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
20792 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
20793 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
20794 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
20795 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
20796 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0
20799 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0
20802 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_OFST 0
20805 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0
20816 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
20828 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
20851 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0
20856 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0
20866 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
20867 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
20869 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
20874 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0
20875 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
20878 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0
20879 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
20880 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1
20882 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2
20883 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
20884 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3
20886 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4
20888 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5
20890 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6
20892 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7
20894 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8
20896 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9
20898 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa
20900 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb
20902 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc
20904 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_LS 0xd
20906 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_LS 0xe
20908 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_LS 0xf
20910 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_HS 0x10
20912 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_HS 0x11
20914 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_HS 0x12
20915 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0
20918 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
20919 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
20920 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
20921 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
20922 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
20923 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0
20926 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_OFST 0
20929 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_OFST 0
20940 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0
20952 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0
20972 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0
20977 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0
20984 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0
20989 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
21001 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0
21009 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0
21019 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0
21024 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
21031 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
21034 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
21035 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
21036 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
21038 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
21045 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0
21053 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0
21061 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0
21067 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_OFST 0
21074 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */
21075 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */
21080 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_OFST 0
21096 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */
21097 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */
21098 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */
21099 /* C(0) request */
21113 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0
21115 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */
21116 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */
21117 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */
21118 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */
21119 /* C(0) status */
21132 /* C(0) value */
21144 #define MC_CMD_PCIE_TUNE 0xf2
21156 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0
21159 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0
21161 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1
21163 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2
21165 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3
21167 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5
21172 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6
21174 #define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7
21181 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0
21186 #define MC_CMD_PCIE_TUNE_OUT_LEN 0
21191 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
21201 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
21202 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
21204 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
21209 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0
21210 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
21212 /* enum: Attenuation (0-15) */
21213 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0
21214 /* enum: CTLE Boost (0-15) */
21215 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1
21216 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
21217 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2
21218 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
21219 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3
21220 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
21221 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4
21222 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
21223 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5
21224 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
21225 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6
21227 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7
21229 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8
21231 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
21233 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
21234 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0
21237 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
21238 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
21239 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
21240 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
21241 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */
21242 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */
21243 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */
21244 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */
21245 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */
21246 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */
21247 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */
21248 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */
21249 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */
21250 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */
21251 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */
21252 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */
21253 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */
21254 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0
21257 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0
21260 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0
21271 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0
21283 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
21306 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0
21311 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
21321 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
21322 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
21324 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
21329 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0
21330 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
21333 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0
21335 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1
21337 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2
21338 /* enum: De-emphasis coefficient C(0) (PIPE) */
21339 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3
21341 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4
21342 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0
21347 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0
21350 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_OFST 0
21357 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
21366 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0
21371 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
21378 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
21381 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
21382 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
21383 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
21385 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
21390 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0
21393 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0
21401 #define MC_CMD_LICENSING 0xf3
21409 #define MC_CMD_LICENSING_IN_OP_OFST 0
21414 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
21416 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
21421 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
21447 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
21449 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
21457 #define MC_CMD_LICENSING_V3 0xd0
21465 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0
21470 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
21474 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1
21479 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0
21501 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
21503 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
21539 #define MC_CMD_LICENSING_GET_ID_V3 0xd1
21545 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0
21554 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0
21562 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0
21572 #define MC_CMD_MC2MC_PROXY 0xf4
21578 #define MC_CMD_MC2MC_PROXY_IN_LEN 0
21581 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0
21590 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5
21598 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0
21604 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
21607 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
21609 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
21618 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
21628 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0
21630 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0
21632 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LBN 0
21642 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0
21645 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0
21647 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1
21656 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
21666 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0
21668 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0
21670 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LBN 0
21680 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0
21682 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0
21684 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LBN 0
21697 #define MC_CMD_LICENSED_APP_OP 0xf6
21709 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0
21715 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0
21717 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1
21721 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0
21726 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0
21729 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
21730 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_NUM(len) (((len)-0)/4)
21732 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0
21734 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0
21741 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0
21753 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0
21762 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0
21772 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0
21780 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
21788 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0
21810 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0
21819 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0
21821 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1
21829 * exists, then the field is filled with 0xFF.
21839 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
21847 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0
21849 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0
21851 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LBN 0
21861 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0
21863 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1
21866 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0
21877 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
21885 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0
21891 #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0
21895 #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1
21899 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2
21903 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0
21911 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0
21916 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0
21922 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0
21925 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0
21927 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1
21931 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2
21953 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7
21961 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
21963 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0
21964 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
21966 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_OFST 0
21976 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
21978 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
21981 * of 0xFFFFFFFF is guaranteed never to be a valid handle.
21987 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0
21996 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
22002 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0
22007 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
22009 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0
22010 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
22012 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_OFST 0
22022 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
22024 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
22034 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
22046 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
22051 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
22056 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
22072 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0
22079 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
22087 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
22101 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
22102 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_NUM(len) (((len)-0)/4)
22106 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0
22123 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb
22131 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
22133 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0
22134 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
22143 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
22145 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
22148 * of 0xFFFFFFFF is guaranteed never to be a valid handle.
22154 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0
22163 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
22169 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0
22174 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
22176 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0
22177 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
22186 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
22188 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
22198 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe
22206 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0
22211 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0
22216 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0
22230 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd
22236 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0
22241 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0
22269 #define MC_CMD_GET_PORT_MODES 0xff
22275 #define MC_CMD_GET_PORT_MODES_IN_LEN 0
22282 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0
22296 #define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_OFST 0
22325 #define MC_CMD_OVERRIDE_PORT_MODE 0x137
22332 #define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_OFST 0
22334 #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_OFST 0
22335 #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_LBN 0
22342 #define MC_CMD_OVERRIDE_PORT_MODE_OUT_LEN 0
22349 #define MC_CMD_READ_ATB 0x100
22356 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0
22358 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */
22359 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */
22360 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */
22370 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0
22379 #define MC_CMD_GET_WORKAROUNDS 0x59
22388 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
22393 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
22395 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
22397 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
22399 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10
22405 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20
22407 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40
22409 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80
22416 #define MC_CMD_PRIVILEGE_MASK 0x5a
22423 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF
22424 * 1,3 = 0x00030001
22426 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0
22428 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_OFST 0
22429 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0
22431 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_OFST 0
22434 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
22440 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
22441 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
22442 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
22443 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
22444 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
22446 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
22447 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
22448 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
22449 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
22450 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
22451 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
22455 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
22459 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
22465 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
22469 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
22475 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
22477 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE 0x10000
22481 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALLOC_CLIENT 0x20000
22485 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_FUNC_DMA 0x40000
22491 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ARBITRARY_DMA 0x80000
22495 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000
22500 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0
22508 #define MC_CMD_LINK_STATE_MODE 0x5c
22516 * e.g. VF 1,3 = 0x00030001
22518 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
22520 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_OFST 0
22521 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
22523 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_OFST 0
22529 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
22530 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
22531 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
22534 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
22538 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0
22547 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101
22553 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0
22558 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0
22569 #define MC_CMD_FUSE_DIAGS 0x102
22575 #define MC_CMD_FUSE_DIAGS_IN_LEN 0
22579 /* Total number of mismatched bits between pairs in area 0 */
22580 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0
22582 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */
22585 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */
22588 /* Checksum of data after logical OR of pairs in area 0 */
22623 #define MC_CMD_PRIVILEGE_MODIFY 0x60
22631 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0
22633 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */
22634 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */
22635 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */
22636 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */
22637 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */
22638 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */
22643 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0
22660 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0
22667 #define MC_CMD_XPM_READ_BYTES 0x103
22675 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0
22682 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0
22685 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num))
22686 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_NUM(len) (((len)-0)/1)
22688 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0
22690 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0
22699 #define MC_CMD_XPM_WRITE_BYTES 0x104
22711 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0
22719 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0
22724 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0
22731 #define MC_CMD_XPM_READ_SECTOR 0x105
22739 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0
22752 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0
22754 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */
22755 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */
22756 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */
22757 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */
22758 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */
22762 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0
22771 #define MC_CMD_XPM_WRITE_SECTOR 0x106
22783 * sectors (or until no more space available). If 0, only one write attempt is
22787 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0
22802 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0
22809 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0
22817 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107
22825 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0
22829 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0
22836 #define MC_CMD_XPM_BLANK_CHECK 0x108
22844 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0
22857 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0
22864 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0
22873 #define MC_CMD_XPM_REPAIR 0x109
22881 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0
22888 #define MC_CMD_XPM_REPAIR_OUT_LEN 0
22896 #define MC_CMD_XPM_DECODER_TEST 0x10a
22902 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0
22905 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0
22916 #define MC_CMD_XPM_WRITE_TEST 0x10b
22922 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0
22925 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0
22937 #define MC_CMD_EXEC_SIGNED 0x10c
22945 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0
22958 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0
22967 #define MC_CMD_PREPARE_SIGNED 0x10d
22975 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0
22979 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0
22985 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0
22988 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
22990 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
22991 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0
22997 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
22999 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
23012 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
23024 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
23026 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_OFST 0
23027 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
23037 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
23044 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
23046 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_OFST 0
23047 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
23058 #define MC_CMD_RX_BALANCING 0x118
23066 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0
23079 #define MC_CMD_RX_BALANCING_OUT_LEN 0
23087 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c
23099 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0
23112 #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0
23121 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b
23129 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0
23139 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0
23150 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0
23164 #define MC_CMD_SET_EVQ_TMR 0x120
23172 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0
23183 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */
23184 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */
23185 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */
23186 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */
23191 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0
23202 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
23208 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0
23213 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0
23271 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
23282 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0
23287 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */
23289 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0
23297 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1
23302 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */
23303 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */
23304 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */
23305 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */
23306 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */
23307 /* enum: To enable Switch loopback with Rx engine 0 */
23308 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4
23310 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5
23315 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0
23324 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
23333 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0
23339 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1
23340 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */
23341 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */
23342 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */
23343 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */
23344 /* enum: To enable Switch loopback with Rx engine 0 */
23345 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4
23347 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5
23352 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0
23360 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1
23365 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0
23377 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
23385 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0
23389 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0
23397 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
23405 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0
23409 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0
23417 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124
23423 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0
23428 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0
23439 #define MC_CMD_SUC_VERSION 0x134
23445 #define MC_CMD_SUC_VERSION_IN_LEN 0
23450 #define MC_CMD_SUC_VERSION_OUT_VERSION_OFST 0
23468 #define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_OFST 0
23471 #define MC_CMD_SUC_VERSION_GET_BOOT_VERSION 0xb007700b
23476 #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_OFST 0
23491 #define MC_CMD_GET_RX_PREFIX_ID 0x13b
23499 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_OFST 0
23501 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_OFST 0
23503 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LBN 0
23509 #define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_OFST 0
23510 #define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_LBN 0
23512 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_OFST 0
23515 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_OFST 0
23518 #define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_OFST 0
23521 #define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_OFST 0
23524 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_OFST 0
23527 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_OFST 0
23530 #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_MPORT_OFST 0
23533 #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_OFST 0
23536 #define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_OFST 0
23539 #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_OFST 0
23542 #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIPPED_OFST 0
23545 #define MC_CMD_GET_RX_PREFIX_ID_IN_VSWITCH_STATUS_OFST 0
23556 #define MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_OFST 0
23572 #define RX_PREFIX_FIELD_INFO_OFFSET_BITS_OFST 0
23574 #define RX_PREFIX_FIELD_INFO_OFFSET_BITS_LBN 0
23586 #define RX_PREFIX_FIELD_INFO_LENGTH 0x0 /* enum */
23587 #define RX_PREFIX_FIELD_INFO_RSS_HASH_VALID 0x1 /* enum */
23588 #define RX_PREFIX_FIELD_INFO_USER_FLAG 0x2 /* enum */
23589 #define RX_PREFIX_FIELD_INFO_CLASS 0x3 /* enum */
23590 #define RX_PREFIX_FIELD_INFO_PARTIAL_TSTAMP 0x4 /* enum */
23591 #define RX_PREFIX_FIELD_INFO_RSS_HASH 0x5 /* enum */
23592 #define RX_PREFIX_FIELD_INFO_USER_MARK 0x6 /* enum */
23593 #define RX_PREFIX_FIELD_INFO_INGRESS_MPORT 0x7 /* enum */
23594 #define RX_PREFIX_FIELD_INFO_INGRESS_VPORT 0x7 /* enum */
23595 #define RX_PREFIX_FIELD_INFO_CSUM_FRAME 0x8 /* enum */
23596 #define RX_PREFIX_FIELD_INFO_VLAN_STRIP_TCI 0x9 /* enum */
23597 #define RX_PREFIX_FIELD_INFO_VLAN_STRIPPED 0xa /* enum */
23598 #define RX_PREFIX_FIELD_INFO_VSWITCH_STATUS 0xb /* enum */
23611 #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_OFST 0
23613 #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LBN 0
23627 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_MINNUM 0
23640 #define MC_CMD_QUERY_RX_PREFIX_ID 0x13c
23648 #define MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_OFST 0
23658 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_OFST 0
23661 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_FIXED 0x0
23667 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MINNUM 0
23676 #define MC_CMD_BUNDLE 0x13d
23684 #define MC_CMD_BUNDLE_IN_OP_OFST 0
23687 #define MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_GET 0x0
23689 #define MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_SET 0x1
23698 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_OFST 0
23706 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_OFST 0
23709 #define MC_CMD_BUNDLE_COMPONENTS_READ_ONLY 0x0
23711 #define MC_CMD_BUNDLE_COMPONENTS_READ_WRITE 0x1
23722 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_OFST 0
23731 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_OUT_LEN 0
23738 #define MC_CMD_GET_VPD 0x165
23748 #define MC_CMD_GET_VPD_IN_ADDR_OFST 0
23752 #define MC_CMD_GET_VPD_OUT_LENMIN 0
23755 #define MC_CMD_GET_VPD_OUT_LEN(num) (0+1*(num))
23756 #define MC_CMD_GET_VPD_OUT_DATA_NUM(len) (((len)-0)/1)
23758 #define MC_CMD_GET_VPD_OUT_DATA_OFST 0
23760 #define MC_CMD_GET_VPD_OUT_DATA_MINNUM 0
23769 #define MC_CMD_GET_NCSI_INFO 0x167
23777 #define MC_CMD_GET_NCSI_INFO_IN_OP_OFST 0
23780 #define MC_CMD_GET_NCSI_INFO_IN_OP_LINK 0x0
23782 #define MC_CMD_GET_NCSI_INFO_IN_OP_STATISTICS 0x1
23790 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_OFST 0
23799 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_LBN 0
23814 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_OFST 0
23842 #define CLIENT_HANDLE_OPAQUE_OFST 0
23845 #define CLIENT_HANDLE_NULL 0xffffffff
23847 #define CLIENT_HANDLE_SELF 0xfffffffe
23848 #define CLIENT_HANDLE_OPAQUE_LBN 0
23854 #define CLOCK_INFO_CLOCK_ID_OFST 0
23857 #define CLOCK_INFO_CLOCK_CMC 0x0
23859 #define CLOCK_INFO_CLOCK_NMC 0x1
23861 #define CLOCK_INFO_CLOCK_SDNET 0x2
23863 #define CLOCK_INFO_CLOCK_SDNET_LUT 0x3
23865 #define CLOCK_INFO_CLOCK_SDNET_CTRL 0x4
23867 #define CLOCK_INFO_CLOCK_SSS 0x5
23869 #define CLOCK_INFO_CLOCK_MAC 0x6
23870 #define CLOCK_INFO_CLOCK_ID_LBN 0
23876 #define CLOCK_INFO_SETTABLE_LBN 0
23905 #define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_OFST 0
23907 #define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_A 0x0 /* enum */
23908 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_A 0x1 /* enum */
23909 #define SCHED_CREDIT_CHECK_RESULT_HUB_B 0x2 /* enum */
23910 #define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_C 0x3 /* enum */
23911 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_TX 0x4 /* enum */
23912 #define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_D 0x5 /* enum */
23913 #define SCHED_CREDIT_CHECK_RESULT_HUB_REPLAY 0x6 /* enum */
23914 #define SCHED_CREDIT_CHECK_RESULT_DMAC_H2C 0x7 /* enum */
23915 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_B 0x8 /* enum */
23916 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_REPLAY 0x9 /* enum */
23917 #define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LBN 0
23923 #define SCHED_CREDIT_CHECK_RESULT_DEST 0x0
23925 #define SCHED_CREDIT_CHECK_RESULT_SOURCE 0x1
23928 /* Level of node in scheduler hierarchy (level 0 is the bottom of the
23956 #define MC_CMD_GET_CLOCKS_INFO 0x166
23962 #define MC_CMD_GET_CLOCKS_INFO_IN_LEN 0
23965 #define MC_CMD_GET_CLOCKS_INFO_OUT_LENMIN 0
23968 #define MC_CMD_GET_CLOCKS_INFO_OUT_LEN(num) (0+28*(num))
23969 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_NUM(len) (((len)-0)/28)
23971 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_OFST 0
23973 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MINNUM 0
23994 #define MC_CMD_VNIC_ENCAP_RULE_ADD 0x16d
24002 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_OFST 0
24011 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_LBN 0
24026 * Currently only IPv4 (0x0800) and IPv6 (0x86DD) ethertypes may be used.
24039 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_LBN 0
24054 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_LBN 0
24072 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_OFST 0
24082 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e
24090 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_OFST 0
24094 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT_LEN 0
24101 #define UUID_TIME_LOW_OFST 0
24103 #define UUID_TIME_LOW_LBN 0
24135 #define MC_CMD_PLUGIN_ALLOC 0x1ad
24143 #define MC_CMD_PLUGIN_ALLOC_IN_UUID_OFST 0
24149 #define MC_CMD_PLUGIN_ALLOC_IN_FLAG_INFO_ONLY_LBN 0
24163 #define MC_CMD_PLUGIN_ALLOC_IN_ANY 0xffff
24171 #define MC_CMD_PLUGIN_ALLOC_OUT_HANDLE_OFST 0
24179 #define MC_CMD_PLUGIN_FREE 0x1ae
24187 #define MC_CMD_PLUGIN_FREE_IN_HANDLE_OFST 0
24191 #define MC_CMD_PLUGIN_FREE_OUT_LEN 0
24199 #define MC_CMD_PLUGIN_GET_META_GLOBAL 0x1af
24207 #define MC_CMD_PLUGIN_GET_META_GLOBAL_IN_HANDLE_OFST 0
24215 #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_UUID_OFST 0
24229 /* Number of bytes mapped through to the plugin's CSRs. 0 if that feature was
24239 #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_READ_LBN 0
24270 #define MC_CMD_PLUGIN_GET_META_PUBLISHER 0x1b0
24278 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_HANDLE_OFST 0
24286 * the even-numbered fields (0,2,4,...) are keys and their following odd-
24295 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_EXTENSION_KVS 0x0
24309 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_TOTAL_SIZE_OFST 0
24314 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_MINNUM 0
24325 #define MC_CMD_PLUGIN_GET_META_MSG 0x1b1
24333 #define MC_CMD_PLUGIN_GET_META_MSG_IN_HANDLE_OFST 0
24344 #define MC_CMD_PLUGIN_GET_META_MSG_OUT_ID_OFST 0
24353 * bytes at the end set to 0, however this convention is not enforced by the MC
24372 #define PLUGIN_EXTENSION_UUID_OFST 0
24374 #define PLUGIN_EXTENSION_UUID_LBN 0
24395 #define MC_CMD_PLUGIN_GET_ALL 0x1b2
24405 #define MC_CMD_PLUGIN_GET_ALL_IN_FLAGS_OFST 0
24407 #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_ENABLED_OFST 0
24408 #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_ENABLED_LBN 0
24410 #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_DISABLED_OFST 0
24415 #define MC_CMD_PLUGIN_GET_ALL_OUT_LENMIN 0
24418 #define MC_CMD_PLUGIN_GET_ALL_OUT_LEN(num) (0+20*(num))
24419 #define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_NUM(len) (((len)-0)/20)
24423 #define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_OFST 0
24425 #define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_MINNUM 0
24436 #define MC_CMD_PLUGIN_REQ 0x1b3
24448 #define MC_CMD_PLUGIN_REQ_IN_HANDLE_OFST 0
24458 #define MC_CMD_PLUGIN_REQ_IN_DATA_MINNUM 0
24463 #define MC_CMD_PLUGIN_REQ_OUT_LENMIN 0
24466 #define MC_CMD_PLUGIN_REQ_OUT_LEN(num) (0+1*(num))
24467 #define MC_CMD_PLUGIN_REQ_OUT_DATA_NUM(len) (((len)-0)/1)
24471 #define MC_CMD_PLUGIN_REQ_OUT_DATA_OFST 0
24473 #define MC_CMD_PLUGIN_REQ_OUT_DATA_MINNUM 0
24485 #define DESC_ADDR_REGION_DESC_ADDR_BASE_OFST 0
24487 #define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_OFST 0
24489 #define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LBN 0
24495 #define DESC_ADDR_REGION_DESC_ADDR_BASE_LBN 0
24542 #define MC_CMD_GET_DESC_ADDR_INFO 0x1b7
24548 #define MC_CMD_GET_DESC_ADDR_INFO_IN_LEN 0
24555 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_OFST 0
24558 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_FLAT 0x0
24562 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_REGIONED 0x1
24569 #define MC_CMD_GET_DESC_ADDR_REGIONS 0x1b8
24575 #define MC_CMD_GET_DESC_ADDR_REGIONS_IN_LEN 0
24581 #define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LEN(num) (0+32*(num))
24582 #define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_NUM(len) (((len)-0)/32)
24586 #define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_OFST 0
24597 #define MC_CMD_SET_DESC_ADDR_REGIONS 0x1b9
24612 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_OFST 0
24637 #define MC_CMD_SET_DESC_ADDR_REGIONS_OUT_LEN 0
24651 #define MC_CMD_CLIENT_CMD 0x1ba
24659 #define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_OFST 0
24663 #define MC_CMD_CLIENT_CMD_OUT_LEN 0
24677 #define MC_CMD_CLIENT_ALLOC 0x1bb
24683 #define MC_CMD_CLIENT_ALLOC_IN_LEN 0
24688 #define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_OFST 0
24698 #define MC_CMD_CLIENT_FREE 0x1bc
24708 #define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_OFST 0
24712 #define MC_CMD_CLIENT_FREE_OUT_LEN 0
24726 #define MC_CMD_SET_VI_USER 0x1be
24734 #define MC_CMD_SET_VI_USER_IN_INSTANCE_OFST 0
24744 #define MC_CMD_SET_VI_USER_OUT_LEN 0
24779 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES 0x1c4
24790 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
24794 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMIN 0
24797 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(num) (0+6*(num))
24798 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_NUM(len) (((len)-0)/6)
24800 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_OFST 0
24802 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MINNUM 0
24813 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES 0x1c5
24825 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
24830 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MINNUM 0
24835 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT_LEN 0
24850 #define MC_CMD_GET_BOARD_ATTR 0x1c6
24856 #define MC_CMD_GET_BOARD_ATTR_IN_LEN 0
24863 #define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_OFST 0
24865 #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_OFST 0
24866 #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_LBN 0
24868 #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_OFST 0
24871 #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_OFST 0
24877 #define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_LBN 0
24886 #define MC_CMD_FPGA_VOLTAGE_LOW 0x0
24888 #define MC_CMD_FPGA_VOLTAGE_REG 0x1
24890 #define MC_CMD_FPGA_VOLTAGE_HIGH 0x2
24899 #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_UNKNOWN 0x0
24901 #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_SFP 0x1
24903 #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_QSFP 0x2
24911 #define MC_CMD_GET_SOC_STATE 0x1c7
24917 #define MC_CMD_GET_SOC_STATE_IN_LEN 0
24922 #define MC_CMD_GET_SOC_STATE_OUT_FLAGS_OFST 0
24924 #define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_OFST 0
24925 #define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_LBN 0
24927 #define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_OFST 0
24930 #define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_OFST 0
24937 #define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_LBN 0
24940 #define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOT 0x0
24942 #define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOTLOADER 0x1
24944 #define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_START 0x2
24946 #define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_RUNNING 0x3
24948 #define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_MAINTENANCE 0x4
24962 #define MC_CMD_CHECK_SCHEDULER_CREDITS 0x1c8
24970 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_OFST 0
24972 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_OFST 0
24973 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_LBN 0
24976 * into pages. This field specifies which (0-indexed) page to request. A
24977 * request with PAGE=0 will snapshot the results, and subsequent requests with
24978 * PAGE>0 will return data from the most recent snapshot. The GENERATION field
24992 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_OFST 0
25000 /* Result generation count. Incremented any time a request is made with PAGE=0.
25007 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MINNUM 0
25016 #define MC_CMD_TXQ_STATS 0x1d5
25024 #define MC_CMD_TXQ_STATS_IN_INSTANCE_OFST 0
25030 #define MC_CMD_TXQ_STATS_IN_CLEAR_LBN 0
25034 #define MC_CMD_TXQ_STATS_OUT_LENMIN 0
25037 #define MC_CMD_TXQ_STATS_OUT_LEN(num) (0+8*(num))
25038 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_NUM(len) (((len)-0)/8)
25039 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_OFST 0
25041 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_OFST 0
25043 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_LBN 0
25049 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_MINNUM 0
25052 #define MC_CMD_TXQ_STATS_CTPIO_MAX_FILL 0x0 /* enum */
25058 #define FUNCTION_PERSONALITY_ID_OFST 0
25061 #define FUNCTION_PERSONALITY_NULL 0x0
25065 #define FUNCTION_PERSONALITY_EF100 0x1
25069 #define FUNCTION_PERSONALITY_VIRTIO_NET 0x2
25073 #define FUNCTION_PERSONALITY_VIRTIO_BLK 0x3
25075 #define FUNCTION_PERSONALITY_ACCEL_MGMT 0x4
25077 #define FUNCTION_PERSONALITY_ACCEL_USR 0x5
25078 #define FUNCTION_PERSONALITY_ID_LBN 0
25086 #define MC_CMD_VIRTIO_GET_FEATURES 0x168
25096 #define MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_OFST 0
25099 #define MC_CMD_VIRTIO_GET_FEATURES_IN_RESERVED 0x0
25101 #define MC_CMD_VIRTIO_GET_FEATURES_IN_NET 0x1
25103 #define MC_CMD_VIRTIO_GET_FEATURES_IN_BLOCK 0x2
25112 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_OFST 0
25114 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_OFST 0
25116 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LBN 0
25130 #define MC_CMD_VIRTIO_TEST_FEATURES 0x169
25140 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_OFST 0
25161 #define MC_CMD_VIRTIO_TEST_FEATURES_OUT_LEN 0
25173 #define MC_CMD_VIRTIO_GET_CAPABILITIES 0x1d3
25183 #define MC_CMD_VIRTIO_GET_CAPABILITIES_IN_DEVICE_ID_OFST 0
25191 #define MC_CMD_VIRTIO_GET_CAPABILITIES_OUT_MAX_QUEUES_OFST 0
25202 #define MC_CMD_VIRTIO_INIT_QUEUE 0x16a
25212 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_OFST 0
25215 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_RXQ 0x0
25217 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_TXQ 0x1
25219 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_BLOCK 0x2
25228 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_VF_NULL 0xffff
25241 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_LBN 0
25287 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NO_VECTOR 0xffff
25338 #define MC_CMD_VIRTIO_INIT_QUEUE_RESP_LEN 0
25345 #define MC_CMD_VIRTIO_FINI_QUEUE 0x16b
25353 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_OFST 0
25365 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_VF_NULL 0xffff
25373 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_AVAIL_IDX_OFST 0
25376 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_OFST 0
25391 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET 0x16c
25401 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_OFST 0
25413 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_VF_NULL 0xffff
25421 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_OFST 0
25430 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_OFST 0
25438 #define PCIE_FUNCTION_PF_OFST 0
25443 #define PCIE_FUNCTION_PF_ANY 0xfffe
25445 #define PCIE_FUNCTION_PF_NULL 0xffff
25446 #define PCIE_FUNCTION_PF_LBN 0
25454 #define PCIE_FUNCTION_VF_ANY 0xfffe
25458 #define PCIE_FUNCTION_VF_NULL 0xffff
25469 #define PCIE_FUNCTION_INTF_HOST 0x0
25473 #define PCIE_FUNCTION_INTF_AP 0x1
25485 #define QUEUE_ID_ABS_VI_OFST 0
25487 #define QUEUE_ID_ABS_VI_LBN 0
25509 #define MC_CMD_DESC_PROXY_FUNC_CREATE 0x172
25520 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_OFST 0
25522 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_OFST 0
25524 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LBN 0
25530 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_OFST 0
25553 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_OFST 0
25581 #define MC_CMD_DESC_PROXY_FUNC_DESTROY 0x173
25591 #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LABEL_OFST 0
25600 #define MC_CMD_DESC_PROXY_FUNC_DESTROY_OUT_LEN 0
25609 #define VIRTIO_BLK_CONFIG_FEATURES_OFST 0
25611 #define VIRTIO_BLK_CONFIG_FEATURES_LO_OFST 0
25613 #define VIRTIO_BLK_CONFIG_FEATURES_LO_LBN 0
25619 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_OFST 0
25620 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_LBN 0
25622 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_OFST 0
25625 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_OFST 0
25628 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_OFST 0
25631 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_OFST 0
25634 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_OFST 0
25637 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_OFST 0
25640 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_OFST 0
25643 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_OFST 0
25646 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_OFST 0
25649 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_OFST 0
25652 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_OFST 0
25655 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_OFST 0
25658 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_OFST 0
25661 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_OFST 0
25664 #define VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_OFST 0
25667 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_OFST 0
25670 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_OFST 0
25673 #define VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_OFST 0
25676 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_OFST 0
25679 #define VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_OFST 0
25682 #define VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_OFST 0
25685 #define VIRTIO_BLK_CONFIG_FEATURES_LBN 0
25833 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET 0x174
25847 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_OFST 0
25858 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MINNUM 0
25863 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_OUT_LEN 0
25873 #define MC_CMD_DESC_PROXY_FUNC_COMMIT 0x175
25883 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_OFST 0
25888 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_NON_VOLATILE 0x0
25890 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_VOLATILE 0x1
25896 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_OFST 0
25906 #define MC_CMD_DESC_PROXY_FUNC_OPEN 0x176
25916 #define MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LABEL_OFST 0
25926 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_OFST 0
25954 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LIVE 0x0
25956 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PENDING 0x1
25960 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_UNCONFIGURED 0x2
25974 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MINNUM 0
25988 #define MC_CMD_DESC_PROXY_FUNC_CLOSE 0x1a1
25996 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_OFST 0
26000 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_OUT_LEN 0
26005 #define DESC_PROXY_FUNC_MAP_FUNC_OFST 0
26007 #define DESC_PROXY_FUNC_MAP_FUNC_LO_OFST 0
26009 #define DESC_PROXY_FUNC_MAP_FUNC_LO_LBN 0
26015 #define DESC_PROXY_FUNC_MAP_FUNC_LBN 0
26017 #define DESC_PROXY_FUNC_MAP_FUNC_PF_OFST 0
26019 #define DESC_PROXY_FUNC_MAP_FUNC_PF_LBN 0
26049 #define MC_CMD_DESC_PROXY_FUNC_ENUM 0x177
26056 /* Starting index, set to 0 on first request. See
26059 #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_OFST 0
26068 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_OFST 0
26070 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_OFST 0
26071 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_LBN 0
26076 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MINNUM 0
26092 #define MC_CMD_DESC_PROXY_FUNC_ENABLE 0x178
26102 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_OFST 0
26113 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_OFST 0
26124 * source function (0 to max_virtqueues-1). For a multi-queue device, the
26130 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE 0x1d0
26140 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_HANDLE_OFST 0
26152 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_OUT_LEN 0
26160 #define MC_CMD_DESC_PROXY_FUNC_DISABLE 0x179
26170 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_OFST 0
26174 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_OUT_LEN 0
26181 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE 0x1d1
26191 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_HANDLE_OFST 0
26198 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_OUT_LEN 0
26210 #define MC_CMD_DESC_PROXY_GET_VI_INFO 0x1d2
26220 #define MC_CMD_DESC_PROXY_GET_VI_INFO_IN_HANDLE_OFST 0
26224 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_LENMIN 0
26227 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_LEN(num) (0+4*(num))
26228 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_NUM(len) (((len)-0)/4)
26230 * queues (in order from 0 to max_virtqueues-1), as array of QUEUE_ID
26233 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_OFST 0
26235 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_MINNUM 0
26238 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_ABS_VI_OFST 0
26252 #define MC_CMD_GET_ADDR_SPC_ID 0x1a0
26260 #define MC_CMD_GET_ADDR_SPC_ID_IN_TYPE_OFST 0
26265 #define MC_CMD_GET_ADDR_SPC_ID_IN_SELF 0x0
26269 #define MC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC 0x1
26273 #define MC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC_PASID 0x2
26277 #define MC_CMD_GET_ADDR_SPC_ID_IN_REL_VI 0x3
26281 #define MC_CMD_GET_ADDR_SPC_ID_IN_ABS_VI 0x4
26285 #define MC_CMD_GET_ADDR_SPC_ID_IN_DESC_PROXY_HANDLE 0x5
26287 #define MC_CMD_GET_ADDR_SPC_ID_IN_MC_MEM 0x6
26290 #define MC_CMD_GET_ADDR_SPC_ID_IN_NIC_MEM 0x7
26326 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_OFST 0
26328 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_OFST 0
26330 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LBN 0
26345 #define MC_CMD_GET_CLIENT_HANDLE 0x1c3
26353 #define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_OFST 0
26356 #define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_FUNC 0x0
26382 #define MC_CMD_GET_CLIENT_HANDLE_IN_PCIE_FUNCTION_INTF_NULL 0xffffffff
26392 #define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_OFST 0
26397 #define MAE_FIELD_FLAGS_FLAT_OFST 0
26399 #define MAE_FIELD_FLAGS_SUPPORT_STATUS_OFST 0
26400 #define MAE_FIELD_FLAGS_SUPPORT_STATUS_LBN 0
26402 #define MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS_OFST 0
26405 #define MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS_OFST 0
26408 #define MAE_FIELD_FLAGS_FLAT_LBN 0
26421 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_OFST 0
26423 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_LBN 0
26545 #define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_LBN 0
26564 #define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_LBN 0
26608 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_OFST 0
26610 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_LBN 0
26935 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_OFST 0
26937 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_LBN 0
27262 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_IP_FRAG_LBN 0
27359 #define MAE_MPORT_SELECTOR_FLAT_OFST 0
27364 #define MAE_MPORT_SELECTOR_NULL 0x0
27366 #define MAE_MPORT_SELECTOR_ASSIGNED 0x1000000
27367 #define MAE_MPORT_SELECTOR_TYPE_OFST 0
27371 #define MAE_MPORT_SELECTOR_TYPE_PPORT 0x2
27375 #define MAE_MPORT_SELECTOR_TYPE_FUNC 0x3
27377 #define MAE_MPORT_SELECTOR_TYPE_MPORT_ID 0x4
27380 #define MAE_MPORT_SELECTOR_TYPE_MH_FUNC 0x5
27382 #define MAE_MPORT_SELECTOR_TYPE_INVALID 0xff
27383 #define MAE_MPORT_SELECTOR_MPORT_ID_OFST 0
27384 #define MAE_MPORT_SELECTOR_MPORT_ID_LBN 0
27386 #define MAE_MPORT_SELECTOR_PPORT_ID_OFST 0
27387 #define MAE_MPORT_SELECTOR_PPORT_ID_LBN 0
27389 #define MAE_MPORT_SELECTOR_FUNC_INTF_ID_OFST 0
27392 #define MAE_MPORT_SELECTOR_HOST_PRIMARY 0x1 /* enum */
27393 #define MAE_MPORT_SELECTOR_NIC_EMBEDDED 0x2 /* enum */
27395 #define MAE_MPORT_SELECTOR_CALLER 0xf
27396 #define MAE_MPORT_SELECTOR_CALLER_INTF 0xf /* enum */
27397 #define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_OFST 0
27400 #define MAE_MPORT_SELECTOR_FUNC_PF_ID_OFST 0
27403 #define MAE_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
27404 #define MAE_MPORT_SELECTOR_FUNC_VF_ID_LBN 0
27407 #define MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL 0xffff
27419 #define MAE_MPORT_SELECTOR_FUNC_PF_ID_CALLER 0xff
27423 #define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_CALLER 0xf
27424 #define MAE_MPORT_SELECTOR_FLAT_LBN 0
27432 #define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_OFST 0
27434 #define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LBN 0
27444 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_OFST 0
27446 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_OFST 0
27448 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LBN 0
27459 #define MAE_LINK_ENDPOINT_SELECTOR_MAE_LINK_ENDPOINT_COMPAT 0x0
27460 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LBN 0
27468 #define MC_CMD_MAE_GET_CAPS 0x140
27474 #define MC_CMD_MAE_GET_CAPS_IN_LEN 0
27482 #define MC_CMD_MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT_OFST 0
27487 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_LBN 0
27552 #define MC_CMD_MAE_GET_CAPS_V2_OUT_MATCH_FIELD_COUNT_OFST 0
27557 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_VXLAN_LBN 0
27618 * COUNTER_TYPES_SUPPORTED==0x1). See also
27633 #define MC_CMD_MAE_GET_CAPS_V3_OUT_MATCH_FIELD_COUNT_OFST 0
27638 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_VXLAN_LBN 0
27699 * COUNTER_TYPES_SUPPORTED==0x1). See also
27716 #define MC_CMD_MAE_GET_AR_CAPS 0x141
27722 #define MC_CMD_MAE_GET_AR_CAPS_IN_LEN 0
27731 #define MC_CMD_MAE_GET_AR_CAPS_OUT_COUNT_OFST 0
27739 #define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_MINNUM 0
27748 #define MC_CMD_MAE_GET_OR_CAPS 0x142
27754 #define MC_CMD_MAE_GET_OR_CAPS_IN_LEN 0
27763 #define MC_CMD_MAE_GET_OR_CAPS_OUT_COUNT_OFST 0
27768 #define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_MINNUM 0
27778 #define MC_CMD_MAE_COUNTER_ALLOC 0x143
27788 #define MC_CMD_MAE_COUNTER_ALLOC_IN_REQUESTED_COUNT_OFST 0
27794 #define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_REQUESTED_COUNT_OFST 0
27812 * counts wrap from 0xffffffff to 1.
27814 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_OFST 0
27816 /* enum: Generation counter 0 is reserved and unused. */
27817 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_INVALID 0x0
27831 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NULL 0xffffffff
27838 #define MC_CMD_MAE_COUNTER_FREE 0x144
27852 #define MC_CMD_MAE_COUNTER_FREE_IN_COUNTER_ID_COUNT_OFST 0
27864 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_ID_COUNT_OFST 0
27895 #define MC_CMD_MAE_COUNTER_FREE_OUT_GENERATION_COUNT_OFST 0
27927 #define MC_CMD_MAE_COUNTERS_STREAM_START 0x151
27933 * with COUNTER_TYPES_MASK=0x1 (i.e. AR counters only).
27937 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_QID_OFST 0
27946 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_LBN 0
27955 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_QID_OFST 0
27964 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_ZERO_SQUASH_DISABLE_LBN 0
27971 * 0x3 requests both AR and CT counters. A value of zero is invalid. Counter
27983 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_FLAGS_OFST 0
27985 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_OFST 0
27986 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_LBN 0
27994 #define MC_CMD_MAE_COUNTERS_STREAM_STOP 0x152
28002 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_IN_QID_OFST 0
28013 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_GENERATION_COUNT_OFST 0
28020 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LEN(num) (0+4*(num))
28021 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_NUM(len) (((len)-0)/4)
28023 * MAE_COUNTER_TYPE_AR==0, this response is backwards-compatible with V1. The
28029 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_OFST 0
28043 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS 0x153
28051 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_NUM_CREDITS_OFST 0
28055 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_OUT_LEN 0
28061 * header must be constructed as a valid packet with 0-length payload.
28067 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC 0x148
28078 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_ENCAP_TYPE_OFST 0
28082 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MINNUM 0
28088 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_OFST 0
28093 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_NULL 0xffffffff
28100 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE 0x149
28111 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_EH_ID_OFST 0
28117 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_MINNUM 0
28122 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_OUT_LEN 0
28129 #define MC_CMD_MAE_ENCAP_HEADER_FREE 0x14a
28138 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LEN(num) (0+4*(num))
28139 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_NUM(len) (((len)-0)/4)
28141 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_OFST 0
28151 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LEN(num) (0+4*(num))
28152 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_NUM(len) (((len)-0)/4)
28154 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_OFST 0
28169 #define MC_CMD_MAE_MAC_ADDR_ALLOC 0x15e
28177 #define MC_CMD_MAE_MAC_ADDR_ALLOC_IN_MAC_ADDR_OFST 0
28182 #define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_OFST 0
28187 #define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL 0xffffffff
28194 #define MC_CMD_MAE_MAC_ADDR_FREE 0x15f
28203 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_LEN(num) (0+4*(num))
28204 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_NUM(len) (((len)-0)/4)
28206 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_OFST 0
28216 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LEN(num) (0+4*(num))
28217 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_NUM(len) (((len)-0)/4)
28219 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_OFST 0
28233 #define MC_CMD_MAE_ACTION_SET_ALLOC 0x14d
28240 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAGS_OFST 0
28242 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_OFST 0
28243 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_LBN 0
28245 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_OFST 0
28248 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DECAP_OFST 0
28251 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_OFST 0
28254 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAG_OFST 0
28257 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_OFST 0
28260 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_OFST 0
28263 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_OFST 0
28266 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_OFST 0
28281 /* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
28321 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_OFST 0
28323 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_OFST 0
28324 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_LBN 0
28326 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_OFST 0
28329 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_OFST 0
28332 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_OFST 0
28335 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_OFST 0
28338 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_OFST 0
28341 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_OFST 0
28344 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_OFST 0
28347 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_OFST 0
28362 /* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
28405 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_LBN 0
28422 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_LBN 0
28446 #define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_OFST 0
28450 #define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_ACTION_SET_ID_NULL 0xffffffff
28456 #define MC_CMD_MAE_ACTION_SET_FREE 0x14e
28465 #define MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(num) (0+4*(num))
28466 #define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_NUM(len) (((len)-0)/4)
28468 #define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_OFST 0
28478 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(num) (0+4*(num))
28479 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_NUM(len) (((len)-0)/4)
28481 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_OFST 0
28496 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC 0x14f
28508 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_COUNT_OFST 0
28530 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_OFST 0
28535 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ACTION_SET_LIST_ID_NULL 0xffffffff
28542 #define MC_CMD_MAE_ACTION_SET_LIST_FREE 0x150
28551 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LEN(num) (0+4*(num))
28552 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_NUM(len) (((len)-0)/4)
28554 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_OFST 0
28564 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LEN(num) (0+4*(num))
28565 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_NUM(len) (((len)-0)/4)
28567 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_OFST 0
28580 #define MC_CMD_MAE_OUTER_RULE_INSERT 0x15a
28592 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE_OFST 0
28606 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_CT_LBN 0
28636 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_MINNUM 0
28642 #define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_OFST 0
28646 #define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL 0xffffffff
28652 #define MC_CMD_MAE_OUTER_RULE_REMOVE 0x15b
28661 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(num) (0+4*(num))
28662 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_NUM(len) (((len)-0)/4)
28664 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_OFST 0
28674 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(num) (0+4*(num))
28675 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_NUM(len) (((len)-0)/4)
28677 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_OFST 0
28688 #define MC_CMD_MAE_OUTER_RULE_UPDATE 0x17d
28696 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_OR_ID_OFST 0
28707 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_CT_LBN 0
28733 #define MC_CMD_MAE_OUTER_RULE_UPDATE_OUT_LEN 0
28737 #define MAE_ACTION_RULE_RESPONSE_ASL_ID_OFST 0
28739 #define MAE_ACTION_RULE_RESPONSE_ASL_ID_LBN 0
28753 #define MAE_ACTION_RULE_RESPONSE_DO_CT_LBN 0
28788 #define MC_CMD_MAE_ACTION_RULE_INSERT 0x15c
28800 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_PRIO_OFST 0
28811 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_MINNUM 0
28817 #define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_OFST 0
28821 #define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL 0xffffffff
28829 #define MC_CMD_MAE_ACTION_RULE_UPDATE 0x15d
28837 #define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_AR_ID_OFST 0
28844 #define MC_CMD_MAE_ACTION_RULE_UPDATE_OUT_LEN 0
28850 #define MC_CMD_MAE_ACTION_RULE_DELETE 0x155
28859 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(num) (0+4*(num))
28860 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_NUM(len) (((len)-0)/4)
28862 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_OFST 0
28872 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(num) (0+4*(num))
28873 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_NUM(len) (((len)-0)/4)
28875 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_OFST 0
28886 #define MC_CMD_MAE_MPORT_LOOKUP 0x160
28893 #define MC_CMD_MAE_MPORT_LOOKUP_IN_MPORT_SELECTOR_OFST 0
28898 #define MC_CMD_MAE_MPORT_LOOKUP_OUT_MPORT_ID_OFST 0
28907 #define MC_CMD_MAE_MPORT_ALLOC 0x163
28917 #define MC_CMD_MAE_MPORT_ALLOC_IN_TYPE_OFST 0
28924 #define MC_CMD_MAE_MPORT_ALLOC_IN_MPORT_TYPE_ALIAS 0x1
28929 #define MC_CMD_MAE_MPORT_ALLOC_IN_MPORT_TYPE_VNIC 0x2
28939 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_TYPE_OFST 0
28946 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_MPORT_TYPE_ALIAS 0x1
28951 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_MPORT_TYPE_VNIC 0x2
28967 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_TYPE_OFST 0
28974 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_MPORT_TYPE_ALIAS 0x1
28979 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_MPORT_TYPE_VNIC 0x2
28987 #define MC_CMD_MAE_MPORT_ALLOC_OUT_MPORT_ID_OFST 0
28993 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_MPORT_ID_OFST 0
29006 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_MPORT_ID_OFST 0
29014 #define MC_CMD_MAE_MPORT_FREE 0x164
29022 #define MC_CMD_MAE_MPORT_FREE_IN_MPORT_ID_OFST 0
29026 #define MC_CMD_MAE_MPORT_FREE_OUT_LEN 0
29030 #define MAE_MPORT_DESC_MPORT_ID_OFST 0
29032 #define MAE_MPORT_DESC_MPORT_ID_LBN 0
29042 #define MAE_MPORT_DESC_CAN_RECEIVE_ON_LBN 0
29059 #define MAE_MPORT_DESC_MPORT_TYPE_NET_PORT 0x0
29061 #define MAE_MPORT_DESC_MPORT_TYPE_ALIAS 0x1
29063 #define MAE_MPORT_DESC_MPORT_TYPE_VNIC 0x2
29097 #define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_FUNCTION 0x1 /* enum */
29098 #define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_PLUGIN 0x2 /* enum */
29116 #define MAE_MPORT_DESC_VF_IDX_NULL 0xffff
29127 #define MAE_MPORT_DESC_V2_MPORT_ID_OFST 0
29129 #define MAE_MPORT_DESC_V2_MPORT_ID_LBN 0
29139 #define MAE_MPORT_DESC_V2_CAN_RECEIVE_ON_LBN 0
29156 #define MAE_MPORT_DESC_V2_MPORT_TYPE_NET_PORT 0x0
29158 #define MAE_MPORT_DESC_V2_MPORT_TYPE_ALIAS 0x1
29160 #define MAE_MPORT_DESC_V2_MPORT_TYPE_VNIC 0x2
29194 #define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_FUNCTION 0x1 /* enum */
29195 #define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_PLUGIN 0x2 /* enum */
29213 #define MAE_MPORT_DESC_V2_VF_IDX_NULL 0xffff
29233 #define MC_CMD_MAE_MPORT_ENUMERATE 0x17c
29239 #define MC_CMD_MAE_MPORT_ENUMERATE_IN_LEN 0
29247 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_COUNT_OFST 0
29257 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MINNUM 0
29269 #define MC_CMD_MAE_MPORT_READ_JOURNAL 0x147
29277 #define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_OFST 0
29287 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_OFST 0
29289 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_OFST 0
29290 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_LBN 0
29303 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MINNUM 0
29313 #define TABLE_FIELD_DESCR_FIELD_ID_OFST 0
29317 #define TABLE_FIELD_DESCR_FIELD_ID_LBN 0
29335 #define TABLE_FIELD_DESCR_MASK_NEVER 0x0
29337 #define TABLE_FIELD_DESCR_MASK_EXACT 0x1
29339 #define TABLE_FIELD_DESCR_MASK_TERNARY 0x2
29340 /* enum: Whole field match: mask must be all 1 bits, or all 0 bits. */
29341 #define TABLE_FIELD_DESCR_MASK_WHOLE_FIELD 0x3
29342 /* enum: Longest prefix match: mask must be 1 bit(s) followed by 0 bit(s). */
29343 #define TABLE_FIELD_DESCR_MASK_LPM 0x4
29347 * currently use version 0.
29359 #define MC_CMD_TABLE_LIST 0x1c9
29366 /* Index of the first item to be returned in the TABLE_ID sequence. (Set to 0
29370 #define MC_CMD_TABLE_LIST_IN_FIRST_TABLE_ID_INDEX_OFST 0
29380 #define MC_CMD_TABLE_LIST_OUT_N_TABLES_OFST 0
29388 #define MC_CMD_TABLE_LIST_OUT_TABLE_ID_MINNUM 0
29401 #define MC_CMD_TABLE_DESCRIPTOR 0x1ca
29409 #define MC_CMD_TABLE_DESCRIPTOR_IN_TABLE_ID_OFST 0
29413 /* Index of the first item to be returned in the FIELDS sequence. (Set to 0 for
29427 #define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_ENTRIES_OFST 0
29439 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_DIRECT 0x1
29441 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_BCAM 0x2
29445 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_TCAM 0x3
29449 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_STCAM 0x4
29462 /* Number of priorities for STCAM or TCAM; otherwise 0. The priority of a table
29464 * 0=highest to N_PRIORITIES-1=lowest.
29468 /* Maximum number of masks for STCAM; otherwise 0. */
29475 #define MC_CMD_TABLE_DESCRIPTOR_OUT_ALLOC_MASKS_LBN 0
29480 * always set to 0 indicating the original MC_CMD_TABLE_INSERT/UPDATE/DELETE
29513 #define MC_CMD_TABLE_INSERT 0x1cd
29525 #define MC_CMD_TABLE_INSERT_IN_TABLE_ID_OFST 0
29532 /* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM
29539 * data is required and this must be 0).
29544 * reports ALLOC_MASKS==1. Otherwise set to 0.
29548 /* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
29551 /* (32-bit alignment padding - set to 0) */
29554 /* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0)
29558 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
29560 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
29569 #define MC_CMD_TABLE_INSERT_OUT_LEN 0
29580 #define MC_CMD_TABLE_UPDATE 0x1ce
29592 #define MC_CMD_TABLE_UPDATE_IN_TABLE_ID_OFST 0
29599 /* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM
29606 * data is required and this must be 0).
29611 * reports ALLOC_MASKS==1. Otherwise set to 0.
29615 /* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
29618 /* (32-bit alignment padding - set to 0) */
29621 /* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0)
29625 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
29627 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
29636 #define MC_CMD_TABLE_UPDATE_OUT_LEN 0
29647 #define MC_CMD_TABLE_DELETE 0x1cf
29659 #define MC_CMD_TABLE_DELETE_IN_TABLE_ID_OFST 0
29666 /* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM
29673 * data is required and this must be 0).
29678 * reports ALLOC_MASKS==1. Otherwise set to 0.
29682 /* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
29685 /* (32-bit alignment padding - set to 0) */
29688 /* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0)
29692 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
29694 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
29703 #define MC_CMD_TABLE_DELETE_OUT_LEN 0