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1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
36 #define MC_SMEM_P0_DOORBELL_OFST 0x000
37 #define MC_SMEM_P1_DOORBELL_OFST 0x004
38 /* The rest of these are firmware-defined */
39 #define MC_SMEM_P0_PDU_OFST 0x008
40 #define MC_SMEM_P1_PDU_OFST 0x108
41 #define MC_SMEM_PDU_LEN 0x100
42 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
43 #define MC_SMEM_P0_STATUS_OFST 0x7f8
44 #define MC_SMEM_P1_STATUS_OFST 0x7fc
46 /* Values to be written to the per-port status dword in shared
48 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
49 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
52 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
57 * least every driver must support version 0 and MCDI_PCOL_VERSION
61 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
68 * 0 7 8 16 20 22 23 24 31
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
94 #define MCDI_HEADER_OFST 0
95 #define MCDI_HEADER_CODE_LBN 0
102 #define MCDI_HEADER_SEQ_WIDTH 4
114 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
116 #define MCDI_HEADER_XFLAGS_DBRET 0x02
119 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
120 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400
126 * - To advance a shared memory request if XFLAGS_EVREQ was set
127 * - As a notification (link state, i2c event), controlled
132 * 0 32 33 36 44 52 60
139 * - LEVEL==INFO Command succeeded
140 * - LEVEL==ERR Command failed
142 * 0 8 16 24 32
146 * LEVEL==ERR, Datalen == 0 => Reboot
150 * examining the first byte which is 0xc0. This corresponds to the
151 * non-existent MCDI command MC_CMD_DEBUG_LOG.
153 * 0 7 8
154 * | command | Resync | = 0xc0
156 * Since the event is written in big-endian byte order, this works
157 * providing bits 56-63 of the event are 0xc0.
160 * | Rsvd | Code | = 0xc0
162 * Which means for convenience the event code is 0xc for all MC
165 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
168 #define MC_CMD_ERR_CODE_OFST 0
169 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
174 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
175 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
176 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
177 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
178 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
179 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
180 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
181 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
185 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
186 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
187 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
189 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
190 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
191 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
193 #define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
194 #define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
195 #define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)
198 #define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)
206 0, 0, 0 }
226 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
227 * stack ID (which must be in the range 1-255) along with an EVB port ID.
229 #define EVB_STACK_ID(n) (((n) & 0xff) << 16)
233 * may be followed by the (0-based) number of the first argument that
236 #define MC_CMD_ERR_ARG_OFST 4
240 * specific to Solarflare firmware should use values in the range 0x1000 -
241 * 0x10ff. The range 0x2000 - 0x20ff is reserved for private error codes (see
245 #define MC_CMD_ERR_EPERM 0x1
246 /* enum: Non-existent command target */
247 #define MC_CMD_ERR_ENOENT 0x2
249 #define MC_CMD_ERR_EINTR 0x4
251 #define MC_CMD_ERR_EIO 0x5
253 #define MC_CMD_ERR_EEXIST 0x6
255 #define MC_CMD_ERR_EAGAIN 0xb
257 #define MC_CMD_ERR_ENOMEM 0xc
259 #define MC_CMD_ERR_EACCES 0xd
261 #define MC_CMD_ERR_EBUSY 0x10
263 #define MC_CMD_ERR_ENODEV 0x13
265 #define MC_CMD_ERR_EINVAL 0x16
267 #define MC_CMD_ERR_ENOSPC 0x1c
268 /* enum: Read-only */
269 #define MC_CMD_ERR_EROFS 0x1e
271 #define MC_CMD_ERR_EPIPE 0x20
273 #define MC_CMD_ERR_ERANGE 0x22
274 /* enum: Non-recursive resource is already acquired */
275 #define MC_CMD_ERR_EDEADLK 0x23
277 #define MC_CMD_ERR_ENOSYS 0x26
279 #define MC_CMD_ERR_ETIME 0x3e
281 #define MC_CMD_ERR_ENOLINK 0x43
283 #define MC_CMD_ERR_EPROTO 0x47
285 #define MC_CMD_ERR_EBADMSG 0x4a
287 #define MC_CMD_ERR_ENOTSUP 0x5f
289 #define MC_CMD_ERR_EADDRNOTAVAIL 0x63
291 #define MC_CMD_ERR_ENOTCONN 0x6b
293 #define MC_CMD_ERR_EALREADY 0x72
296 #define MC_CMD_ERR_ESTALE 0x74
298 #define MC_CMD_ERR_ALLOC_FAIL 0x1000
299 /* enum: V-adaptor not found. */
300 #define MC_CMD_ERR_NO_VADAPTOR 0x1001
302 #define MC_CMD_ERR_NO_EVB_PORT 0x1002
303 /* enum: V-switch not found. */
304 #define MC_CMD_ERR_NO_VSWITCH 0x1003
306 #define MC_CMD_ERR_VLAN_LIMIT 0x1004
308 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
310 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
311 /* enum: Invalid v-switch type. */
312 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
313 /* enum: Invalid v-port type. */
314 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
316 #define MC_CMD_ERR_MAC_EXIST 0x1009
318 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
320 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
322 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c
327 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
329 #define MC_CMD_ERR_VLAN_EXIST 0x100e
331 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f
334 * event and then resend its request. This error code is followed by a 32-bit
337 #define MC_CMD_ERR_PROXY_PENDING 0x1010
342 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
347 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
349 * an operation failed due to lack of SR-IOV privilege. Normally it is
354 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013
358 * sub-variant switching.
360 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014
364 #define MC_CMD_ERR_NO_CLOCK 0x1015
368 #define MC_CMD_ERR_UNREACHABLE 0x1016
372 #define MC_CMD_ERR_QUEUE_FULL 0x1017
377 #define MC_CMD_ERR_NO_PCIE 0x1018
382 #define MC_CMD_ERR_NO_DATAPATH 0x1019
384 #define MC_CMD_ERR_VIS_PRESENT 0x101a
388 #define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
392 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
393 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */
396 #define MC_CMD_FPGA_FLASH_PRIMARY 0x0 /* enum */
397 #define MC_CMD_FPGA_FLASH_SECONDARY 0x1 /* enum */
400 /* enum: Legacy mode as described in XN-200039-TC. */
401 #define MC_CMD_EXTERNAL_MAE_LINK_MODE_LEGACY 0x0
402 /* enum: Switchdev mode as described in XN-200039-TC. */
403 #define MC_CMD_EXTERNAL_MAE_LINK_MODE_SWITCHDEV 0x1
404 /* enum: Bootstrap mode as described in XN-200039-TC. */
405 #define MC_CMD_EXTERNAL_MAE_LINK_MODE_BOOTSTRAP 0x2
406 /* enum: Link-mode change is in-progress as described in XN-200039-TC. */
407 #define MC_CMD_EXTERNAL_MAE_LINK_MODE_PENDING 0xf
422 #define PCIE_INTERFACE_HOST_PRIMARY 0x0
424 * an on-NIC ARM module is expected to be connected.
426 #define PCIE_INTERFACE_NIC_EMBEDDED 0x1
431 #define PCIE_INTERFACE_CALLER 0xffffffff
435 #define MC_CMD_CLIENT_ID_SELF 0xffffffff
447 * and must never set a non-zero mask value for this field.
449 #define MAE_FIELD_UNSUPPORTED 0x0
454 #define MAE_FIELD_SUPPORTED_MATCH_NEVER 0x1
459 #define MAE_FIELD_SUPPORTED_MATCH_ALWAYS 0x2
465 #define MAE_FIELD_SUPPORTED_MATCH_OPTIONAL 0x3
471 #define MAE_FIELD_SUPPORTED_MATCH_PREFIX 0x4
475 #define MAE_FIELD_SUPPORTED_MATCH_MASK 0x5
478 * lookup. (Values are not arbitrary - constrained by table access ABI.)
481 #define MAE_CT_VNI_MODE_ZERO 0x0
485 #define MAE_CT_VNI_MODE_VNI 0x1
489 #define MAE_CT_VNI_MODE_1VLAN 0x2
493 #define MAE_CT_VNI_MODE_2VLAN 0x3
498 #define MAE_FIELD_INGRESS_PORT 0x0
499 #define MAE_FIELD_MARK 0x1 /* enum */
503 #define MAE_FIELD_RECIRC_ID 0x2
504 #define MAE_FIELD_IS_IP_FRAG 0x3 /* enum */
505 #define MAE_FIELD_DO_CT 0x4 /* enum */
506 #define MAE_FIELD_CT_HIT 0x5 /* enum */
508 #define MAE_FIELD_CT_MARK 0x6
510 #define MAE_FIELD_CT_DOMAIN 0x7
512 #define MAE_FIELD_CT_PRIVATE_FLAGS 0x8
513 /* enum: 1 if the packet ingressed the NIC from one of the MACs, else 0. */
514 #define MAE_FIELD_IS_FROM_NETWORK 0x9
515 /* enum: 1 if the packet has 1 or more VLAN tags, else 0. */
516 #define MAE_FIELD_HAS_OVLAN 0xa
517 /* enum: 1 if the packet has 2 or more VLAN tags, else 0. */
518 #define MAE_FIELD_HAS_IVLAN 0xb
519 /* enum: 1 if the outer packet has 1 or more VLAN tags, else 0; only present
522 #define MAE_FIELD_ENC_HAS_OVLAN 0xc
523 /* enum: 1 if the outer packet has 2 or more VLAN tags, else 0; only present
526 #define MAE_FIELD_ENC_HAS_IVLAN 0xd
528 #define MAE_FIELD_ENC_IP_FRAG 0xe
529 #define MAE_FIELD_ETHER_TYPE 0x21 /* enum */
530 #define MAE_FIELD_VLAN0_TCI 0x22 /* enum */
531 #define MAE_FIELD_VLAN0_PROTO 0x23 /* enum */
532 #define MAE_FIELD_VLAN1_TCI 0x24 /* enum */
533 #define MAE_FIELD_VLAN1_PROTO 0x25 /* enum */
535 #define MAE_FIELD_ETH_SADDR 0x28
537 #define MAE_FIELD_ETH_DADDR 0x29
539 #define MAE_FIELD_SRC_IP4 0x2a
541 #define MAE_FIELD_SRC_IP6 0x2b
543 #define MAE_FIELD_DST_IP4 0x2c
545 #define MAE_FIELD_DST_IP6 0x2d
547 #define MAE_FIELD_IP_PROTO 0x2e
549 #define MAE_FIELD_IP_TOS 0x2f
551 #define MAE_FIELD_IP_TTL 0x30
554 * matching? TODO: there was a proposal for driver-allocation fields. The
560 #define MAE_FIELD_IP_FLAGS 0x31
562 #define MAE_FIELD_L4_SPORT 0x32
564 #define MAE_FIELD_L4_DPORT 0x33
566 #define MAE_FIELD_TCP_FLAGS 0x34
568 #define MAE_FIELD_TCP_SYN_FIN_RST 0x35
569 /* enum: Packet is IP fragment with fragment offset 0 */
570 #define MAE_FIELD_IP_FIRST_FRAG 0x36
574 #define MAE_FIELD_ENCAP_TYPE 0x3f
578 #define MAE_FIELD_OUTER_RULE_ID 0x40
580 #define MAE_FIELD_ENC_ETHER_TYPE 0x41
582 #define MAE_FIELD_ENC_VLAN0_TCI 0x42
584 #define MAE_FIELD_ENC_VLAN0_PROTO 0x43
586 #define MAE_FIELD_ENC_VLAN1_TCI 0x44
588 #define MAE_FIELD_ENC_VLAN1_PROTO 0x45
590 #define MAE_FIELD_ENC_ETH_SADDR 0x48
592 #define MAE_FIELD_ENC_ETH_DADDR 0x49
594 #define MAE_FIELD_ENC_SRC_IP4 0x4a
596 #define MAE_FIELD_ENC_SRC_IP6 0x4b
598 #define MAE_FIELD_ENC_DST_IP4 0x4c
600 #define MAE_FIELD_ENC_DST_IP6 0x4d
602 #define MAE_FIELD_ENC_IP_PROTO 0x4e
604 #define MAE_FIELD_ENC_IP_TOS 0x4f
606 #define MAE_FIELD_ENC_IP_TTL 0x50
608 #define MAE_FIELD_ENC_IP_FLAGS 0x51
610 #define MAE_FIELD_ENC_L4_SPORT 0x52
612 #define MAE_FIELD_ENC_L4_DPORT 0x53
616 #define MAE_FIELD_ENC_VNET_ID 0x54
620 * should be treated same as NONE. (Values are not arbitrary - constrained by
623 #define MAE_MCDI_ENCAP_TYPE_NONE 0x0 /* enum */
625 #define MAE_MCDI_ENCAP_TYPE_VXLAN 0x1
626 #define MAE_MCDI_ENCAP_TYPE_NVGRE 0x2 /* enum */
627 #define MAE_MCDI_ENCAP_TYPE_GENEVE 0x3 /* enum */
628 #define MAE_MCDI_ENCAP_TYPE_L2GRE 0x4 /* enum */
634 #define MAE_MPORT_END_MAE 0x1
636 #define MAE_MPORT_END_VNIC 0x2
641 * from CT counter 42. Generation counts are also type-specific. This value is
645 /* enum: Action Rule counters - can be referenced in AR response. */
646 #define MAE_COUNTER_TYPE_AR 0x0
647 /* enum: Conntrack counters - can be referenced in CT response. */
648 #define MAE_COUNTER_TYPE_CT 0x1
649 /* enum: Outer Rule counters - can be referenced in OR response. */
650 #define MAE_COUNTER_TYPE_OR 0x2
652 /* TABLE_ID enum: Unique IDs for tables. The 32-bit ID values have been
653 * structured with bits [31:24] reserved (0), [23:16] indicating which major
654 * block the tables belongs to (0=VNIC TX, none currently; 1=MAE; 2=VNIC RX),
655 * [15:8] a unique ID within the block, and [7:0] reserved for future
658 * all supported - MC_CMD_TABLE_LIST returns the list of actually supported
661 /* enum: Outer_Rule_Table in the MAE - refer to SF-123102-TC. */
662 #define TABLE_ID_OUTER_RULE_TABLE 0x10000
663 /* enum: Outer_Rule_No_CT_Table in the MAE - refer to SF-123102-TC. */
664 #define TABLE_ID_OUTER_RULE_NO_CT_TABLE 0x10100
665 /* enum: Mgmt_Filter_Table in the MAE - refer to SF-123102-TC. */
666 #define TABLE_ID_MGMT_FILTER_TABLE 0x10200
667 /* enum: Conntrack_Table in the MAE - refer to SF-123102-TC. */
668 #define TABLE_ID_CONNTRACK_TABLE 0x10300
669 /* enum: Action_Rule_Table in the MAE - refer to SF-123102-TC. */
670 #define TABLE_ID_ACTION_RULE_TABLE 0x10400
671 /* enum: Mgroup_Default_Action_Set_Table in the MAE - refer to SF-123102-TC. */
672 #define TABLE_ID_MGROUP_DEFAULT_ACTION_SET_TABLE 0x10500
673 /* enum: Encap_Hdr_Part1_Table in the MAE - refer to SF-123102-TC. */
674 #define TABLE_ID_ENCAP_HDR_PART1_TABLE 0x10600
675 /* enum: Encap_Hdr_Part2_Table in the MAE - refer to SF-123102-TC. */
676 #define TABLE_ID_ENCAP_HDR_PART2_TABLE 0x10700
677 /* enum: Replace_Src_MAC_Table in the MAE - refer to SF-123102-TC. */
678 #define TABLE_ID_REPLACE_SRC_MAC_TABLE 0x10800
679 /* enum: Replace_Dst_MAC_Table in the MAE - refer to SF-123102-TC. */
680 #define TABLE_ID_REPLACE_DST_MAC_TABLE 0x10900
681 /* enum: Dst_Mport_VC_Table in the MAE - refer to SF-123102-TC. */
682 #define TABLE_ID_DST_MPORT_VC_TABLE 0x10a00
683 /* enum: LACP_LAG_Config_Table in the MAE - refer to SF-123102-TC. */
684 #define TABLE_ID_LACP_LAG_CONFIG_TABLE 0x10b00
685 /* enum: LACP_Balance_Table in the MAE - refer to SF-123102-TC. */
686 #define TABLE_ID_LACP_BALANCE_TABLE 0x10c00
687 /* enum: Dst_Mport_Host_Chan_Table in the MAE - refer to SF-123102-TC. */
688 #define TABLE_ID_DST_MPORT_HOST_CHAN_TABLE 0x10d00
689 /* enum: VNIC_Rx_Encap_Table in VNIC Rx - refer to SF-123102-TC. */
690 #define TABLE_ID_VNIC_RX_ENCAP_TABLE 0x20000
691 /* enum: Steering_Table in VNIC Rx - refer to SF-123102-TC. */
692 #define TABLE_ID_STEERING_TABLE 0x20100
693 /* enum: RSS_Context_Table in VNIC Rx - refer to SF-123102-TC. */
694 #define TABLE_ID_RSS_CONTEXT_TABLE 0x20200
695 /* enum: Indirection_Table in VNIC Rx - refer to SF-123102-TC. */
696 #define TABLE_ID_INDIRECTION_TABLE 0x20300
699 * types; can be calculated by (((ether_type_msb >> 2) & 0x4) ^ 0x4) |
700 * (ether_type_msb & 0x3);
702 #define TABLE_COMPRESSED_VLAN_TPID_8100 0x5 /* enum */
703 #define TABLE_COMPRESSED_VLAN_TPID_88A8 0x4 /* enum */
704 #define TABLE_COMPRESSED_VLAN_TPID_9100 0x1 /* enum */
705 #define TABLE_COMPRESSED_VLAN_TPID_9200 0x2 /* enum */
706 #define TABLE_COMPRESSED_VLAN_TPID_9300 0x3 /* enum */
709 #define TABLE_NAT_DIR_SOURCE 0x0 /* enum */
710 #define TABLE_NAT_DIR_DEST 0x1 /* enum */
717 #define TABLE_RSS_KEY_MODE_SA_DA 0x0
719 #define TABLE_RSS_KEY_MODE_SA_DA_SP_DP 0x1
721 #define TABLE_RSS_KEY_MODE_SA 0x2
723 #define TABLE_RSS_KEY_MODE_DA 0x3
725 #define TABLE_RSS_KEY_MODE_SA_SP 0x4
727 #define TABLE_RSS_KEY_MODE_DA_DP 0x5
728 /* enum: Nothing (produces input of 0, resulting in output hash of 0) */
729 #define TABLE_RSS_KEY_MODE_NONE 0x7
733 #define TABLE_RSS_SPREAD_MODE_INDIRECTION 0x0
735 #define TABLE_RSS_SPREAD_MODE_EVEN 0x1
741 * corresponding table definitions in SF-123102-TC; however, the mapping should
749 * the field is unused and should be set to 0 (or masked out if permitted by
752 #define TABLE_FIELD_ID_UNUSED 0x0
753 /* enum: Source m-port (a full m-port label). */
754 #define TABLE_FIELD_ID_SRC_MPORT 0x1
755 /* enum: Destination m-port (a full m-port label). */
756 #define TABLE_FIELD_ID_DST_MPORT 0x2
757 /* enum: Source m-group ID. */
758 #define TABLE_FIELD_ID_SRC_MGROUP_ID 0x3
759 /* enum: Physical network port ID (or m-port ID; same thing, for physical
762 #define TABLE_FIELD_ID_NETWORK_PORT_ID 0x4
765 #define TABLE_FIELD_ID_IS_FROM_NETWORK 0x5
767 #define TABLE_FIELD_ID_CH_VC 0x6
769 #define TABLE_FIELD_ID_CH_VC_LOW 0x7
771 #define TABLE_FIELD_ID_USER_MARK 0x8
773 #define TABLE_FIELD_ID_USER_FLAG 0x9
774 /* enum: Counter ID associated with a response. All-bits-1 is a null value to
777 #define TABLE_FIELD_ID_COUNTER_ID 0xa
782 #define TABLE_FIELD_ID_DISCRIM 0xb
784 * 48-bit value for this field is in network order, i.e. a MAC address of
785 * AA:BB:CC:DD:EE:FF becomes a 48-bit value of 0xAABBCCDDEEFF.
787 #define TABLE_FIELD_ID_DST_MAC 0x14
789 #define TABLE_FIELD_ID_SRC_MAC 0x15
791 #define TABLE_FIELD_ID_OVLAN_TPID_COMPRESSED 0x16
793 #define TABLE_FIELD_ID_OVLAN 0x17
794 /* enum: Outer VLAN ID (least significant 12 bits of full 16-bit TCI) only. */
795 #define TABLE_FIELD_ID_OVLAN_VID 0x18
797 #define TABLE_FIELD_ID_IVLAN_TPID_COMPRESSED 0x19
799 #define TABLE_FIELD_ID_IVLAN 0x1a
800 /* enum: Inner VLAN ID (least significant 12 bits of full 16-bit TCI) only. */
801 #define TABLE_FIELD_ID_IVLAN_VID 0x1b
803 #define TABLE_FIELD_ID_ETHER_TYPE 0x1c
805 * frame to the 128-bit value for this field is in network order, with IPv4
807 * [2345::6789:ABCD] is 0x2345000000000000000000006789ABCD; the IPv4 address
808 * 192.168.1.2 is 0xC0A80102000000000000000000000000.
810 #define TABLE_FIELD_ID_SRC_IP 0x1d
812 #define TABLE_FIELD_ID_DST_IP 0x1e
813 /* enum: IPv4 Type-of-Service or IPv6 Traffic Class field. */
814 #define TABLE_FIELD_ID_IP_TOS 0x1f
816 #define TABLE_FIELD_ID_IP_PROTO 0x20
817 /* enum: Layer 4 source port. */
818 #define TABLE_FIELD_ID_SRC_PORT 0x21
819 /* enum: Layer 4 destination port. */
820 #define TABLE_FIELD_ID_DST_PORT 0x22
822 #define TABLE_FIELD_ID_TCP_FLAGS 0x23
824 #define TABLE_FIELD_ID_VNI 0x24
826 #define TABLE_FIELD_ID_HAS_ENCAP 0x32
828 #define TABLE_FIELD_ID_HAS_ENC_OVLAN 0x33
830 #define TABLE_FIELD_ID_HAS_ENC_IVLAN 0x34
832 #define TABLE_FIELD_ID_HAS_ENC_IP 0x35
834 #define TABLE_FIELD_ID_HAS_ENC_IP4 0x36
836 #define TABLE_FIELD_ID_HAS_ENC_UDP 0x37
838 #define TABLE_FIELD_ID_HAS_OVLAN 0x38
840 #define TABLE_FIELD_ID_HAS_IVLAN 0x39
842 #define TABLE_FIELD_ID_HAS_IP 0x3a
845 #define TABLE_FIELD_ID_HAS_L4 0x3b
847 #define TABLE_FIELD_ID_IP_FRAG 0x3c
848 /* enum: True if only/inner frame is the first IP fragment (fragment offset 0).
850 #define TABLE_FIELD_ID_IP_FIRST_FRAG 0x3d
851 /* enum: True if only/inner frame has an IP Time-To-Live of <= 1. (Note: the
853 * with TTL=0 - which we shouldn't be seeing! - as well.)
855 #define TABLE_FIELD_ID_IP_TTL_LE_ONE 0x3e
857 #define TABLE_FIELD_ID_TCP_INTERESTING_FLAGS 0x3f
859 #define TABLE_FIELD_ID_RDP_PL_CHAN 0x50
861 #define TABLE_FIELD_ID_RDP_C_PL_EN 0x51
863 #define TABLE_FIELD_ID_RDP_C_PL 0x52
865 #define TABLE_FIELD_ID_RDP_D_PL_EN 0x53
867 #define TABLE_FIELD_ID_RDP_D_PL 0x54
869 #define TABLE_FIELD_ID_RDP_OUT_HOST_CHAN_EN 0x55
871 #define TABLE_FIELD_ID_RDP_OUT_HOST_CHAN 0x56
873 #define TABLE_FIELD_ID_RECIRC_ID 0x64
875 #define TABLE_FIELD_ID_DOMAIN 0x65
876 /* enum: Construction mode for encap_tunnel_id - see MAE_CT_VNI_MODE enum. */
877 #define TABLE_FIELD_ID_CT_VNI_MODE 0x66
880 #define TABLE_FIELD_ID_CT_TCP_FLAGS_INHIBIT 0x67
882 #define TABLE_FIELD_ID_DO_CT_IP4_TCP 0x68
884 #define TABLE_FIELD_ID_DO_CT_IP4_UDP 0x69
886 #define TABLE_FIELD_ID_DO_CT_IP6_TCP 0x6a
888 #define TABLE_FIELD_ID_DO_CT_IP6_UDP 0x6b
890 #define TABLE_FIELD_ID_OUTER_RULE_ID 0x6c
891 /* enum: Encapsulation type - see MAE_MCDI_ENCAP_TYPE enum. */
892 #define TABLE_FIELD_ID_ENCAP_TYPE 0x6d
893 /* enum: Encap tunnel ID for conntrack lookups from VNI, VLAN tag(s), or 0,
896 #define TABLE_FIELD_ID_ENCAP_TUNNEL_ID 0x78
898 #define TABLE_FIELD_ID_CT_ENTRY_ID 0x79
900 #define TABLE_FIELD_ID_NAT_PORT 0x7a
903 * byte mapped to a 32-bit value in network order, i.e. the IPv4 address
904 * 192.168.1.2 is the value 0xC0A80102.
906 #define TABLE_FIELD_ID_NAT_IP 0x7b
907 /* enum: NAT direction: 0=>source, 1=>destination. */
908 #define TABLE_FIELD_ID_NAT_DIR 0x7c
912 #define TABLE_FIELD_ID_CT_MARK 0x7d
914 #define TABLE_FIELD_ID_CT_PRIV_FLAGS 0x7e
916 #define TABLE_FIELD_ID_CT_HIT 0x7f
917 /* enum: True to suppress delivery when source and destination m-ports match.
919 #define TABLE_FIELD_ID_SUPPRESS_SELF_DELIVERY 0x8c
921 #define TABLE_FIELD_ID_DO_DECAP 0x8d
923 #define TABLE_FIELD_ID_DECAP_DSCP_COPY 0x8e
925 #define TABLE_FIELD_ID_DECAP_ECN_RFC6040 0x8f
927 #define TABLE_FIELD_ID_DO_REPLACE_DSCP 0x90
929 #define TABLE_FIELD_ID_DO_REPLACE_ECN 0x91
930 /* enum: True to decrement IP Time-To-Live. */
931 #define TABLE_FIELD_ID_DO_DECR_IP_TTL 0x92
933 #define TABLE_FIELD_ID_DO_SRC_MAC 0x93
935 #define TABLE_FIELD_ID_DO_DST_MAC 0x94
936 /* enum: Number of VLAN tags to pop. Valid values are 0, 1, or 2. */
937 #define TABLE_FIELD_ID_DO_VLAN_POP 0x95
938 /* enum: Number of VLANs tags to push. Valid values are 0, 1, or 2. */
939 #define TABLE_FIELD_ID_DO_VLAN_PUSH 0x96
941 #define TABLE_FIELD_ID_DO_COUNT 0x97
943 #define TABLE_FIELD_ID_DO_ENCAP 0x98
945 #define TABLE_FIELD_ID_ENCAP_DSCP_COPY 0x99
947 #define TABLE_FIELD_ID_ENCAP_ECN_COPY 0x9a
949 #define TABLE_FIELD_ID_DO_DELIVER 0x9b
951 #define TABLE_FIELD_ID_DO_FLAG 0x9c
953 #define TABLE_FIELD_ID_DO_MARK 0x9d
956 #define TABLE_FIELD_ID_DO_SET_NET_CHAN 0x9e
957 /* enum: True to override the reported source m-port for host deliveries. */
958 #define TABLE_FIELD_ID_DO_SET_SRC_MPORT 0x9f
960 #define TABLE_FIELD_ID_ENCAP_HDR_ID 0xaa
962 #define TABLE_FIELD_ID_DSCP_VALUE 0xab
964 * DO_REPLACE_ECN is not set, ECN_CONTROL[0] and ECN_CONTROL[1] are set to
967 #define TABLE_FIELD_ID_ECN_CONTROL 0xac
969 #define TABLE_FIELD_ID_SRC_MAC_ID 0xad
971 #define TABLE_FIELD_ID_DST_MAC_ID 0xae
975 #define TABLE_FIELD_ID_REPORTED_SRC_MPORT_OR_NET_CHAN 0xaf
976 /* enum: 64-byte chunk of added encapsulation header. */
977 #define TABLE_FIELD_ID_CHUNK64 0xb4
978 /* enum: 32-byte chunk of added encapsulation header. */
979 #define TABLE_FIELD_ID_CHUNK32 0xb5
980 /* enum: 16-byte chunk of added encapsulation header. */
981 #define TABLE_FIELD_ID_CHUNK16 0xb6
982 /* enum: 8-byte chunk of added encapsulation header. */
983 #define TABLE_FIELD_ID_CHUNK8 0xb7
984 /* enum: 4-byte chunk of added encapsulation header. */
985 #define TABLE_FIELD_ID_CHUNK4 0xb8
986 /* enum: 2-byte chunk of added encapsulation header. */
987 #define TABLE_FIELD_ID_CHUNK2 0xb9
989 #define TABLE_FIELD_ID_HDR_LEN_W 0xba
991 #define TABLE_FIELD_ID_ENC_LACP_HASH_L23 0xbb
992 /* enum: Static value for layer 4 LACP hash of the encapsulation header. */
993 #define TABLE_FIELD_ID_ENC_LACP_HASH_L4 0xbc
996 * encapsulated packet to a LAG m-port.
998 #define TABLE_FIELD_ID_USE_ENC_LACP_HASHES 0xbd
1002 #define TABLE_FIELD_ID_DO_CT 0xc8
1005 #define TABLE_FIELD_ID_DO_NAT 0xc9
1007 #define TABLE_FIELD_ID_DO_RECIRC 0xca
1008 /* enum: Next action set payload ID for replay. The null value is all-1-bits.
1010 #define TABLE_FIELD_ID_NEXT_ACTION_SET_PAYLOAD 0xcb
1011 /* enum: Next action set row ID for replay. The null value is all-1-bits. */
1012 #define TABLE_FIELD_ID_NEXT_ACTION_SET_ROW 0xcc
1014 * null value is all-1-bits.
1016 #define TABLE_FIELD_ID_MC_ACTION_SET_PAYLOAD 0xcd
1018 * value is all-1-bits.
1020 #define TABLE_FIELD_ID_MC_ACTION_SET_ROW 0xce
1021 /* enum: True to include layer 4 in LACP hash on delivery to a LAG m-port. */
1022 #define TABLE_FIELD_ID_LACP_INC_L4 0xdc
1024 #define TABLE_FIELD_ID_LACP_PLUGIN 0xdd
1026 #define TABLE_FIELD_ID_BAL_TBL_BASE_DIV64 0xde
1027 /* enum: Length of balance table region: 0=>64, 1=>128, 2=>256. */
1028 #define TABLE_FIELD_ID_BAL_TBL_LEN_ID 0xdf
1029 /* enum: UDP port to match for UDP-based encapsulations; required to be 0 for
1032 #define TABLE_FIELD_ID_UDP_PORT 0xe6
1034 #define TABLE_FIELD_ID_RSS_ON_OUTER 0xe7
1038 #define TABLE_FIELD_ID_STEER_ON_OUTER 0xe8
1040 #define TABLE_FIELD_ID_DST_QID 0xf0
1042 #define TABLE_FIELD_ID_DROP 0xf1
1044 #define TABLE_FIELD_ID_VLAN_STRIP 0xf2
1046 * false to bitwise-OR the USER_MARK into it.
1048 #define TABLE_FIELD_ID_MARK_OVERRIDE 0xf3
1050 * false to bitwise-OR the USER_FLAG into it.
1052 #define TABLE_FIELD_ID_FLAG_OVERRIDE 0xf4
1054 #define TABLE_FIELD_ID_RSS_CTX_ID 0xfa
1056 #define TABLE_FIELD_ID_RSS_EN 0xfb
1058 #define TABLE_FIELD_ID_KEY 0xfc
1059 /* enum: Key mode for IPv4 TCP packets - see TABLE_RSS_KEY_MODE enum. */
1060 #define TABLE_FIELD_ID_TCP_V4_KEY_MODE 0xfd
1061 /* enum: Key mode for IPv6 TCP packets - see TABLE_RSS_KEY_MODE enum. */
1062 #define TABLE_FIELD_ID_TCP_V6_KEY_MODE 0xfe
1063 /* enum: Key mode for IPv4 UDP packets - see TABLE_RSS_KEY_MODE enum. */
1064 #define TABLE_FIELD_ID_UDP_V4_KEY_MODE 0xff
1065 /* enum: Key mode for IPv6 UDP packets - see TABLE_RSS_KEY_MODE enum. */
1066 #define TABLE_FIELD_ID_UDP_V6_KEY_MODE 0x100
1067 /* enum: Key mode for other IPv4 packets - see TABLE_RSS_KEY_MODE enum. */
1068 #define TABLE_FIELD_ID_OTHER_V4_KEY_MODE 0x101
1069 /* enum: Key mode for other IPv6 packets - see TABLE_RSS_KEY_MODE enum. */
1070 #define TABLE_FIELD_ID_OTHER_V6_KEY_MODE 0x102
1071 /* enum: Spreading mode - 0=>indirection; 1=>even. */
1072 #define TABLE_FIELD_ID_SPREAD_MODE 0x103
1075 * spread across (only values 1-255 are valid for this mode).
1077 #define TABLE_FIELD_ID_INDIR_TBL_BASE 0x104
1079 * within the Indirection_Table, where length = 32 << len_id. Must be set to 0
1082 #define TABLE_FIELD_ID_INDIR_TBL_LEN_ID 0x105
1084 #define TABLE_FIELD_ID_INDIR_OFFSET 0x106
1095 #define MCDI_EVENT_LEVEL_INFO 0x0
1097 #define MCDI_EVENT_LEVEL_WARN 0x1
1099 #define MCDI_EVENT_LEVEL_ERR 0x2
1101 #define MCDI_EVENT_LEVEL_FATAL 0x3
1102 #define MCDI_EVENT_DATA_OFST 0
1103 #define MCDI_EVENT_DATA_LEN 4
1104 #define MCDI_EVENT_CMDDONE_SEQ_OFST 0
1105 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0
1107 #define MCDI_EVENT_CMDDONE_DATALEN_OFST 0
1110 #define MCDI_EVENT_CMDDONE_ERRNO_OFST 0
1113 #define MCDI_EVENT_LINKCHANGE_LP_CAP_OFST 0
1114 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
1116 #define MCDI_EVENT_LINKCHANGE_SPEED_OFST 0
1118 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
1120 #define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
1122 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
1124 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
1126 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
1128 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
1130 #define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
1132 #define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
1134 #define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
1135 #define MCDI_EVENT_LINKCHANGE_FCNTL_OFST 0
1137 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
1138 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0
1141 #define MCDI_EVENT_SENSOREVT_MONITOR_OFST 0
1142 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
1144 #define MCDI_EVENT_SENSOREVT_STATE_OFST 0
1147 #define MCDI_EVENT_SENSOREVT_VALUE_OFST 0
1150 #define MCDI_EVENT_FWALERT_DATA_OFST 0
1153 #define MCDI_EVENT_FWALERT_REASON_OFST 0
1154 #define MCDI_EVENT_FWALERT_REASON_LBN 0
1157 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
1158 #define MCDI_EVENT_FLR_VF_OFST 0
1159 #define MCDI_EVENT_FLR_VF_LBN 0
1161 #define MCDI_EVENT_TX_ERR_TXQ_OFST 0
1162 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0
1164 #define MCDI_EVENT_TX_ERR_TYPE_OFST 0
1166 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
1167 /* enum: Descriptor loader reported failure. Specific to EF10-family NICs. */
1168 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
1170 * EF10-family NICs
1172 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2
1173 /* enum: Overlength packet. Specific to EF10-family NICs. */
1174 #define MCDI_EVENT_TX_ERR_2BIG 0x3
1175 /* enum: Malformed option descriptor. Specific to EF10-family NICs. */
1176 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5
1177 /* enum: Option descriptor part way through a packet. Specific to EF10-family
1180 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8
1181 /* enum: DMA or PIO data access error. Specific to EF10-family NICs */
1182 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
1183 #define MCDI_EVENT_TX_ERR_INFO_OFST 0
1186 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 0
1189 #define MCDI_EVENT_TX_FLUSH_TXQ_OFST 0
1190 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
1192 #define MCDI_EVENT_PTP_ERR_TYPE_OFST 0
1193 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
1196 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
1198 #define MCDI_EVENT_PTP_ERR_FILTER 0x2
1200 #define MCDI_EVENT_PTP_ERR_FIFO 0x3
1202 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4
1203 #define MCDI_EVENT_AOE_ERR_TYPE_OFST 0
1204 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0
1206 /* enum: AOE failed to load - no valid image? */
1207 #define MCDI_EVENT_AOE_NO_LOAD 0x1
1209 #define MCDI_EVENT_AOE_FC_ASSERT 0x2
1211 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3
1213 #define MCDI_EVENT_AOE_FC_NO_START 0x4
1214 /* enum: Generic AOE fault - likely to have been reported via other means too
1217 #define MCDI_EVENT_AOE_FAULT 0x5
1219 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
1221 #define MCDI_EVENT_AOE_LOAD 0x7
1223 #define MCDI_EVENT_AOE_DMA 0x8
1227 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9
1229 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
1231 #define MCDI_EVENT_AOE_PTP_STATUS 0xb
1233 #define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc
1235 #define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd
1237 #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe
1239 #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf
1241 #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10
1243 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11
1244 /* enum: FPGA boot-flash contains an invalid image header */
1245 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12
1247 #define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
1249 #define MCDI_EVENT_AOE_FC_RUNNING 0x14
1250 #define MCDI_EVENT_AOE_ERR_DATA_OFST 0
1253 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 0
1257 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0
1260 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
1261 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0
1265 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0
1267 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1
1269 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2
1271 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3
1273 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4
1275 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5
1277 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6
1279 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
1281 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
1282 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 0
1286 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
1288 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
1289 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 0
1292 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 0
1295 #define MCDI_EVENT_RX_ERR_RXQ_OFST 0
1296 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0
1298 #define MCDI_EVENT_RX_ERR_TYPE_OFST 0
1300 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
1301 #define MCDI_EVENT_RX_ERR_INFO_OFST 0
1304 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 0
1307 #define MCDI_EVENT_RX_FLUSH_RXQ_OFST 0
1308 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
1310 #define MCDI_EVENT_MC_REBOOT_COUNT_OFST 0
1311 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
1313 #define MCDI_EVENT_MUM_ERR_TYPE_OFST 0
1314 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0
1316 /* enum: MUM failed to load - no valid image? */
1317 #define MCDI_EVENT_MUM_NO_LOAD 0x1
1319 #define MCDI_EVENT_MUM_ASSERT 0x2
1321 #define MCDI_EVENT_MUM_WATCHDOG 0x3
1322 #define MCDI_EVENT_MUM_ERR_DATA_OFST 0
1325 #define MCDI_EVENT_DBRET_SEQ_OFST 0
1326 #define MCDI_EVENT_DBRET_SEQ_LBN 0
1328 #define MCDI_EVENT_SUC_ERR_TYPE_OFST 0
1329 #define MCDI_EVENT_SUC_ERR_TYPE_LBN 0
1332 #define MCDI_EVENT_SUC_BAD_APP 0x1
1334 #define MCDI_EVENT_SUC_ASSERT 0x2
1336 #define MCDI_EVENT_SUC_EXCEPTION 0x3
1338 #define MCDI_EVENT_SUC_WATCHDOG 0x4
1339 #define MCDI_EVENT_SUC_ERR_ADDRESS_OFST 0
1342 #define MCDI_EVENT_SUC_ERR_DATA_OFST 0
1345 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 0
1346 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 0
1348 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 0
1350 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4
1353 #define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 0
1356 #define MCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 0
1361 #define MCDI_EVENT_MODULECHANGE_LD_CAP_OFST 0
1362 #define MCDI_EVENT_MODULECHANGE_LD_CAP_LBN 0
1364 #define MCDI_EVENT_MODULECHANGE_SEQ_OFST 0
1367 #define MCDI_EVENT_DATA_LBN 0
1382 #define MCDI_EVENT_EV_CODE_WIDTH 4
1386 #define MCDI_EVENT_SW_EVENT 0x0
1388 #define MCDI_EVENT_CODE_BADSSERT 0x1
1390 #define MCDI_EVENT_CODE_PMNOTICE 0x2
1392 #define MCDI_EVENT_CODE_CMDDONE 0x3
1394 #define MCDI_EVENT_CODE_LINKCHANGE 0x4
1396 #define MCDI_EVENT_CODE_SENSOREVT 0x5
1398 #define MCDI_EVENT_CODE_SCHEDERR 0x6
1400 #define MCDI_EVENT_CODE_REBOOT 0x7
1402 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
1404 #define MCDI_EVENT_CODE_FWALERT 0x9
1406 #define MCDI_EVENT_CODE_FLR 0xa
1408 #define MCDI_EVENT_CODE_TX_ERR 0xb
1410 #define MCDI_EVENT_CODE_TX_FLUSH 0xc
1412 #define MCDI_EVENT_CODE_PTP_RX 0xd
1414 #define MCDI_EVENT_CODE_PTP_FAULT 0xe
1416 #define MCDI_EVENT_CODE_PTP_PPS 0xf
1418 #define MCDI_EVENT_CODE_RX_FLUSH 0x10
1420 #define MCDI_EVENT_CODE_RX_ERR 0x11
1422 #define MCDI_EVENT_CODE_AOE 0x12
1424 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13
1426 #define MCDI_EVENT_CODE_HW_PPS 0x14
1430 #define MCDI_EVENT_CODE_MC_REBOOT 0x15
1432 #define MCDI_EVENT_CODE_PAR_ERR 0x16
1434 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
1436 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
1438 #define MCDI_EVENT_CODE_MC_BIST 0x19
1440 #define MCDI_EVENT_CODE_PTP_TIME 0x1a
1442 #define MCDI_EVENT_CODE_MUM 0x1b
1444 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
1448 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
1452 #define MCDI_EVENT_CODE_DBRET 0x1e
1454 #define MCDI_EVENT_CODE_SUC 0x1f
1458 #define MCDI_EVENT_CODE_LINKCHANGE_V2 0x20
1463 #define MCDI_EVENT_CODE_MODULECHANGE 0x21
1469 #define MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x22
1475 #define MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23
1480 * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.
1482 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x24
1485 * SF-122927-TC for details.
1487 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x25
1491 * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0
1492 * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy
1494 * SF-122927-TC for details.
1496 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x26
1502 #define MCDI_EVENT_CODE_MPORT_JOURNAL_CHANGE 0x27
1506 #define MCDI_EVENT_CODE_TESTGEN 0xfa
1507 #define MCDI_EVENT_CMDDONE_DATA_OFST 0
1508 #define MCDI_EVENT_CMDDONE_DATA_LEN 4
1509 #define MCDI_EVENT_CMDDONE_DATA_LBN 0
1511 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
1512 #define MCDI_EVENT_LINKCHANGE_DATA_LEN 4
1513 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
1515 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0
1516 #define MCDI_EVENT_SENSOREVT_DATA_LEN 4
1517 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0
1519 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
1520 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4
1521 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
1523 #define MCDI_EVENT_TX_ERR_DATA_OFST 0
1524 #define MCDI_EVENT_TX_ERR_DATA_LEN 4
1525 #define MCDI_EVENT_TX_ERR_DATA_LBN 0
1530 #define MCDI_EVENT_PTP_SECONDS_OFST 0
1531 #define MCDI_EVENT_PTP_SECONDS_LEN 4
1532 #define MCDI_EVENT_PTP_SECONDS_LBN 0
1537 #define MCDI_EVENT_PTP_MAJOR_OFST 0
1538 #define MCDI_EVENT_PTP_MAJOR_LEN 4
1539 #define MCDI_EVENT_PTP_MAJOR_LBN 0
1544 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
1545 #define MCDI_EVENT_PTP_NANOSECONDS_LEN 4
1546 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
1551 #define MCDI_EVENT_PTP_MINOR_OFST 0
1552 #define MCDI_EVENT_PTP_MINOR_LEN 4
1553 #define MCDI_EVENT_PTP_MINOR_LBN 0
1557 #define MCDI_EVENT_PTP_UUID_OFST 0
1558 #define MCDI_EVENT_PTP_UUID_LEN 4
1559 #define MCDI_EVENT_PTP_UUID_LBN 0
1561 #define MCDI_EVENT_RX_ERR_DATA_OFST 0
1562 #define MCDI_EVENT_RX_ERR_DATA_LEN 4
1563 #define MCDI_EVENT_RX_ERR_DATA_LBN 0
1565 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0
1566 #define MCDI_EVENT_PAR_ERR_DATA_LEN 4
1567 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0
1569 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
1570 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4
1571 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
1573 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
1574 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4
1575 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
1578 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
1579 #define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4
1580 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
1582 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
1600 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
1610 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
1611 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4
1612 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
1614 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
1615 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4
1616 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
1619 * should resend it. A non-zero value means that the authorization has been
1624 #define MCDI_EVENT_DBRET_DATA_OFST 0
1625 #define MCDI_EVENT_DBRET_DATA_LEN 4
1626 #define MCDI_EVENT_DBRET_DATA_LBN 0
1628 #define MCDI_EVENT_LINKCHANGE_V2_DATA_OFST 0
1629 #define MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 4
1630 #define MCDI_EVENT_LINKCHANGE_V2_DATA_LBN 0
1632 #define MCDI_EVENT_MODULECHANGE_DATA_OFST 0
1633 #define MCDI_EVENT_MODULECHANGE_DATA_LEN 4
1634 #define MCDI_EVENT_MODULECHANGE_DATA_LBN 0
1637 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 0
1638 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4
1639 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 0
1642 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 0
1643 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4
1644 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 0
1647 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 0
1648 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4
1649 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 0
1654 #define MCDI_EVENT_DESC_PROXY_DATA_OFST 0
1655 #define MCDI_EVENT_DESC_PROXY_DATA_LEN 4
1656 #define MCDI_EVENT_DESC_PROXY_DATA_LBN 0
1659 #define MCDI_EVENT_DESC_PROXY_GENERATION_OFST 0
1660 #define MCDI_EVENT_DESC_PROXY_GENERATION_LEN 4
1661 #define MCDI_EVENT_DESC_PROXY_GENERATION_LBN 0
1664 * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63.
1666 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 0
1667 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4
1668 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0
1678 #define FCDI_EVENT_LEVEL_INFO 0x0
1680 #define FCDI_EVENT_LEVEL_WARN 0x1
1682 #define FCDI_EVENT_LEVEL_ERR 0x2
1684 #define FCDI_EVENT_LEVEL_FATAL 0x3
1685 #define FCDI_EVENT_DATA_OFST 0
1686 #define FCDI_EVENT_DATA_LEN 4
1687 #define FCDI_EVENT_LINK_STATE_STATUS_OFST 0
1688 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0
1690 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */
1691 #define FCDI_EVENT_LINK_UP 0x1 /* enum */
1692 #define FCDI_EVENT_DATA_LBN 0
1697 #define FCDI_EVENT_EV_CODE_WIDTH 4
1701 #define FCDI_EVENT_CODE_REBOOT 0x1
1703 #define FCDI_EVENT_CODE_ASSERT 0x2
1705 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
1707 #define FCDI_EVENT_CODE_LINK_STATE 0x4
1709 #define FCDI_EVENT_CODE_TIMED_READ 0x5
1711 #define FCDI_EVENT_CODE_PPS_IN 0x6
1713 #define FCDI_EVENT_CODE_PTP_TICK 0x7
1715 #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8
1717 #define FCDI_EVENT_CODE_PTP_STATUS 0x9
1718 /* enum: Port id config to map MC-FC port idx */
1719 #define FCDI_EVENT_CODE_PORT_CONFIG 0xa
1721 #define FCDI_EVENT_CODE_BOOT_RESULT 0xb
1724 #define FCDI_EVENT_REBOOT_FC_FW 0x0 /* enum */
1725 #define FCDI_EVENT_REBOOT_FC_BOOTLOADER 0x1 /* enum */
1726 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
1727 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LEN 4
1728 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
1734 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
1735 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LEN 4
1736 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
1738 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0
1739 #define FCDI_EVENT_LINK_STATE_DATA_LEN 4
1740 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0
1742 #define FCDI_EVENT_PTP_STATE_OFST 0
1743 #define FCDI_EVENT_PTP_STATE_LEN 4
1744 #define FCDI_EVENT_PTP_UNDEFINED 0x0 /* enum */
1745 #define FCDI_EVENT_PTP_SETUP_FAILED 0x1 /* enum */
1746 #define FCDI_EVENT_PTP_OPERATIONAL 0x2 /* enum */
1747 #define FCDI_EVENT_PTP_STATE_LBN 0
1751 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0
1752 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LEN 4
1753 #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0
1759 #define FCDI_EVENT_PORT_CONFIG_DATA_OFST 0
1760 #define FCDI_EVENT_PORT_CONFIG_DATA_LEN 4
1761 #define FCDI_EVENT_PORT_CONFIG_DATA_LBN 0
1763 #define FCDI_EVENT_BOOT_RESULT_OFST 0
1764 #define FCDI_EVENT_BOOT_RESULT_LEN 4
1767 #define FCDI_EVENT_BOOT_RESULT_LBN 0
1772 * such that bits 32-63 containing | event code, level, source etc remain the
1780 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_NUM(len) (((len)-8)/8)
1782 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
1783 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LEN 4
1784 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
1788 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LEN 4
1793 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LEN 4
1800 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_LEN 4
1804 #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_LEN 4
1820 #define MUM_EVENT_LEVEL_INFO 0x0
1822 #define MUM_EVENT_LEVEL_WARN 0x1
1824 #define MUM_EVENT_LEVEL_ERR 0x2
1826 #define MUM_EVENT_LEVEL_FATAL 0x3
1827 #define MUM_EVENT_DATA_OFST 0
1828 #define MUM_EVENT_DATA_LEN 4
1829 #define MUM_EVENT_SENSOR_ID_OFST 0
1830 #define MUM_EVENT_SENSOR_ID_LBN 0
1834 #define MUM_EVENT_SENSOR_STATE_OFST 0
1837 #define MUM_EVENT_PORT_PHY_READY_OFST 0
1838 #define MUM_EVENT_PORT_PHY_READY_LBN 0
1840 #define MUM_EVENT_PORT_PHY_LINK_UP_OFST 0
1843 #define MUM_EVENT_PORT_PHY_TX_LOL_OFST 0
1846 #define MUM_EVENT_PORT_PHY_RX_LOL_OFST 0
1849 #define MUM_EVENT_PORT_PHY_TX_LOS_OFST 0
1850 #define MUM_EVENT_PORT_PHY_TX_LOS_LBN 4
1852 #define MUM_EVENT_PORT_PHY_RX_LOS_OFST 0
1855 #define MUM_EVENT_PORT_PHY_TX_FAULT_OFST 0
1858 #define MUM_EVENT_DATA_LBN 0
1863 #define MUM_EVENT_EV_CODE_WIDTH 4
1867 #define MUM_EVENT_CODE_REBOOT 0x1
1869 #define MUM_EVENT_CODE_ASSERT 0x2
1871 #define MUM_EVENT_CODE_SENSOR 0x3
1873 #define MUM_EVENT_CODE_QSFP_LASI_INTERRUPT 0x4
1874 #define MUM_EVENT_SENSOR_DATA_OFST 0
1875 #define MUM_EVENT_SENSOR_DATA_LEN 4
1876 #define MUM_EVENT_SENSOR_DATA_LBN 0
1878 #define MUM_EVENT_PORT_PHY_FLAGS_OFST 0
1879 #define MUM_EVENT_PORT_PHY_FLAGS_LEN 4
1880 #define MUM_EVENT_PORT_PHY_FLAGS_LBN 0
1882 #define MUM_EVENT_PORT_PHY_COPPER_LEN_OFST 0
1883 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LEN 4
1884 #define MUM_EVENT_PORT_PHY_COPPER_LEN_LBN 0
1886 #define MUM_EVENT_PORT_PHY_CAPS_OFST 0
1887 #define MUM_EVENT_PORT_PHY_CAPS_LEN 4
1888 #define MUM_EVENT_PORT_PHY_CAPS_LBN 0
1890 #define MUM_EVENT_PORT_PHY_TECH_OFST 0
1891 #define MUM_EVENT_PORT_PHY_TECH_LEN 4
1892 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_UNKNOWN 0x0 /* enum */
1893 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_OPTICAL 0x1 /* enum */
1894 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE 0x2 /* enum */
1895 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_PASSIVE_EQUALIZED 0x3 /* enum */
1896 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LIMITING 0x4 /* enum */
1897 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_COPPER_ACTIVE_LINEAR 0x5 /* enum */
1898 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_BASE_T 0x6 /* enum */
1899 #define MUM_EVENT_PORT_PHY_STATE_QSFP_MODULE_TECH_LOOPBACK_PASSIVE 0x7 /* enum */
1900 #define MUM_EVENT_PORT_PHY_TECH_LBN 0
1903 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_WIDTH 4
1904 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_FLAGS 0x0 /* enum */
1905 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_COPPER_LEN 0x1 /* enum */
1906 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_CAPS 0x2 /* enum */
1907 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_TECH 0x3 /* enum */
1908 #define MUM_EVENT_PORT_PHY_SRC_DATA_ID_MAX 0x4 /* enum */
1910 #define MUM_EVENT_PORT_PHY_SRC_PORT_NO_WIDTH 4
1915 * Read multiple 32byte words from MC memory. Note - this command really
1919 #define MC_CMD_READ32 0x1
1926 #define MC_CMD_READ32_IN_ADDR_OFST 0
1927 #define MC_CMD_READ32_IN_ADDR_LEN 4
1928 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4
1929 #define MC_CMD_READ32_IN_NUMWORDS_LEN 4
1932 #define MC_CMD_READ32_OUT_LENMIN 4
1935 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1936 #define MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
1937 #define MC_CMD_READ32_OUT_BUFFER_OFST 0
1938 #define MC_CMD_READ32_OUT_BUFFER_LEN 4
1948 #define MC_CMD_WRITE32 0x2
1957 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
1958 #define MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4)
1959 #define MC_CMD_WRITE32_IN_ADDR_OFST 0
1960 #define MC_CMD_WRITE32_IN_ADDR_LEN 4
1961 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4
1962 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4
1968 #define MC_CMD_WRITE32_OUT_LEN 0
1973 * Copy MC code between two locations and jump. Note - this command really
1977 #define MC_CMD_COPYCODE 0x3
1990 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
1991 #define MC_CMD_COPYCODE_IN_SRC_ADDR_LEN 4
1993 #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000
1997 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
2002 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
2003 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_PRESENT_OFST 0
2006 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SATELLITE_CPUS_NOT_LOADED_OFST 0
2009 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_IGNORE_CONFIG_OFST 0
2012 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_OFST 0
2013 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_SKIP_BOOT_ICORE_SYNC_LBN 4
2015 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_FORCE_STANDALONE_OFST 0
2018 #define MC_CMD_COPYCODE_IN_BOOT_MAGIC_DISABLE_XIP_OFST 0
2022 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
2023 #define MC_CMD_COPYCODE_IN_DEST_ADDR_LEN 4
2025 #define MC_CMD_COPYCODE_IN_NUMWORDS_LEN 4
2028 #define MC_CMD_COPYCODE_IN_JUMP_LEN 4
2030 #define MC_CMD_COPYCODE_JUMP_NONE 0x1
2033 #define MC_CMD_COPYCODE_OUT_LEN 0
2038 * Select function for function-specific commands.
2040 #define MC_CMD_SET_FUNC 0x4
2046 #define MC_CMD_SET_FUNC_IN_LEN 4
2048 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0
2049 #define MC_CMD_SET_FUNC_IN_FUNC_LEN 4
2052 #define MC_CMD_SET_FUNC_OUT_LEN 0
2059 #define MC_CMD_GET_BOOT_STATUS 0x5
2065 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
2070 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
2071 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
2073 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
2074 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
2075 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
2076 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 4
2077 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
2079 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 4
2082 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 4
2093 #define MC_CMD_GET_ASSERTS 0x6
2099 #define MC_CMD_GET_ASSERTS_IN_LEN 4
2101 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
2102 #define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4
2107 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
2108 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4
2110 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
2111 /* enum: A system-level assertion has failed. */
2112 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
2113 /* enum: A thread-level assertion has failed. */
2114 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
2116 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
2118 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
2120 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
2121 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4
2124 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
2129 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
2132 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4
2134 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
2141 #define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 0
2142 #define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 4
2144 /* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
2145 /* enum: A system-level assertion has failed. */
2146 /* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
2147 /* enum: A thread-level assertion has failed. */
2148 /* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
2150 /* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
2152 /* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
2154 #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 4
2155 #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 4
2158 #define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 4
2163 /* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
2166 #define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 4
2168 #define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 4
2171 #define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 4
2179 #define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 0
2180 #define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 4
2182 /* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
2183 /* enum: A system-level assertion has failed. */
2184 /* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
2185 /* enum: A thread-level assertion has failed. */
2186 /* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
2188 /* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
2190 /* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
2192 #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 4
2193 #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 4
2196 #define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 4
2201 /* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
2204 #define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 4
2206 #define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 4
2209 #define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 4
2211 /* MC firmware unique build ID (as binary SHA-1 value) */
2218 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LEN 4
2222 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LEN 4
2229 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LEN 4
2233 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LEN 4
2238 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
2239 /* MC firmware extra version info (as null-terminated US-ASCII string) */
2242 /* MC firmware build name (as null-terminated US-ASCII string) */
2252 #define MC_CMD_LOG_CTRL 0x7
2260 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
2261 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4
2263 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
2265 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
2267 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
2268 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4
2271 #define MC_CMD_LOG_CTRL_OUT_LEN 0
2278 #define MC_CMD_GET_VERSION 0x8
2284 #define MC_CMD_GET_VERSION_IN_LEN 0
2287 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4
2288 /* placeholder, set to 0 */
2289 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
2290 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4
2293 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4
2294 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
2295 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4
2297 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
2299 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
2301 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
2303 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002
2307 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2308 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2311 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
2312 #define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4
2319 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_LEN 4
2323 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_LEN 4
2329 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2330 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2333 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
2334 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4
2341 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LEN 4
2345 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LEN 4
2359 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2360 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2363 #define MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 4
2364 #define MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 4
2371 #define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LEN 4
2375 #define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LEN 4
2383 #define MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 4
2385 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2397 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2426 /* MC firmware unique build ID (as binary SHA-1 value) */
2431 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 4
2432 /* MC firmware build name (as null-terminated US-ASCII string) */
2435 /* The SUC firmware version as four numbers - a.b.c.d */
2437 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 4
2438 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 4
2439 /* SUC firmware build date (as 64-bit Unix timestamp) */
2443 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2447 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2451 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2454 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 4
2455 /* The CMC firmware version as four numbers - a.b.c.d */
2457 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 4
2458 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 4
2459 /* CMC firmware build date (as 64-bit Unix timestamp) */
2463 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2467 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2472 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2473 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2476 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 4
2478 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
2481 /* Board name / adapter model (as null-terminated US-ASCII string) */
2486 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 4
2487 /* Board serial number (as null-terminated US-ASCII string) */
2498 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2499 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2502 #define MC_CMD_GET_VERSION_V3_OUT_PCOL_OFST 4
2503 #define MC_CMD_GET_VERSION_V3_OUT_PCOL_LEN 4
2510 #define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LEN 4
2514 #define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LEN 4
2522 #define MC_CMD_GET_VERSION_V3_OUT_FLAGS_LEN 4
2524 #define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2536 #define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2565 /* MC firmware unique build ID (as binary SHA-1 value) */
2570 #define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_LEN 4
2571 /* MC firmware build name (as null-terminated US-ASCII string) */
2574 /* The SUC firmware version as four numbers - a.b.c.d */
2576 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_LEN 4
2577 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_NUM 4
2578 /* SUC firmware build date (as 64-bit Unix timestamp) */
2582 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2586 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2590 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2593 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_LEN 4
2594 /* The CMC firmware version as four numbers - a.b.c.d */
2596 #define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_LEN 4
2597 #define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_NUM 4
2598 /* CMC firmware build date (as 64-bit Unix timestamp) */
2602 #define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2606 #define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2611 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2612 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2615 #define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_LEN 4
2617 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
2620 /* Board name / adapter model (as null-terminated US-ASCII string) */
2625 #define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_LEN 4
2626 /* Board serial number (as null-terminated US-ASCII string) */
2629 /* The version of the datapath hardware design as three number - a.b.c */
2631 #define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_LEN 4
2634 * number - a.b.c
2637 #define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_LEN 4
2644 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2645 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2648 #define MC_CMD_GET_VERSION_V4_OUT_PCOL_OFST 4
2649 #define MC_CMD_GET_VERSION_V4_OUT_PCOL_LEN 4
2656 #define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LEN 4
2660 #define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LEN 4
2668 #define MC_CMD_GET_VERSION_V4_OUT_FLAGS_LEN 4
2670 #define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2682 #define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2711 /* MC firmware unique build ID (as binary SHA-1 value) */
2716 #define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_LEN 4
2717 /* MC firmware build name (as null-terminated US-ASCII string) */
2720 /* The SUC firmware version as four numbers - a.b.c.d */
2722 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_LEN 4
2723 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_NUM 4
2724 /* SUC firmware build date (as 64-bit Unix timestamp) */
2728 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2732 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2736 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2739 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_LEN 4
2740 /* The CMC firmware version as four numbers - a.b.c.d */
2742 #define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_LEN 4
2743 #define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_NUM 4
2744 /* CMC firmware build date (as 64-bit Unix timestamp) */
2748 #define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2752 #define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2757 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2758 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2761 #define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_LEN 4
2763 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
2766 /* Board name / adapter model (as null-terminated US-ASCII string) */
2771 #define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_LEN 4
2772 /* Board serial number (as null-terminated US-ASCII string) */
2775 /* The version of the datapath hardware design as three number - a.b.c */
2777 #define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_LEN 4
2780 * number - a.b.c
2783 #define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_LEN 4
2785 /* The SOC boot version as four numbers - a.b.c.d */
2787 #define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_LEN 4
2788 #define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_NUM 4
2789 /* The SOC uboot version as four numbers - a.b.c.d */
2791 #define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_LEN 4
2792 #define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_NUM 4
2793 /* The SOC main rootfs version as four numbers - a.b.c.d */
2795 #define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
2796 #define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
2797 /* The SOC recovery buildroot version as four numbers - a.b.c.d */
2799 #define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
2800 #define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
2806 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2807 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2810 #define MC_CMD_GET_VERSION_V5_OUT_PCOL_OFST 4
2811 #define MC_CMD_GET_VERSION_V5_OUT_PCOL_LEN 4
2818 #define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LEN 4
2822 #define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LEN 4
2830 #define MC_CMD_GET_VERSION_V5_OUT_FLAGS_LEN 4
2832 #define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2844 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2873 /* MC firmware unique build ID (as binary SHA-1 value) */
2878 #define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_LEN 4
2879 /* MC firmware build name (as null-terminated US-ASCII string) */
2882 /* The SUC firmware version as four numbers - a.b.c.d */
2884 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_LEN 4
2885 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_NUM 4
2886 /* SUC firmware build date (as 64-bit Unix timestamp) */
2890 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2894 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2898 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2901 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_LEN 4
2902 /* The CMC firmware version as four numbers - a.b.c.d */
2904 #define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_LEN 4
2905 #define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_NUM 4
2906 /* CMC firmware build date (as 64-bit Unix timestamp) */
2910 #define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2914 #define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2919 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2920 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2923 #define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_LEN 4
2925 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
2928 /* Board name / adapter model (as null-terminated US-ASCII string) */
2933 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_LEN 4
2934 /* Board serial number (as null-terminated US-ASCII string) */
2937 /* The version of the datapath hardware design as three number - a.b.c */
2939 #define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_LEN 4
2942 * number - a.b.c
2945 #define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_LEN 4
2947 /* The SOC boot version as four numbers - a.b.c.d */
2949 #define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_LEN 4
2950 #define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_NUM 4
2951 /* The SOC uboot version as four numbers - a.b.c.d */
2953 #define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_LEN 4
2954 #define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_NUM 4
2955 /* The SOC main rootfs version as four numbers - a.b.c.d */
2957 #define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
2958 #define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
2959 /* The SOC recovery buildroot version as four numbers - a.b.c.d */
2961 #define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
2962 #define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
2963 /* Board version as four numbers - a.b.c.d. BOARD_VERSION[0] duplicates the
2967 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_LEN 4
2968 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_NUM 4
2969 /* Bundle version as four numbers - a.b.c.d */
2971 #define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_LEN 4
2972 #define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_NUM 4
2979 #define MC_CMD_PTP 0xb
2987 #define MC_CMD_PTP_IN_OP_OFST 0
2990 #define MC_CMD_PTP_OP_ENABLE 0x1
2992 #define MC_CMD_PTP_OP_DISABLE 0x2
2997 #define MC_CMD_PTP_OP_TRANSMIT 0x3
2999 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4
3003 #define MC_CMD_PTP_OP_STATUS 0x5
3005 #define MC_CMD_PTP_OP_ADJUST 0x6
3007 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7
3009 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
3011 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
3013 #define MC_CMD_PTP_OP_RESET_STATS 0xa
3015 #define MC_CMD_PTP_OP_DEBUG 0xb
3017 #define MC_CMD_PTP_OP_FPGAREAD 0xc
3019 #define MC_CMD_PTP_OP_FPGAWRITE 0xd
3021 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
3023 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
3027 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
3031 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
3035 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
3039 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13
3041 #define MC_CMD_PTP_OP_RST_CLK 0x14
3043 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15
3045 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
3046 /* enum: Get the clock attributes. NOTE- extended version of
3049 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
3053 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
3057 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
3059 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
3063 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
3067 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
3069 #define MC_CMD_PTP_OP_MAX 0x1c
3073 #define MC_CMD_PTP_IN_CMD_OFST 0
3074 #define MC_CMD_PTP_IN_CMD_LEN 4
3075 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
3076 #define MC_CMD_PTP_IN_PERIPH_ID_LEN 4
3077 /* Not used, initialize to 0. Events are always sent to function relative queue
3078 * 0.
3081 #define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4
3084 #define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4
3086 #define MC_CMD_PTP_MODE_V1 0x0
3087 /* enum: PTP, version 1, with VLAN headers - deprecated */
3088 #define MC_CMD_PTP_MODE_V1_VLAN 0x1
3090 #define MC_CMD_PTP_MODE_V2 0x2
3091 /* enum: PTP, version 2, with VLAN headers - deprecated */
3092 #define MC_CMD_PTP_MODE_V2_VLAN 0x3
3094 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4
3096 #define MC_CMD_PTP_MODE_FCOE 0x5
3100 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3101 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3102 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3103 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3110 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1)
3111 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3112 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3113 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3114 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3117 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4
3127 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3128 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3129 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3130 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3134 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3135 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3136 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3137 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3141 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3142 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3143 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3144 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3148 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3149 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3150 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3151 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3156 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LEN 4
3160 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LEN 4
3164 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28
3169 #define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c
3172 #define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4
3175 #define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4
3178 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4
3181 #define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4
3185 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3186 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3187 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3188 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3193 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LEN 4
3197 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LEN 4
3201 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
3206 /* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */
3209 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4
3212 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4
3215 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4
3218 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4
3221 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4
3225 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3226 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3227 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3228 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3231 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4
3238 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LEN 4
3242 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LEN 4
3248 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3249 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3250 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3251 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3255 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3256 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3257 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3258 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3261 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4
3265 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3266 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3267 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3268 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3272 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3273 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3274 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3275 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3278 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4
3282 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3283 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3284 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3285 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3287 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4
3289 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4
3296 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1)
3297 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3298 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3299 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3300 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3302 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4
3311 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3312 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3313 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3314 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3317 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4
3320 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4
3323 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4
3326 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4
3330 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3331 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3332 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3333 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3336 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4
3339 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4
3342 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4
3345 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4
3348 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4
3352 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3353 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3354 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3355 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3360 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LEN 4
3364 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LEN 4
3372 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3373 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3374 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3375 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3376 /* Number of VLAN tags, 0 if not VLAN */
3378 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4
3381 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
3386 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3387 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3388 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3389 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3390 /* 1 to enable UUID filtering, 0 to disable */
3392 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4
3397 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LEN 4
3401 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LEN 4
3407 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3408 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3409 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3410 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3411 /* 1 to enable Domain filtering, 0 to disable */
3413 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4
3416 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4
3420 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3421 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3422 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3423 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3426 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4
3428 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
3430 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
3434 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3435 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3436 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3437 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3441 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3442 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3444 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
3445 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4
3447 #define MC_CMD_PTP_ENABLE_PPS 0x0
3449 #define MC_CMD_PTP_DISABLE_PPS 0x1
3450 /* Not used, initialize to 0. Events are always sent to function relative queue
3451 * 0.
3454 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4
3458 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3459 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3460 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3461 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3465 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3466 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3467 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3468 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3472 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3473 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3474 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3475 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3479 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3480 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3481 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3482 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3485 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4
3487 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
3495 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3496 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3497 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3498 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3501 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4
3503 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
3505 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
3508 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4
3512 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3513 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3514 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3515 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3516 /* 1 to enable PPS test mode, 0 to disable and return result. */
3518 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4
3522 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3523 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3524 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3525 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3526 /* NIC - Host System Clock Synchronization status */
3528 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4
3530 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
3532 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
3537 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4
3539 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4
3541 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4
3544 #define MC_CMD_PTP_OUT_LEN 0
3549 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
3550 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4
3552 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
3553 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4
3555 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
3556 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4
3558 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
3559 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4
3562 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
3565 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
3570 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
3571 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4
3573 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
3574 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4
3576 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
3577 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4
3579 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
3580 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4
3585 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0
3586 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4
3588 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0
3589 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4
3591 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4
3592 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4
3594 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4
3595 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4
3598 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4
3603 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
3604 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4
3606 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
3607 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4
3610 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4
3613 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4
3616 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4
3619 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4
3622 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4
3625 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4
3628 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4
3631 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4
3634 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4
3637 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4
3640 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4
3643 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4
3646 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4
3649 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4
3655 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
3656 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)
3658 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
3664 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
3665 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4
3667 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
3668 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4
3670 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
3671 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4
3674 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4
3677 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4
3680 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4
3683 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4
3688 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
3689 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4
3691 #define MC_CMD_PTP_MANF_SUCCESS 0x0
3693 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1
3695 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2
3697 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
3699 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4
3701 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5
3703 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6
3705 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7
3707 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
3709 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
3711 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
3713 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb
3715 #define MC_CMD_PTP_MANF_PPS_NS 0xc
3717 #define MC_CMD_PTP_MANF_REGISTERS 0xd
3719 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe
3721 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
3722 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4
3727 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
3728 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4
3730 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
3731 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4
3734 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4
3740 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
3741 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)
3742 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
3749 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
3753 * be assumed. Note this enum is deprecated. Do not add to it- use the
3756 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
3757 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4
3759 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
3761 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
3762 /* enum: Major register has units of seconds, minor 2^-27s per tick */
3763 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
3772 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
3773 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4
3775 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
3777 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
3778 /* enum: Major register has units of seconds, minor 2^-27s per tick */
3779 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
3782 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3
3790 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
3791 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4
3794 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4
3796 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
3808 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4
3810 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4
3812 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4
3821 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_OFST 0
3822 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_LEN 4
3824 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_NANOSECONDS 0x0
3826 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_16SECONDS_8NANOSECONDS 0x1
3827 /* enum: Major register has units of seconds, minor 2^-27s per tick */
3828 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_27FRACTION 0x2
3831 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_QTR_NANOSECONDS 0x3
3839 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_OFST 4
3840 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_LEN 4
3843 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_CAPABILITIES_LEN 4
3845 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_LBN 0
3857 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED0_LEN 4
3859 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED1_LEN 4
3861 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED2_LEN 4
3865 * response is not supported a value of -0.1 ns should be assumed, which is
3866 * equivalent to a -10% adjustment.
3871 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_LEN 4
3875 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_LEN 4
3887 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_LEN 4
3891 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_LEN 4
3898 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
3899 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4
3901 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
3902 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4
3905 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4
3908 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4
3913 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0
3914 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4
3916 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4
3917 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4
3920 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4
3923 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4
3924 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */
3926 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4
3927 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */
3929 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4
3932 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
3934 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
3935 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4
3940 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0
3947 #define MC_CMD_CSR_READ32 0xc
3955 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0
3956 #define MC_CMD_CSR_READ32_IN_ADDR_LEN 4
3957 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4
3958 #define MC_CMD_CSR_READ32_IN_STEP_LEN 4
3960 #define MC_CMD_CSR_READ32_IN_NUMWORDS_LEN 4
3963 #define MC_CMD_CSR_READ32_OUT_LENMIN 4
3966 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
3967 #define MC_CMD_CSR_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
3969 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
3970 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
3980 #define MC_CMD_CSR_WRITE32 0xd
3989 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
3990 #define MC_CMD_CSR_WRITE32_IN_BUFFER_NUM(len) (((len)-8)/4)
3992 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
3993 #define MC_CMD_CSR_WRITE32_IN_ADDR_LEN 4
3994 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
3995 #define MC_CMD_CSR_WRITE32_IN_STEP_LEN 4
3997 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
4003 #define MC_CMD_CSR_WRITE32_OUT_LEN 4
4004 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
4005 #define MC_CMD_CSR_WRITE32_OUT_STATUS_LEN 4
4013 #define MC_CMD_HP 0x54
4020 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
4022 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
4026 #define MC_CMD_HP_IN_SUBCMD_OFST 0
4027 #define MC_CMD_HP_IN_SUBCMD_LEN 4
4028 /* enum: OCSD (Option Card Sensor Data) sub-command. */
4029 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0
4030 /* enum: Last known valid HP sub-command. */
4031 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0
4032 /* The address to the array of sensor fields. (Or NULL to use a sub-command.)
4034 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4
4036 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
4037 #define MC_CMD_HP_IN_OCSD_ADDR_LO_LEN 4
4041 #define MC_CMD_HP_IN_OCSD_ADDR_HI_LEN 4
4044 /* The requested update interval, in seconds. (Or the sub-command if ADDR is
4048 #define MC_CMD_HP_IN_OCSD_INTERVAL_LEN 4
4051 #define MC_CMD_HP_OUT_LEN 4
4052 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
4053 #define MC_CMD_HP_OUT_OCSD_STATUS_LEN 4
4055 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1
4057 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2
4059 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3
4066 #define MC_CMD_STACKINFO 0xf
4072 #define MC_CMD_STACKINFO_IN_LEN 0
4078 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
4079 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_NUM(len) (((len)-0)/12)
4081 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
4092 #define MC_CMD_MDIO_READ 0x10
4102 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0
4103 #define MC_CMD_MDIO_READ_IN_BUS_LEN 4
4105 #define MC_CMD_MDIO_BUS_INTERNAL 0x0
4107 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1
4109 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
4110 #define MC_CMD_MDIO_READ_IN_PRTAD_LEN 4
4113 #define MC_CMD_MDIO_READ_IN_DEVAD_LEN 4
4117 #define MC_CMD_MDIO_CLAUSE22 0x20
4120 #define MC_CMD_MDIO_READ_IN_ADDR_LEN 4
4125 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
4126 #define MC_CMD_MDIO_READ_OUT_VALUE_LEN 4
4130 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
4131 #define MC_CMD_MDIO_READ_OUT_STATUS_LEN 4
4133 #define MC_CMD_MDIO_STATUS_GOOD 0x8
4140 #define MC_CMD_MDIO_WRITE 0x11
4150 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
4151 #define MC_CMD_MDIO_WRITE_IN_BUS_LEN 4
4153 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */
4155 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
4157 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
4158 #define MC_CMD_MDIO_WRITE_IN_PRTAD_LEN 4
4161 #define MC_CMD_MDIO_WRITE_IN_DEVAD_LEN 4
4165 /* MC_CMD_MDIO_CLAUSE22 0x20 */
4168 #define MC_CMD_MDIO_WRITE_IN_ADDR_LEN 4
4171 #define MC_CMD_MDIO_WRITE_IN_VALUE_LEN 4
4174 #define MC_CMD_MDIO_WRITE_OUT_LEN 4
4178 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
4179 #define MC_CMD_MDIO_WRITE_OUT_STATUS_LEN 4
4181 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */
4188 #define MC_CMD_DBI_WRITE 0x12
4197 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
4198 #define MC_CMD_DBI_WRITE_IN_DBIWROP_NUM(len) (((len)-0)/12)
4199 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
4202 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
4209 #define MC_CMD_DBI_WRITE_OUT_LEN 0
4213 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
4214 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LEN 4
4215 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
4217 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
4218 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LEN 4
4219 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_OFST 4
4222 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_OFST 4
4225 #define MC_CMD_DBIWROP_TYPEDEF_CS2_OFST 4
4231 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LEN 4
4238 * Read a 32-bit register from the indirect port register map. The port to
4241 #define MC_CMD_PORT_READ32 0x14
4244 #define MC_CMD_PORT_READ32_IN_LEN 4
4246 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0
4247 #define MC_CMD_PORT_READ32_IN_ADDR_LEN 4
4252 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
4253 #define MC_CMD_PORT_READ32_OUT_VALUE_LEN 4
4255 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
4256 #define MC_CMD_PORT_READ32_OUT_STATUS_LEN 4
4261 * Write a 32-bit register to the indirect port register map. The port to
4264 #define MC_CMD_PORT_WRITE32 0x15
4269 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
4270 #define MC_CMD_PORT_WRITE32_IN_ADDR_LEN 4
4272 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
4273 #define MC_CMD_PORT_WRITE32_IN_VALUE_LEN 4
4276 #define MC_CMD_PORT_WRITE32_OUT_LEN 4
4278 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
4279 #define MC_CMD_PORT_WRITE32_OUT_STATUS_LEN 4
4284 * Read a 128-bit register from the indirect port register map. The port to
4287 #define MC_CMD_PORT_READ128 0x16
4290 #define MC_CMD_PORT_READ128_IN_LEN 4
4292 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0
4293 #define MC_CMD_PORT_READ128_IN_ADDR_LEN 4
4298 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
4302 #define MC_CMD_PORT_READ128_OUT_STATUS_LEN 4
4307 * Write a 128-bit register to the indirect port register map. The port to
4310 #define MC_CMD_PORT_WRITE128 0x17
4315 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
4316 #define MC_CMD_PORT_WRITE128_IN_ADDR_LEN 4
4318 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
4322 #define MC_CMD_PORT_WRITE128_OUT_LEN 4
4324 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
4325 #define MC_CMD_PORT_WRITE128_OUT_STATUS_LEN 4
4328 #define MC_CMD_CAPABILITIES_LEN 4
4330 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0
4342 #define MC_CMD_CAPABILITIES_AOE_LBN 4
4358 #define MC_CMD_GET_BOARD_CFG 0x18
4364 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0
4371 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2)
4372 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
4373 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
4374 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
4380 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
4385 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
4400 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
4405 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
4410 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
4415 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
4416 /* Siena only. This field contains a 16-bit value for each of the types of
4431 * Read DBI register(s) -- extended functionality
4433 #define MC_CMD_DBI_READX 0x19
4442 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
4443 #define MC_CMD_DBI_READX_IN_DBIRDOP_NUM(len) (((len)-0)/8)
4444 /* Each Read op consists of an address (offset 0), VF/CS2) */
4445 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
4447 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
4448 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LEN 4
4449 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_LBN 0
4451 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
4452 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_LEN 4
4460 #define MC_CMD_DBI_READX_OUT_LENMIN 4
4463 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
4464 #define MC_CMD_DBI_READX_OUT_VALUE_NUM(len) (((len)-0)/4)
4466 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0
4467 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4
4474 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0
4475 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LEN 4
4476 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0
4478 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
4479 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LEN 4
4480 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_OFST 4
4483 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_OFST 4
4486 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_OFST 4
4495 * Set the 16byte seed for the MC pseudo-random generator.
4497 #define MC_CMD_SET_RAND_SEED 0x1a
4505 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
4509 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0
4516 #define MC_CMD_LTSSM_HIST 0x1b
4519 #define MC_CMD_LTSSM_HIST_IN_LEN 0
4522 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0
4525 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
4526 #define MC_CMD_LTSSM_HIST_OUT_DATA_NUM(len) (((len)-0)/4)
4527 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */
4528 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
4529 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
4530 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
4544 #define MC_CMD_DRV_ATTACH 0x1c
4552 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
4553 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
4554 #define MC_CMD_DRV_ATTACH_OFST 0
4555 #define MC_CMD_DRV_ATTACH_LBN 0
4557 #define MC_CMD_DRV_ATTACH_IN_ATTACH_OFST 0
4558 #define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
4560 #define MC_CMD_DRV_PREBOOT_OFST 0
4563 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 0
4566 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 0
4569 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 0
4572 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 0
4573 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 4
4575 #define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
4578 #define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 0
4581 /* 1 to set new state, or 0 to just report the existing state */
4582 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
4583 #define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
4586 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4
4588 #define MC_CMD_FW_FULL_FEATURED 0x0
4590 #define MC_CMD_FW_LOW_LATENCY 0x1
4592 #define MC_CMD_FW_PACKED_STREAM 0x2
4596 #define MC_CMD_FW_HIGH_TX_RATE 0x3
4598 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
4602 #define MC_CMD_FW_RULES_ENGINE 0x5
4604 #define MC_CMD_FW_DPDK 0x6
4605 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
4608 #define MC_CMD_FW_L3XUDP 0x7
4612 * (i.e. non-production) builds.
4614 #define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe
4615 /* enum: Only this option is allowed for non-admin functions */
4616 #define MC_CMD_FW_DONT_CARE 0xffffffff
4623 #define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 0
4624 #define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 4
4625 /* MC_CMD_DRV_ATTACH_OFST 0 */
4626 /* MC_CMD_DRV_ATTACH_LBN 0 */
4628 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 0
4629 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 0
4631 /* MC_CMD_DRV_PREBOOT_OFST 0 */
4634 #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 0
4637 #define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 0
4640 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 0
4643 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 0
4644 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 4
4646 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
4649 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 0
4652 /* 1 to set new state, or 0 to just report the existing state */
4653 #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 4
4654 #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 4
4657 #define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 4
4659 /* MC_CMD_FW_FULL_FEATURED 0x0 */
4661 /* MC_CMD_FW_LOW_LATENCY 0x1 */
4663 /* MC_CMD_FW_PACKED_STREAM 0x2 */
4667 /* MC_CMD_FW_HIGH_TX_RATE 0x3 */
4669 /* MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 */
4673 /* MC_CMD_FW_RULES_ENGINE 0x5 */
4675 /* MC_CMD_FW_DPDK 0x6 */
4676 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
4679 /* MC_CMD_FW_L3XUDP 0x7 */
4683 * (i.e. non-production) builds.
4685 /* MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe */
4686 /* enum: Only this option is allowed for non-admin functions */
4687 /* MC_CMD_FW_DONT_CARE 0xffffffff */
4688 /* Version of the driver to be reported by management protocols (e.g. NC-SI)
4689 * handled by the NIC. This is a zero-terminated ASCII string.
4695 #define MC_CMD_DRV_ATTACH_OUT_LEN 4
4697 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
4698 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4
4703 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
4704 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4
4706 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
4707 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4
4708 /* enum: Labels the lowest-numbered function visible to the OS */
4709 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
4713 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
4715 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
4719 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
4724 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
4726 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x5
4727 /* enum: If set, indicates that TX only spreading is enabled. Even-numbered
4728 * TXQs will use one engine, and odd-numbered TXQs will use the other. This
4729 * also has the effect that only even-numbered RXQs will receive traffic.
4731 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x5
4738 #define MC_CMD_SHMUART 0x1f
4741 #define MC_CMD_SHMUART_IN_LEN 4
4743 #define MC_CMD_SHMUART_IN_FLAG_OFST 0
4744 #define MC_CMD_SHMUART_IN_FLAG_LEN 4
4747 #define MC_CMD_SHMUART_OUT_LEN 0
4752 * Generic per-port reset. There is no equivalent for per-board reset. Locks
4753 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
4756 #define MC_CMD_PORT_RESET 0x20
4762 #define MC_CMD_PORT_RESET_IN_LEN 0
4765 #define MC_CMD_PORT_RESET_OUT_LEN 0
4770 * Generic per-resource reset. There is no equivalent for per-board reset.
4771 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
4774 #define MC_CMD_ENTITY_RESET 0x20
4778 #define MC_CMD_ENTITY_RESET_IN_LEN 4
4782 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
4783 #define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4
4784 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_OFST 0
4785 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
4789 #define MC_CMD_ENTITY_RESET_OUT_LEN 0
4796 #define MC_CMD_PCIE_CREDITS 0x21
4800 /* poll period. 0 is disabled */
4801 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
4802 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_LEN 4
4804 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
4805 #define MC_CMD_PCIE_CREDITS_IN_WIPE_LEN 4
4809 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
4813 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
4831 #define MC_CMD_RXD_MONITOR 0x22
4835 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0
4836 #define MC_CMD_RXD_MONITOR_IN_QID_LEN 4
4837 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
4838 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_LEN 4
4840 #define MC_CMD_RXD_MONITOR_IN_WIPE_LEN 4
4844 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
4845 #define MC_CMD_RXD_MONITOR_OUT_QID_LEN 4
4846 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
4847 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_LEN 4
4849 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_LEN 4
4851 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_LEN 4
4853 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_LEN 4
4855 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_LEN 4
4857 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_LEN 4
4859 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_LEN 4
4861 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_LEN 4
4863 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_LEN 4
4865 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_LEN 4
4867 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_LEN 4
4869 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_LEN 4
4871 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_LEN 4
4873 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_LEN 4
4875 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_LEN 4
4877 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_LEN 4
4879 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_LEN 4
4881 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_LEN 4
4883 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_LEN 4
4890 #define MC_CMD_PUTS 0x23
4900 #define MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)
4901 #define MC_CMD_PUTS_IN_DEST_OFST 0
4902 #define MC_CMD_PUTS_IN_DEST_LEN 4
4903 #define MC_CMD_PUTS_IN_UART_OFST 0
4904 #define MC_CMD_PUTS_IN_UART_LBN 0
4906 #define MC_CMD_PUTS_IN_PORT_OFST 0
4909 #define MC_CMD_PUTS_IN_DHOST_OFST 4
4918 #define MC_CMD_PUTS_OUT_LEN 0
4926 #define MC_CMD_GET_PHY_CFG 0x24
4932 #define MC_CMD_GET_PHY_CFG_IN_LEN 0
4937 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
4938 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4
4939 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_OFST 0
4940 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
4942 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_OFST 0
4945 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_OFST 0
4948 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_OFST 0
4951 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_OFST 0
4952 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
4954 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_OFST 0
4957 #define MC_CMD_GET_PHY_CFG_OUT_BIST_OFST 0
4961 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
4962 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4
4965 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4
4976 #define MC_CMD_PHY_CAP_100FDX_LBN 4
5031 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4
5034 #define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4
5037 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4
5043 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4
5045 #define MC_CMD_MEDIA_XAUI 0x1
5047 #define MC_CMD_MEDIA_CX4 0x2
5049 #define MC_CMD_MEDIA_KX4 0x3
5051 #define MC_CMD_MEDIA_XFP 0x4
5053 #define MC_CMD_MEDIA_SFP_PLUS 0x5
5055 #define MC_CMD_MEDIA_BASE_T 0x6
5057 #define MC_CMD_MEDIA_QSFP_PLUS 0x7
5059 #define MC_CMD_MEDIA_DSFP 0x8
5061 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4
5063 #define MC_CMD_MMD_CLAUSE22 0x0
5064 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
5065 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
5066 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
5067 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
5068 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
5069 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
5070 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
5072 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
5073 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
5074 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
5082 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
5084 #define MC_CMD_START_BIST 0x25
5090 #define MC_CMD_START_BIST_IN_LEN 4
5092 #define MC_CMD_START_BIST_IN_TYPE_OFST 0
5093 #define MC_CMD_START_BIST_IN_TYPE_LEN 4
5095 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1
5097 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2
5099 #define MC_CMD_BPX_SERDES_BIST 0x3
5101 #define MC_CMD_MC_LOOPBACK_BIST 0x4
5103 #define MC_CMD_PHY_BIST 0x5
5105 #define MC_CMD_MC_MEM_BIST 0x6
5107 #define MC_CMD_PORT_MEM_BIST 0x7
5109 #define MC_CMD_REG_BIST 0x8
5112 #define MC_CMD_START_BIST_OUT_LEN 0
5121 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
5124 #define MC_CMD_POLL_BIST 0x26
5130 #define MC_CMD_POLL_BIST_IN_LEN 0
5135 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
5136 #define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4
5138 #define MC_CMD_POLL_BIST_RUNNING 0x1
5140 #define MC_CMD_POLL_BIST_PASSED 0x2
5142 #define MC_CMD_POLL_BIST_FAILED 0x3
5143 /* enum: Timed-out. */
5144 #define MC_CMD_POLL_BIST_TIMEOUT 0x4
5145 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
5146 #define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4
5151 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
5152 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
5155 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
5156 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4
5158 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4
5160 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4
5162 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4
5165 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4
5167 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
5169 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
5170 /* enum: Intra-pair short. */
5171 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
5172 /* enum: Inter-pair short. */
5173 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
5175 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
5178 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4
5183 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4
5188 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4
5195 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
5196 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
5199 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
5200 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4
5202 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
5204 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
5206 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
5208 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
5210 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
5212 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
5214 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
5216 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
5218 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
5223 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
5224 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
5227 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
5228 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4
5230 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
5231 /* enum: RAM test - walk ones. */
5232 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
5233 /* enum: RAM test - walk zeros. */
5234 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
5235 /* enum: RAM test - walking inversions zeros/ones. */
5236 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
5237 /* enum: RAM test - walking inversions checkerboard. */
5238 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
5239 /* enum: Register test - set / clear individual bits. */
5240 #define MC_CMD_POLL_BIST_MEM_REG 0x5
5242 #define MC_CMD_POLL_BIST_MEM_ECC 0x6
5245 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4
5248 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4
5250 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
5252 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
5254 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
5256 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
5258 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
5260 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
5262 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
5264 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7
5266 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8
5269 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4
5272 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4
5275 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4
5278 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4
5281 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4
5293 #define MC_CMD_FLUSH_RX_QUEUES 0x27
5296 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
5299 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
5300 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_NUM(len) (((len)-0)/4)
5301 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
5302 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
5308 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
5315 #define MC_CMD_GET_LOOPBACK_MODES 0x28
5321 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
5326 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
5328 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
5329 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LEN 4
5330 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LBN 0
5332 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
5333 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LEN 4
5337 #define MC_CMD_LOOPBACK_NONE 0x0
5339 #define MC_CMD_LOOPBACK_DATA 0x1
5341 #define MC_CMD_LOOPBACK_GMAC 0x2
5343 #define MC_CMD_LOOPBACK_XGMII 0x3
5345 #define MC_CMD_LOOPBACK_XGXS 0x4
5347 #define MC_CMD_LOOPBACK_XAUI 0x5
5349 #define MC_CMD_LOOPBACK_GMII 0x6
5351 #define MC_CMD_LOOPBACK_SGMII 0x7
5353 #define MC_CMD_LOOPBACK_XGBR 0x8
5355 #define MC_CMD_LOOPBACK_XFI 0x9
5357 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa
5359 #define MC_CMD_LOOPBACK_GMII_FAR 0xb
5361 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc
5363 #define MC_CMD_LOOPBACK_XFI_FAR 0xd
5365 #define MC_CMD_LOOPBACK_GPHY 0xe
5367 #define MC_CMD_LOOPBACK_PHYXS 0xf
5369 #define MC_CMD_LOOPBACK_PCS 0x10
5370 /* enum: PMA-PMD. */
5371 #define MC_CMD_LOOPBACK_PMAPMD 0x11
5372 /* enum: Cross-Port. */
5373 #define MC_CMD_LOOPBACK_XPORT 0x12
5374 /* enum: XGMII-Wireside. */
5375 #define MC_CMD_LOOPBACK_XGMII_WS 0x13
5377 #define MC_CMD_LOOPBACK_XAUI_WS 0x14
5379 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
5381 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
5383 #define MC_CMD_LOOPBACK_GMII_WS 0x17
5385 #define MC_CMD_LOOPBACK_XFI_WS 0x18
5387 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
5389 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
5390 /* enum: PMA lanes MAC-Serdes. */
5391 #define MC_CMD_LOOPBACK_PMA_INT 0x1b
5393 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c
5395 #define MC_CMD_LOOPBACK_SD_FAR 0x1d
5396 /* enum: PMA lanes MAC-Serdes Wireside. */
5397 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
5399 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
5401 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
5403 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
5405 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22
5407 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
5409 #define MC_CMD_LOOPBACK_DATA_WS 0x24
5413 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
5418 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LEN 4
5422 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LEN 4
5431 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LEN 4
5435 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LEN 4
5444 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LEN 4
5448 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LEN 4
5457 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LEN 4
5461 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LEN 4
5472 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
5474 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
5475 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LEN 4
5476 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LBN 0
5478 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
5479 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LEN 4
5483 /* MC_CMD_LOOPBACK_NONE 0x0 */
5485 /* MC_CMD_LOOPBACK_DATA 0x1 */
5487 /* MC_CMD_LOOPBACK_GMAC 0x2 */
5489 /* MC_CMD_LOOPBACK_XGMII 0x3 */
5491 /* MC_CMD_LOOPBACK_XGXS 0x4 */
5493 /* MC_CMD_LOOPBACK_XAUI 0x5 */
5495 /* MC_CMD_LOOPBACK_GMII 0x6 */
5497 /* MC_CMD_LOOPBACK_SGMII 0x7 */
5499 /* MC_CMD_LOOPBACK_XGBR 0x8 */
5501 /* MC_CMD_LOOPBACK_XFI 0x9 */
5503 /* MC_CMD_LOOPBACK_XAUI_FAR 0xa */
5505 /* MC_CMD_LOOPBACK_GMII_FAR 0xb */
5507 /* MC_CMD_LOOPBACK_SGMII_FAR 0xc */
5509 /* MC_CMD_LOOPBACK_XFI_FAR 0xd */
5511 /* MC_CMD_LOOPBACK_GPHY 0xe */
5513 /* MC_CMD_LOOPBACK_PHYXS 0xf */
5515 /* MC_CMD_LOOPBACK_PCS 0x10 */
5516 /* enum: PMA-PMD. */
5517 /* MC_CMD_LOOPBACK_PMAPMD 0x11 */
5518 /* enum: Cross-Port. */
5519 /* MC_CMD_LOOPBACK_XPORT 0x12 */
5520 /* enum: XGMII-Wireside. */
5521 /* MC_CMD_LOOPBACK_XGMII_WS 0x13 */
5523 /* MC_CMD_LOOPBACK_XAUI_WS 0x14 */
5525 /* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
5527 /* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
5529 /* MC_CMD_LOOPBACK_GMII_WS 0x17 */
5531 /* MC_CMD_LOOPBACK_XFI_WS 0x18 */
5533 /* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
5535 /* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
5536 /* enum: PMA lanes MAC-Serdes. */
5537 /* MC_CMD_LOOPBACK_PMA_INT 0x1b */
5539 /* MC_CMD_LOOPBACK_SD_NEAR 0x1c */
5541 /* MC_CMD_LOOPBACK_SD_FAR 0x1d */
5542 /* enum: PMA lanes MAC-Serdes Wireside. */
5543 /* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
5545 /* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
5547 /* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
5549 /* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
5551 /* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
5553 /* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
5555 /* MC_CMD_LOOPBACK_DATA_WS 0x24 */
5559 /* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
5564 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LEN 4
5568 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LEN 4
5577 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LEN 4
5581 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LEN 4
5590 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LEN 4
5594 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LEN 4
5603 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LEN 4
5607 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LEN 4
5616 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LEN 4
5620 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LEN 4
5629 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LEN 4
5633 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LEN 4
5642 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LEN 4
5646 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LEN 4
5652 /* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */
5653 #define AN_TYPE_LEN 4
5654 #define AN_TYPE_TYPE_OFST 0
5655 #define AN_TYPE_TYPE_LEN 4
5657 #define MC_CMD_AN_NONE 0x0
5658 /* enum: Clause 28 - BASE-T */
5659 #define MC_CMD_AN_CLAUSE28 0x1
5660 /* enum: Clause 37 - BASE-X */
5661 #define MC_CMD_AN_CLAUSE37 0x2
5662 /* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable
5663 * assemblies. Includes Clause 72/Clause 92 link-training.
5665 #define MC_CMD_AN_CLAUSE73 0x3
5666 #define AN_TYPE_TYPE_LBN 0
5671 #define FEC_TYPE_LEN 4
5672 #define FEC_TYPE_TYPE_OFST 0
5673 #define FEC_TYPE_TYPE_LEN 4
5675 #define MC_CMD_FEC_NONE 0x0
5676 /* enum: Clause 74 BASE-R FEC (a.k.a Firecode) */
5677 #define MC_CMD_FEC_BASER 0x1
5678 /* enum: Clause 91/Clause 108 Reed-Solomon FEC */
5679 #define MC_CMD_FEC_RS 0x2
5680 #define FEC_TYPE_TYPE_LBN 0
5686 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
5689 #define MC_CMD_GET_LINK 0x29
5695 #define MC_CMD_GET_LINK_IN_LEN 0
5699 /* Near-side advertised capabilities. Refer to
5702 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0
5703 #define MC_CMD_GET_LINK_OUT_CAP_LEN 4
5704 /* Link-partner advertised capabilities. Refer to
5707 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
5708 #define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4
5710 * reads non-zero.
5713 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4
5716 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4
5720 #define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4
5722 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
5747 #define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
5751 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4
5753 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
5767 /* Near-side advertised capabilities. Refer to
5770 #define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0
5771 #define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4
5772 /* Link-partner advertised capabilities. Refer to
5775 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4
5776 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4
5778 * reads non-zero.
5781 #define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4
5784 #define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4
5788 #define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4
5790 #define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0
5815 #define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
5819 #define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4
5821 /* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */
5833 * e.g. plugged-in module). In general, subset of
5835 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal
5836 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to
5840 #define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4
5841 /* Auto-negotiation type used on the link */
5843 #define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4
5848 #define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4
5852 #define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4
5854 #define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0
5866 #define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4
5888 * code: 0, EINVAL, ETIME, EAGAIN
5890 #define MC_CMD_SET_LINK 0x2a
5897 /* Near-side advertised capabilities. Refer to
5900 #define MC_CMD_SET_LINK_IN_CAP_OFST 0
5901 #define MC_CMD_SET_LINK_IN_CAP_LEN 4
5903 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
5904 #define MC_CMD_SET_LINK_IN_FLAGS_LEN 4
5905 #define MC_CMD_SET_LINK_IN_LOWPOWER_OFST 4
5906 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
5908 #define MC_CMD_SET_LINK_IN_POWEROFF_OFST 4
5911 #define MC_CMD_SET_LINK_IN_TXDIS_OFST 4
5914 #define MC_CMD_SET_LINK_IN_LINKDOWN_OFST 4
5919 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4
5922 /* A loopback speed of "0" is supported, and means (choose any available
5926 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4
5933 /* Near-side advertised capabilities. Refer to
5936 #define MC_CMD_SET_LINK_IN_V2_CAP_OFST 0
5937 #define MC_CMD_SET_LINK_IN_V2_CAP_LEN 4
5939 #define MC_CMD_SET_LINK_IN_V2_FLAGS_OFST 4
5940 #define MC_CMD_SET_LINK_IN_V2_FLAGS_LEN 4
5941 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 4
5942 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_LBN 0
5944 #define MC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 4
5947 #define MC_CMD_SET_LINK_IN_V2_TXDIS_OFST 4
5950 #define MC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 4
5955 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 4
5958 /* A loopback speed of "0" is supported, and means (choose any available
5962 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 4
5966 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_LBN 0
5973 #define MC_CMD_SET_LINK_OUT_LEN 0
5978 * Set identification LED state. Locks required: None. Return code: 0, EINVAL
5980 #define MC_CMD_SET_ID_LED 0x2b
5986 #define MC_CMD_SET_ID_LED_IN_LEN 4
5988 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
5989 #define MC_CMD_SET_ID_LED_IN_STATE_LEN 4
5990 #define MC_CMD_LED_OFF 0x0 /* enum */
5991 #define MC_CMD_LED_ON 0x1 /* enum */
5992 #define MC_CMD_LED_DEFAULT 0x2 /* enum */
5995 #define MC_CMD_SET_ID_LED_OUT_LEN 0
6000 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
6002 #define MC_CMD_SET_MAC 0x2c
6012 #define MC_CMD_SET_MAC_IN_MTU_OFST 0
6013 #define MC_CMD_SET_MAC_IN_MTU_LEN 4
6014 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
6015 #define MC_CMD_SET_MAC_IN_DRAIN_LEN 4
6019 #define MC_CMD_SET_MAC_IN_ADDR_LO_LEN 4
6023 #define MC_CMD_SET_MAC_IN_ADDR_HI_LEN 4
6027 #define MC_CMD_SET_MAC_IN_REJECT_LEN 4
6029 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
6035 #define MC_CMD_SET_MAC_IN_FCNTL_LEN 4
6037 #define MC_CMD_FCNTL_OFF 0x0
6039 #define MC_CMD_FCNTL_RESPOND 0x1
6041 #define MC_CMD_FCNTL_BIDIR 0x2
6043 #define MC_CMD_FCNTL_AUTO 0x3
6045 #define MC_CMD_FCNTL_QBB 0x4
6047 #define MC_CMD_FCNTL_GENERATE 0x5
6049 #define MC_CMD_SET_MAC_IN_FLAGS_LEN 4
6051 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
6059 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
6060 #define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4
6061 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
6062 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4
6066 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LEN 4
6070 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LEN 4
6074 #define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
6076 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
6082 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4
6084 /* MC_CMD_FCNTL_OFF 0x0 */
6086 /* MC_CMD_FCNTL_RESPOND 0x1 */
6088 /* MC_CMD_FCNTL_BIDIR 0x2 */
6090 /* MC_CMD_FCNTL_AUTO 0x3 */
6092 /* MC_CMD_FCNTL_QBB 0x4 */
6094 /* MC_CMD_FCNTL_GENERATE 0x5 */
6096 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4
6098 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
6106 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4
6108 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
6120 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
6128 #define MC_CMD_SET_MAC_V3_IN_MTU_OFST 0
6129 #define MC_CMD_SET_MAC_V3_IN_MTU_LEN 4
6130 #define MC_CMD_SET_MAC_V3_IN_DRAIN_OFST 4
6131 #define MC_CMD_SET_MAC_V3_IN_DRAIN_LEN 4
6135 #define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LEN 4
6139 #define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LEN 4
6143 #define MC_CMD_SET_MAC_V3_IN_REJECT_LEN 4
6145 #define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_LBN 0
6151 #define MC_CMD_SET_MAC_V3_IN_FCNTL_LEN 4
6153 /* MC_CMD_FCNTL_OFF 0x0 */
6155 /* MC_CMD_FCNTL_RESPOND 0x1 */
6157 /* MC_CMD_FCNTL_BIDIR 0x2 */
6159 /* MC_CMD_FCNTL_AUTO 0x3 */
6161 /* MC_CMD_FCNTL_QBB 0x4 */
6163 /* MC_CMD_FCNTL_GENERATE 0x5 */
6165 #define MC_CMD_SET_MAC_V3_IN_FLAGS_LEN 4
6167 #define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_LBN 0
6175 #define MC_CMD_SET_MAC_V3_IN_CONTROL_LEN 4
6177 #define MC_CMD_SET_MAC_V3_IN_CFG_MTU_LBN 0
6189 #define MC_CMD_SET_MAC_V3_IN_CFG_FCS_LBN 4
6201 * and 4. Some could be implementation-specific and fail with ENOTSUP if not
6202 * available (no examples exist right now). See SF-123581-TC section 4.3 for
6208 #define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LEN 4
6212 #define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LEN 4
6216 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_LEN 4
6218 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
6224 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
6226 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
6228 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
6234 #define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_LEN 4
6238 #define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LEN 4
6242 #define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LEN 4
6247 #define MC_CMD_SET_MAC_OUT_LEN 0
6250 #define MC_CMD_SET_MAC_V2_OUT_LEN 4
6253 * to 0.
6255 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
6256 #define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4
6263 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
6264 * statistics may be read from the message response. If DMA_ADDR != 0, then the
6265 * statistics are dmad to that (page-aligned location). Locks required: None.
6266 * Returns: 0, ETIME
6268 #define MC_CMD_PHY_STATS 0x2d
6276 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
6278 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
6279 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LEN 4
6280 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LBN 0
6282 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
6283 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LEN 4
6288 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
6292 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
6293 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
6296 #define MC_CMD_OUI 0x0
6297 /* enum: PMA-PMD Link Up. */
6298 #define MC_CMD_PMA_PMD_LINK_UP 0x1
6299 /* enum: PMA-PMD RX Fault. */
6300 #define MC_CMD_PMA_PMD_RX_FAULT 0x2
6301 /* enum: PMA-PMD TX Fault. */
6302 #define MC_CMD_PMA_PMD_TX_FAULT 0x3
6303 /* enum: PMA-PMD Signal */
6304 #define MC_CMD_PMA_PMD_SIGNAL 0x4
6305 /* enum: PMA-PMD SNR A. */
6306 #define MC_CMD_PMA_PMD_SNR_A 0x5
6307 /* enum: PMA-PMD SNR B. */
6308 #define MC_CMD_PMA_PMD_SNR_B 0x6
6309 /* enum: PMA-PMD SNR C. */
6310 #define MC_CMD_PMA_PMD_SNR_C 0x7
6311 /* enum: PMA-PMD SNR D. */
6312 #define MC_CMD_PMA_PMD_SNR_D 0x8
6314 #define MC_CMD_PCS_LINK_UP 0x9
6316 #define MC_CMD_PCS_RX_FAULT 0xa
6318 #define MC_CMD_PCS_TX_FAULT 0xb
6320 #define MC_CMD_PCS_BER 0xc
6322 #define MC_CMD_PCS_BLOCK_ERRORS 0xd
6324 #define MC_CMD_PHYXS_LINK_UP 0xe
6326 #define MC_CMD_PHYXS_RX_FAULT 0xf
6328 #define MC_CMD_PHYXS_TX_FAULT 0x10
6330 #define MC_CMD_PHYXS_ALIGN 0x11
6332 #define MC_CMD_PHYXS_SYNC 0x12
6333 /* enum: AN link-up. */
6334 #define MC_CMD_AN_LINK_UP 0x13
6336 #define MC_CMD_AN_COMPLETE 0x14
6338 #define MC_CMD_AN_10GBT_STATUS 0x15
6339 /* enum: Clause 22 Link-Up. */
6340 #define MC_CMD_CL22_LINK_UP 0x16
6342 #define MC_CMD_PHY_NSTATS 0x17
6350 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
6352 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
6354 * effect. Returns: 0, ETIME
6356 #define MC_CMD_MAC_STATS 0x2e
6364 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
6366 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
6367 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LEN 4
6368 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LBN 0
6370 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
6371 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LEN 4
6375 #define MC_CMD_MAC_STATS_IN_CMD_LEN 4
6377 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0
6389 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
6403 #define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4
6406 #define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4
6409 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
6413 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
6415 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
6416 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LEN 4
6417 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LBN 0
6419 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
6420 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LEN 4
6424 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
6425 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
6426 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
6427 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
6428 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
6429 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
6430 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
6431 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
6432 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
6433 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
6434 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
6435 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
6436 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
6437 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
6438 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
6439 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
6440 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
6441 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
6442 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
6443 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
6444 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
6445 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
6446 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
6447 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
6448 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
6449 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
6450 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
6451 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
6452 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
6453 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
6454 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
6455 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
6456 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
6457 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
6458 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
6459 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
6460 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
6461 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
6462 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
6463 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
6464 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
6465 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
6466 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
6467 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
6468 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
6469 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
6470 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
6471 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
6472 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
6473 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
6474 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
6475 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
6476 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
6477 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
6478 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
6479 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
6480 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
6481 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
6482 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
6483 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
6484 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
6488 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
6492 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
6496 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
6500 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
6504 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40
6508 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41
6512 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
6516 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
6520 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
6521 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
6524 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
6528 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
6532 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
6533 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
6534 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
6535 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
6536 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
6537 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
6538 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
6539 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
6540 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
6541 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
6542 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
6543 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
6544 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
6545 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
6546 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
6547 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
6548 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
6549 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
6550 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
6551 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
6552 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
6554 #define MC_CMD_GMAC_DMABUF_START 0x40
6556 #define MC_CMD_GMAC_DMABUF_END 0x5f
6562 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that
6564 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *
6565 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
6567 #define MC_CMD_MAC_GENERATION_END 0x60
6568 #define MC_CMD_MAC_NSTATS 0x61 /* enum */
6571 #define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0
6575 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
6577 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
6578 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LEN 4
6579 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LBN 0
6581 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
6582 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LEN 4
6587 #define MC_CMD_MAC_FEC_DMABUF_START 0x61
6588 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
6590 #define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
6591 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
6593 #define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
6594 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
6595 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
6596 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
6597 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
6598 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
6599 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
6600 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
6601 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
6605 #define MC_CMD_MAC_NSTATS_V2 0x68
6610 #define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0
6614 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
6616 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
6617 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LEN 4
6618 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LBN 0
6620 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
6621 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LEN 4
6626 #define MC_CMD_MAC_CTPIO_DMABUF_START 0x68
6630 #define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
6634 #define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
6638 #define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
6640 #define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
6644 #define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
6648 #define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
6652 #define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
6656 #define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
6658 * or not 32-bit aligned
6660 #define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
6664 #define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
6667 #define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
6671 #define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
6673 #define MC_CMD_MAC_CTPIO_SUCCESS 0x74
6675 #define MC_CMD_MAC_CTPIO_FALLBACK 0x75
6679 #define MC_CMD_MAC_CTPIO_POISON 0x76
6681 #define MC_CMD_MAC_CTPIO_ERASE 0x77
6685 #define MC_CMD_MAC_NSTATS_V3 0x79
6690 #define MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 0
6694 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0
6696 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0
6697 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LEN 4
6698 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LBN 0
6700 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4
6701 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LEN 4
6706 #define MC_CMD_MAC_V4_DMABUF_START 0x79
6710 #define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79
6714 #define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a
6718 #define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b
6722 #define MC_CMD_MAC_NSTATS_V4 0x7d
6731 #define MC_CMD_SRIOV 0x30
6735 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0
6736 #define MC_CMD_SRIOV_IN_ENABLE_LEN 4
6737 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4
6738 #define MC_CMD_SRIOV_IN_VI_BASE_LEN 4
6740 #define MC_CMD_SRIOV_IN_VF_COUNT_LEN 4
6744 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
6745 #define MC_CMD_SRIOV_OUT_VI_SCALE_LEN 4
6746 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
6747 #define MC_CMD_SRIOV_OUT_VF_TOTAL_LEN 4
6752 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
6753 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LEN 4
6754 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
6756 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
6757 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LEN 4
6763 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_LEN 4
6767 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_LEN 4
6773 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LEN 4
6774 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
6780 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_LEN 4
6784 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_LEN 4
6790 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LEN 4
6808 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and
6813 * Returns: 0, EINVAL (invalid RID)
6815 #define MC_CMD_MEMCPY 0x31
6821 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
6822 #define MC_CMD_MEMCPY_IN_RECORD_NUM(len) (((len)-0)/32)
6824 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0
6831 #define MC_CMD_MEMCPY_OUT_LEN 0
6838 #define MC_CMD_WOL_FILTER_SET 0x32
6845 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
6846 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
6847 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
6848 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
6850 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
6851 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
6853 #define MC_CMD_WOL_TYPE_MAGIC 0x0
6855 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
6857 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
6859 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
6861 #define MC_CMD_WOL_TYPE_BITMAP 0x5
6863 #define MC_CMD_WOL_TYPE_LINK 0x6
6865 #define MC_CMD_WOL_TYPE_MAX 0x7
6867 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
6872 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6873 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6874 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6875 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6879 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LEN 4
6883 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LEN 4
6889 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6890 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6891 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6892 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6894 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4
6896 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4
6904 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6905 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6906 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6907 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6919 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6920 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6921 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6922 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6936 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
6937 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
6938 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
6939 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
6941 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4
6943 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
6950 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
6951 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
6952 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4
6957 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
6959 #define MC_CMD_WOL_FILTER_REMOVE 0x33
6965 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
6966 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
6967 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4
6970 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
6975 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
6978 #define MC_CMD_WOL_FILTER_RESET 0x34
6984 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
6985 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
6986 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4
6987 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
6988 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
6991 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
6998 #define MC_CMD_SET_MCAST_HASH 0x35
7002 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
7008 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0
7014 * Locks required: none. Returns: 0
7016 #define MC_CMD_NVRAM_TYPES 0x36
7022 #define MC_CMD_NVRAM_TYPES_IN_LEN 0
7025 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4
7027 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
7028 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4
7030 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
7032 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1
7034 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
7036 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
7038 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
7040 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
7042 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
7044 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
7046 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
7048 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
7050 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
7052 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
7054 #define MC_CMD_NVRAM_TYPE_LOG 0xc
7056 #define MC_CMD_NVRAM_TYPE_FPGA 0xd
7058 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
7060 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf
7062 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
7064 #define MC_CMD_NVRAM_TYPE_CPLD 0x11
7066 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12
7068 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13
7070 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14
7075 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
7078 #define MC_CMD_NVRAM_INFO 0x37
7084 #define MC_CMD_NVRAM_INFO_IN_LEN 4
7085 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
7086 #define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4
7092 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
7093 #define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4
7096 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
7097 #define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4
7099 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4
7101 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4
7103 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
7124 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4
7126 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4
7130 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0
7131 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4
7134 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4
7135 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4
7137 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4
7139 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4
7141 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
7156 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4
7158 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4
7162 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4
7168 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
7175 #define MC_CMD_NVRAM_UPDATE_START 0x38
7183 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
7184 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
7185 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4
7195 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0
7196 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4
7199 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4
7200 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4
7201 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 4
7202 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
7206 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
7212 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7215 #define MC_CMD_NVRAM_READ 0x39
7222 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
7223 #define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4
7226 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
7227 #define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4
7230 #define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4
7234 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0
7235 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4
7238 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4
7239 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4
7242 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4
7246 * from. This allows it to perform a read-modify-write-verify with the write
7252 #define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4
7257 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0
7261 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1
7262 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B
7265 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2
7271 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
7272 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)
7273 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
7283 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7286 #define MC_CMD_NVRAM_WRITE 0x3a
7296 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1)
7297 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
7298 #define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
7301 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
7302 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4
7304 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4
7312 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0
7318 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7321 #define MC_CMD_NVRAM_ERASE 0x3b
7328 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
7329 #define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4
7332 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
7333 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4
7335 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4
7338 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0
7344 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/
7351 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
7360 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
7361 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4
7364 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
7365 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4
7373 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0
7374 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4
7377 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4
7378 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4
7380 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
7382 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
7397 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
7411 * per-partition nvram lock in firmware is only released after the verification
7414 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
7417 * the field are marked with a prefix 'Internal-error'.
7419 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
7420 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
7421 /* enum: Invalid return code; only non-zero values are defined. Defined as
7424 #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0
7426 #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1
7428 #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2
7430 #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3
7432 #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4
7433 /* enum: Error in message digest calculated over the reflash-header, payload
7434 * and reflash-trailer.
7436 #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5
7438 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6
7440 #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7
7442 #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8
7444 #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9
7446 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa
7450 #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb
7451 /* enum: The image contains a test-signed certificate, but the adapter accepts
7454 #define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
7456 #define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
7457 /* enum: Internal-error. The signed image is missing the 'contents' section,
7460 #define MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe
7461 /* enum: Internal-error. The bundle header is invalid. */
7462 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf
7463 /* enum: Internal-error. The bundle does not have a valid reflash image layout.
7465 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10
7466 /* enum: Internal-error. The bundle has an inconsistent layout of components or
7469 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11
7470 /* enum: Internal-error. The bundle manifest is inconsistent with components in
7473 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12
7474 /* enum: Internal-error. The number of components in a bundle do not match the
7477 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13
7478 /* enum: Internal-error. The bundle contains too many components for the MC
7481 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14
7482 /* enum: Internal-error. The bundle manifest has an invalid/inconsistent
7485 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15
7486 /* enum: Internal-error. The hash of a component does not match the hash stored
7489 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16
7490 /* enum: Internal-error. Component hash calculation failed. */
7491 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17
7492 /* enum: Internal-error. The component does not have a valid reflash image
7495 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18
7499 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19
7500 /* enum: The update operation is in-progress. */
7501 #define MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a
7517 * REBOOT_ON_ASSERT=0.
7520 * DATALEN=0
7522 #define MC_CMD_REBOOT 0x3d
7528 #define MC_CMD_REBOOT_IN_LEN 4
7529 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0
7530 #define MC_CMD_REBOOT_IN_FLAGS_LEN 4
7531 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
7534 #define MC_CMD_REBOOT_OUT_LEN 0
7543 #define MC_CMD_SCHEDINFO 0x3e
7549 #define MC_CMD_SCHEDINFO_IN_LEN 0
7552 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4
7555 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
7556 #define MC_CMD_SCHEDINFO_OUT_DATA_NUM(len) (((len)-0)/4)
7557 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
7558 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
7569 #define MC_CMD_REBOOT_MODE 0x3f
7575 #define MC_CMD_REBOOT_MODE_IN_LEN 4
7576 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
7577 #define MC_CMD_REBOOT_MODE_IN_VALUE_LEN 4
7579 #define MC_CMD_REBOOT_MODE_NORMAL 0x0
7580 /* enum: Power-on Reset. */
7581 #define MC_CMD_REBOOT_MODE_POR 0x2
7583 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3
7585 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
7586 #define MC_CMD_REBOOT_MODE_IN_FAKE_OFST 0
7591 #define MC_CMD_REBOOT_MODE_OUT_LEN 4
7592 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
7593 #define MC_CMD_REBOOT_MODE_OUT_VALUE_LEN 4
7614 * backward compatibility, older host software can only use sensors in page 0.
7619 * page 0 of sensor information, with bit 31 in the sensor mask cleared.
7625 * Locks required: None Returns: 0
7627 #define MC_CMD_SENSOR_INFO 0x41
7633 #define MC_CMD_SENSOR_INFO_IN_LEN 0
7636 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
7639 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
7643 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
7644 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4
7650 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
7654 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_OFST 0
7655 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 4
7657 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 4
7658 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 4
7659 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 4
7660 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 0
7664 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4
7667 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
7668 #define MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
7669 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
7670 #define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
7672 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
7674 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
7676 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
7677 /* enum: Phy 0 temperature: degC */
7678 #define MC_CMD_SENSOR_PHY0_TEMP 0x3
7679 /* enum: Phy 0 cooling: bool */
7680 #define MC_CMD_SENSOR_PHY0_COOLING 0x4
7682 #define MC_CMD_SENSOR_PHY1_TEMP 0x5
7684 #define MC_CMD_SENSOR_PHY1_COOLING 0x6
7686 #define MC_CMD_SENSOR_IN_1V0 0x7
7688 #define MC_CMD_SENSOR_IN_1V2 0x8
7690 #define MC_CMD_SENSOR_IN_1V8 0x9
7692 #define MC_CMD_SENSOR_IN_2V5 0xa
7694 #define MC_CMD_SENSOR_IN_3V3 0xb
7696 #define MC_CMD_SENSOR_IN_12V0 0xc
7698 #define MC_CMD_SENSOR_IN_1V2A 0xd
7700 #define MC_CMD_SENSOR_IN_VREF 0xe
7702 #define MC_CMD_SENSOR_OUT_VAOE 0xf
7704 #define MC_CMD_SENSOR_AOE_TEMP 0x10
7706 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
7708 #define MC_CMD_SENSOR_PSU_TEMP 0x12
7709 /* enum: Fan 0 speed: RPM */
7710 #define MC_CMD_SENSOR_FAN_0 0x13
7712 #define MC_CMD_SENSOR_FAN_1 0x14
7714 #define MC_CMD_SENSOR_FAN_2 0x15
7716 #define MC_CMD_SENSOR_FAN_3 0x16
7717 /* enum: Fan 4 speed: RPM */
7718 #define MC_CMD_SENSOR_FAN_4 0x17
7720 #define MC_CMD_SENSOR_IN_VAOE 0x18
7722 #define MC_CMD_SENSOR_OUT_IAOE 0x19
7724 #define MC_CMD_SENSOR_IN_IAOE 0x1a
7726 #define MC_CMD_SENSOR_NIC_POWER 0x1b
7728 #define MC_CMD_SENSOR_IN_0V9 0x1c
7730 #define MC_CMD_SENSOR_IN_I0V9 0x1d
7732 #define MC_CMD_SENSOR_IN_I1V2 0x1e
7734 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
7736 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20
7738 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
7740 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
7742 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
7744 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
7746 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
7748 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
7750 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
7752 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
7754 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
7756 #define MC_CMD_SENSOR_AIRFLOW 0x2a
7758 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
7760 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
7762 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
7763 /* enum: Port 0 PHY power switch over-current: bool */
7764 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
7765 /* enum: Port 1 PHY power switch over-current: bool */
7766 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
7767 /* enum: Mop-up microcontroller reference voltage: mV */
7768 #define MC_CMD_SENSOR_MUM_VCC 0x30
7770 #define MC_CMD_SENSOR_IN_0V9_A 0x31
7772 #define MC_CMD_SENSOR_IN_I0V9_A 0x32
7774 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
7776 #define MC_CMD_SENSOR_IN_0V9_B 0x34
7778 #define MC_CMD_SENSOR_IN_I0V9_B 0x35
7780 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
7782 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
7784 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
7786 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
7788 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
7790 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
7792 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f
7796 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
7798 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
7802 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
7804 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
7808 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
7810 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
7814 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
7816 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
7818 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49
7819 /* enum: Temperature of SODIMM 0 (if installed): degC */
7820 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
7822 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
7823 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
7824 #define MC_CMD_SENSOR_PHY0_VCC 0x4c
7826 #define MC_CMD_SENSOR_PHY1_VCC 0x4d
7828 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
7830 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
7832 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
7834 #define MC_CMD_SENSOR_IN_I1V8 0x51
7836 #define MC_CMD_SENSOR_IN_I2V5 0x52
7838 #define MC_CMD_SENSOR_IN_I3V3 0x53
7840 #define MC_CMD_SENSOR_IN_I12V0 0x54
7842 #define MC_CMD_SENSOR_IN_1V3 0x55
7844 #define MC_CMD_SENSOR_IN_I1V3 0x56
7846 #define MC_CMD_SENSOR_ENGINEERING_1 0x57
7848 #define MC_CMD_SENSOR_ENGINEERING_2 0x58
7850 #define MC_CMD_SENSOR_ENGINEERING_3 0x59
7851 /* enum: Engineering sensor 4 */
7852 #define MC_CMD_SENSOR_ENGINEERING_4 0x5a
7854 #define MC_CMD_SENSOR_ENGINEERING_5 0x5b
7856 #define MC_CMD_SENSOR_ENGINEERING_6 0x5c
7858 #define MC_CMD_SENSOR_ENGINEERING_7 0x5d
7860 #define MC_CMD_SENSOR_ENGINEERING_8 0x5e
7862 #define MC_CMD_SENSOR_PAGE2_NEXT 0x5f
7864 #define MC_CMD_SENSOR_ENTRY_OFST 4
7866 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4
7867 #define MC_CMD_SENSOR_ENTRY_LO_LEN 4
7871 #define MC_CMD_SENSOR_ENTRY_HI_LEN 4
7874 #define MC_CMD_SENSOR_ENTRY_MINNUM 0
7879 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
7882 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
7883 #define MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
7884 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
7885 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
7888 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_OFST 0
7892 /* MC_CMD_SENSOR_ENTRY_OFST 4 */
7894 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
7895 /* MC_CMD_SENSOR_ENTRY_LO_LEN 4 */
7899 /* MC_CMD_SENSOR_ENTRY_HI_LEN 4 */
7902 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
7908 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
7910 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
7916 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
7933 * If the request does not contain the LENGTH field then only sensors 0 to 30
7943 #define MC_CMD_READ_SENSORS 0x42
7950 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
7952 * If the address is 0xffffffffffffffff send the readings in the response (used
7955 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
7957 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
7958 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LEN 4
7959 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LBN 0
7961 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
7962 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LEN 4
7968 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
7970 * If the address is 0xffffffffffffffff send the readings in the response (used
7973 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
7975 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
7976 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LEN 4
7977 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LBN 0
7979 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
7980 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LEN 4
7985 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
7989 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
7991 * If the address is 0xffffffffffffffff send the readings in the response (used
7994 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0
7996 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0
7997 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LEN 4
7998 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LBN 0
8000 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4
8001 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LEN 4
8006 #define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4
8009 #define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 4
8011 #define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 0
8015 #define MC_CMD_READ_SENSORS_OUT_LEN 0
8018 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
8021 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
8022 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
8024 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
8029 #define MC_CMD_SENSOR_STATE_OK 0x0
8031 #define MC_CMD_SENSOR_STATE_WARNING 0x1
8033 #define MC_CMD_SENSOR_STATE_FATAL 0x2
8035 #define MC_CMD_SENSOR_STATE_BROKEN 0x3
8037 #define MC_CMD_SENSOR_STATE_NO_READING 0x4
8039 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
8054 * code: 0
8056 #define MC_CMD_GET_PHY_STATE 0x43
8062 #define MC_CMD_GET_PHY_STATE_IN_LEN 0
8065 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4
8066 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
8067 #define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4
8069 #define MC_CMD_PHY_STATE_OK 0x1
8071 #define MC_CMD_PHY_STATE_ZOMBIE 0x2
8076 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
8079 #define MC_CMD_SETUP_8021QBB 0x44
8083 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
8087 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0
8092 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
8094 #define MC_CMD_WOL_FILTER_GET 0x45
8100 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0
8103 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
8104 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
8105 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4
8110 * Add a protocol offload to NIC for lights-out state. Locks required: None.
8111 * Returns: 0, ENOSYS
8113 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
8122 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
8123 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_NUM(len) (((len)-4)/4)
8124 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
8125 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
8126 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
8127 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
8128 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
8129 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
8136 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
8137 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
8138 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
8141 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_LEN 4
8145 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
8146 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4 */
8147 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
8155 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
8156 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
8157 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_LEN 4
8162 * Remove a protocol offload from NIC for lights-out state. Locks required:
8163 * None. Returns: 0, ENOSYS
8165 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
8172 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
8173 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_LEN 4
8174 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
8175 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_LEN 4
8178 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
8183 * Restore MAC after block reset. Locks required: None. Returns: 0.
8185 #define MC_CMD_MAC_RESET_RESTORE 0x48
8188 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
8191 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
8196 * Deliberately trigger an assert-detonation in the firmware for testing
8198 * required: None Returns: 0
8200 #define MC_CMD_TESTASSERT 0x49
8206 #define MC_CMD_TESTASSERT_IN_LEN 0
8209 #define MC_CMD_TESTASSERT_OUT_LEN 0
8212 #define MC_CMD_TESTASSERT_V2_IN_LEN 4
8214 #define MC_CMD_TESTASSERT_V2_IN_TYPE_OFST 0
8215 #define MC_CMD_TESTASSERT_V2_IN_TYPE_LEN 4
8219 #define MC_CMD_TESTASSERT_V2_IN_FAIL_ASSERTION_WITH_USEFUL_VALUES 0x0
8220 /* enum: Assert using assert(0); */
8221 #define MC_CMD_TESTASSERT_V2_IN_ASSERT_FALSE 0x1
8223 #define MC_CMD_TESTASSERT_V2_IN_WATCHDOG 0x2
8225 #define MC_CMD_TESTASSERT_V2_IN_LOAD_TRAP 0x3
8227 #define MC_CMD_TESTASSERT_V2_IN_STORE_TRAP 0x4
8229 #define MC_CMD_TESTASSERT_V2_IN_JUMP_TRAP 0x5
8232 #define MC_CMD_TESTASSERT_V2_OUT_LEN 0
8238 * understand the given workaround number - which should not be treated as a
8240 * workaround, that's between the driver and the mcfw on a per-workaround
8241 * basis. Locks required: None. Returns: 0, EINVAL .
8243 #define MC_CMD_WORKAROUND 0x4a
8251 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
8252 #define MC_CMD_WORKAROUND_IN_TYPE_LEN 4
8254 #define MC_CMD_WORKAROUND_BUG17230 0x1
8256 #define MC_CMD_WORKAROUND_BUG35388 0x2
8258 #define MC_CMD_WORKAROUND_BUG35017 0x3
8260 #define MC_CMD_WORKAROUND_BUG41750 0x4
8262 * - before adding code that queries this workaround, remember that there's
8266 #define MC_CMD_WORKAROUND_BUG42008 0x5
8274 #define MC_CMD_WORKAROUND_BUG26807 0x6
8276 #define MC_CMD_WORKAROUND_BUG61265 0x7
8277 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
8280 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
8281 #define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4
8284 #define MC_CMD_WORKAROUND_OUT_LEN 0
8289 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4
8290 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
8291 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4
8292 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 0
8293 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
8299 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
8302 * output data, are interpreted on a per-type basis. For SFP+, PAGE=0 or 1
8303 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
8304 * For QSFP, PAGE=-1 is the lower (unbanked) page. PAGE=2 is the EEPROM and
8308 * of "0xffff:0xffff" retrieves the lower (unbanked) page. Locks required -
8309 * None. Return code - 0.
8311 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
8317 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
8318 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
8319 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4
8320 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_OFST 0
8321 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_LBN 0
8323 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_OFST 0
8331 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
8332 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1)
8334 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
8335 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
8336 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
8348 #define MC_CMD_NVRAM_TEST 0x4c
8354 #define MC_CMD_NVRAM_TEST_IN_LEN 4
8355 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
8356 #define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4
8361 #define MC_CMD_NVRAM_TEST_OUT_LEN 4
8362 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
8363 #define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4
8365 #define MC_CMD_NVRAM_TEST_PASS 0x0
8367 #define MC_CMD_NVRAM_TEST_FAIL 0x1
8369 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2
8376 * they are configured first. Locks required: None. Return code: 0, EINVAL.
8378 #define MC_CMD_MRSFP_TWEAK 0x4d
8382 /* 0-6 low->high de-emph. */
8383 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
8384 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_LEN 4
8385 /* 0-8 low->high ref.V */
8386 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
8387 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_LEN 4
8388 /* 0-8 0-8 low->high boost */
8390 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_LEN 4
8391 /* 0-8 low->high ref.V */
8393 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_LEN 4
8396 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
8401 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
8402 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_LEN 4
8404 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
8405 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_LEN 4
8408 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_LEN 4
8410 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0
8412 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1
8417 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:
8421 #define MC_CMD_SENSOR_SET_LIMS 0x4e
8428 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
8429 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_LEN 4
8432 /* interpretation is is sensor-specific. */
8433 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
8434 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_LEN 4
8435 /* interpretation is is sensor-specific. */
8437 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_LEN 4
8438 /* interpretation is is sensor-specific. */
8440 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_LEN 4
8441 /* interpretation is is sensor-specific. */
8443 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_LEN 4
8446 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
8452 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f
8455 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
8459 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
8460 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_LEN 4
8461 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
8462 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_LEN 4
8464 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_LEN 4
8466 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_LEN 4
8472 * none. Returns: 0, EINVAL (bad type).
8474 #define MC_CMD_NVRAM_PARTITIONS 0x51
8480 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
8483 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
8486 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
8487 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4)
8489 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
8490 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
8492 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
8493 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
8494 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
8502 * none. Returns: 0, EINVAL (bad type).
8504 #define MC_CMD_NVRAM_METADATA 0x52
8510 #define MC_CMD_NVRAM_METADATA_IN_LEN 4
8512 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
8513 #define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4
8520 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1)
8522 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
8523 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
8524 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
8525 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4
8526 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 4
8527 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
8529 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 4
8532 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 4
8537 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4
8547 /* 4th component of W.X.Y.Z version number for content of this partition */
8550 /* Zero-terminated string describing the content of this partition */
8553 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
8562 #define MC_CMD_GET_MAC_ADDRESSES 0x55
8568 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
8573 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
8580 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4
8583 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4
8588 * Perform a CLP related operation, see SF-110495-PS for details of CLP
8590 * different manufacturers which are to be found in SF-119187-TC, SF-119186-TC,
8591 * SF-120509-TC and SF-117282-PS.
8593 #define MC_CMD_CLP 0x56
8599 #define MC_CMD_CLP_IN_LEN 4
8601 #define MC_CMD_CLP_IN_OP_OFST 0
8602 #define MC_CMD_CLP_IN_OP_LEN 4
8604 #define MC_CMD_CLP_OP_DEFAULT 0x1
8606 #define MC_CMD_CLP_OP_SET_MAC 0x2
8608 #define MC_CMD_CLP_OP_GET_MAC 0x3
8610 #define MC_CMD_CLP_OP_SET_BOOT 0x4
8612 #define MC_CMD_CLP_OP_GET_BOOT 0x5
8615 #define MC_CMD_CLP_OUT_LEN 0
8618 #define MC_CMD_CLP_IN_DEFAULT_LEN 4
8619 /* MC_CMD_CLP_IN_OP_OFST 0 */
8620 /* MC_CMD_CLP_IN_OP_LEN 4 */
8623 #define MC_CMD_CLP_OUT_DEFAULT_LEN 0
8627 /* MC_CMD_CLP_IN_OP_OFST 0 */
8628 /* MC_CMD_CLP_IN_OP_LEN 4 */
8630 * restores the permanent (factory-programmed) MAC address associated with the
8631 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
8633 #define MC_CMD_CLP_IN_SET_MAC_ADDR_OFST 4
8640 #define MC_CMD_CLP_OUT_SET_MAC_LEN 0
8644 /* MC_CMD_CLP_IN_OP_OFST 0 */
8645 /* MC_CMD_CLP_IN_OP_LEN 4 */
8647 * restores the permanent (factory-programmed) MAC address associated with the
8648 * port. A non-zero MAC address persists until a PCIe reset or a power cycle.
8650 #define MC_CMD_CLP_IN_SET_MAC_V2_ADDR_OFST 4
8656 #define MC_CMD_CLP_IN_SET_MAC_V2_FLAGS_LEN 4
8658 #define MC_CMD_CLP_IN_SET_MAC_V2_VIRTUAL_LBN 0
8662 #define MC_CMD_CLP_IN_GET_MAC_LEN 4
8663 /* MC_CMD_CLP_IN_OP_OFST 0 */
8664 /* MC_CMD_CLP_IN_OP_LEN 4 */
8668 /* MC_CMD_CLP_IN_OP_OFST 0 */
8669 /* MC_CMD_CLP_IN_OP_LEN 4 */
8670 #define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_OFST 4
8671 #define MC_CMD_CLP_IN_GET_MAC_V2_FLAGS_LEN 4
8672 #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_OFST 4
8673 #define MC_CMD_CLP_IN_GET_MAC_V2_PERMANENT_LBN 0
8679 #define MC_CMD_CLP_OUT_GET_MAC_ADDR_OFST 0
8687 /* MC_CMD_CLP_IN_OP_OFST 0 */
8688 /* MC_CMD_CLP_IN_OP_LEN 4 */
8690 #define MC_CMD_CLP_IN_SET_BOOT_FLAG_OFST 4
8694 #define MC_CMD_CLP_OUT_SET_BOOT_LEN 0
8697 #define MC_CMD_CLP_IN_GET_BOOT_LEN 4
8698 /* MC_CMD_CLP_IN_OP_OFST 0 */
8699 /* MC_CMD_CLP_IN_OP_LEN 4 */
8702 #define MC_CMD_CLP_OUT_GET_BOOT_LEN 4
8704 #define MC_CMD_CLP_OUT_GET_BOOT_FLAG_OFST 0
8715 #define MC_CMD_MUM 0x57
8721 #define MC_CMD_MUM_IN_LEN 4
8722 #define MC_CMD_MUM_IN_OP_HDR_OFST 0
8723 #define MC_CMD_MUM_IN_OP_HDR_LEN 4
8724 #define MC_CMD_MUM_IN_OP_OFST 0
8725 #define MC_CMD_MUM_IN_OP_LBN 0
8728 #define MC_CMD_MUM_OP_NULL 0x1
8730 #define MC_CMD_MUM_OP_GET_VERSION 0x2
8732 #define MC_CMD_MUM_OP_RAW_CMD 0x3
8734 #define MC_CMD_MUM_OP_READ 0x4
8736 #define MC_CMD_MUM_OP_WRITE 0x5
8738 #define MC_CMD_MUM_OP_LOG 0x6
8740 #define MC_CMD_MUM_OP_GPIO 0x7
8742 #define MC_CMD_MUM_OP_READ_SENSORS 0x8
8744 #define MC_CMD_MUM_OP_PROGRAM_CLOCKS 0x9
8746 #define MC_CMD_MUM_OP_FPGA_LOAD 0xa
8750 #define MC_CMD_MUM_OP_READ_ATB_SENSOR 0xb
8754 #define MC_CMD_MUM_OP_QSFP 0xc
8758 #define MC_CMD_MUM_OP_READ_DDR_INFO 0xd
8761 #define MC_CMD_MUM_IN_NULL_LEN 4
8763 #define MC_CMD_MUM_IN_CMD_OFST 0
8764 #define MC_CMD_MUM_IN_CMD_LEN 4
8767 #define MC_CMD_MUM_IN_GET_VERSION_LEN 4
8769 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8770 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8775 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8776 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8778 #define MC_CMD_MUM_IN_READ_DEVICE_OFST 4
8779 #define MC_CMD_MUM_IN_READ_DEVICE_LEN 4
8781 #define MC_CMD_MUM_DEV_HITTITE 0x1
8782 /* enum: Hittite HMC1035 clock generator for NIC-side on Sorrento board */
8783 #define MC_CMD_MUM_DEV_HITTITE_NIC 0x2
8784 /* 32-bit address to read from */
8786 #define MC_CMD_MUM_IN_READ_ADDR_LEN 4
8789 #define MC_CMD_MUM_IN_READ_NUMWORDS_LEN 4
8795 #define MC_CMD_MUM_IN_WRITE_LEN(num) (12+4*(num))
8796 #define MC_CMD_MUM_IN_WRITE_BUFFER_NUM(len) (((len)-12)/4)
8798 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8799 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8801 #define MC_CMD_MUM_IN_WRITE_DEVICE_OFST 4
8802 #define MC_CMD_MUM_IN_WRITE_DEVICE_LEN 4
8804 /* MC_CMD_MUM_DEV_HITTITE 0x1 */
8805 /* 32-bit address to write to */
8807 #define MC_CMD_MUM_IN_WRITE_ADDR_LEN 4
8810 #define MC_CMD_MUM_IN_WRITE_BUFFER_LEN 4
8820 #define MC_CMD_MUM_IN_RAW_CMD_WRITE_DATA_NUM(len) (((len)-16)/1)
8822 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8823 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8825 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_OFST 4
8826 #define MC_CMD_MUM_IN_RAW_CMD_CMD_CODE_LEN 4
8829 #define MC_CMD_MUM_IN_RAW_CMD_NUM_WRITE_LEN 4
8832 #define MC_CMD_MUM_IN_RAW_CMD_NUM_READ_LEN 4
8843 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8844 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8845 #define MC_CMD_MUM_IN_LOG_OP_OFST 4
8846 #define MC_CMD_MUM_IN_LOG_OP_LEN 4
8847 #define MC_CMD_MUM_IN_LOG_OP_UART 0x1 /* enum */
8851 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8852 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8853 /* MC_CMD_MUM_IN_LOG_OP_OFST 4 */
8854 /* MC_CMD_MUM_IN_LOG_OP_LEN 4 */
8857 #define MC_CMD_MUM_IN_LOG_OP_UART_ENABLE_LEN 4
8862 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8863 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8864 #define MC_CMD_MUM_IN_GPIO_HDR_OFST 4
8865 #define MC_CMD_MUM_IN_GPIO_HDR_LEN 4
8866 #define MC_CMD_MUM_IN_GPIO_OPCODE_OFST 4
8867 #define MC_CMD_MUM_IN_GPIO_OPCODE_LBN 0
8869 #define MC_CMD_MUM_IN_GPIO_IN_READ 0x0 /* enum */
8870 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE 0x1 /* enum */
8871 #define MC_CMD_MUM_IN_GPIO_OUT_READ 0x2 /* enum */
8872 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE 0x3 /* enum */
8873 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ 0x4 /* enum */
8874 #define MC_CMD_MUM_IN_GPIO_OP 0x5 /* enum */
8878 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8879 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8880 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_OFST 4
8881 #define MC_CMD_MUM_IN_GPIO_IN_READ_HDR_LEN 4
8885 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8886 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8887 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_OFST 4
8888 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_HDR_LEN 4
8889 /* The first 32-bit word to be written to the GPIO OUT register. */
8891 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK1_LEN 4
8892 /* The second 32-bit word to be written to the GPIO OUT register. */
8894 #define MC_CMD_MUM_IN_GPIO_OUT_WRITE_GPIOMASK2_LEN 4
8898 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8899 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8900 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_OFST 4
8901 #define MC_CMD_MUM_IN_GPIO_OUT_READ_HDR_LEN 4
8905 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8906 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8907 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_OFST 4
8908 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_HDR_LEN 4
8909 /* The first 32-bit word to be written to the GPIO OUT ENABLE register. */
8911 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK1_LEN 4
8912 /* The second 32-bit word to be written to the GPIO OUT ENABLE register. */
8914 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_WRITE_GPIOMASK2_LEN 4
8918 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8919 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8920 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_OFST 4
8921 #define MC_CMD_MUM_IN_GPIO_OUT_ENABLE_READ_HDR_LEN 4
8925 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8926 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8927 #define MC_CMD_MUM_IN_GPIO_OP_HDR_OFST 4
8928 #define MC_CMD_MUM_IN_GPIO_OP_HDR_LEN 4
8929 #define MC_CMD_MUM_IN_GPIO_OP_BITWISE_OP_OFST 4
8932 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ 0x0 /* enum */
8933 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE 0x1 /* enum */
8934 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG 0x2 /* enum */
8935 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE 0x3 /* enum */
8936 #define MC_CMD_MUM_IN_GPIO_OP_GPIO_NUMBER_OFST 4
8942 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8943 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8944 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_OFST 4
8945 #define MC_CMD_MUM_IN_GPIO_OP_OUT_READ_HDR_LEN 4
8949 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8950 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8951 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_OFST 4
8952 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_HDR_LEN 4
8953 #define MC_CMD_MUM_IN_GPIO_OP_OUT_WRITE_WRITEBIT_OFST 4
8959 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8960 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8961 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_OFST 4
8962 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_HDR_LEN 4
8963 #define MC_CMD_MUM_IN_GPIO_OP_OUT_CONFIG_CFG_OFST 4
8969 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8970 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8971 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_OFST 4
8972 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_HDR_LEN 4
8973 #define MC_CMD_MUM_IN_GPIO_OP_OUT_ENABLE_ENABLEBIT_OFST 4
8980 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8981 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8982 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_OFST 4
8983 #define MC_CMD_MUM_IN_READ_SENSORS_PARAMS_LEN 4
8984 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_OFST 4
8985 #define MC_CMD_MUM_IN_READ_SENSORS_SENSOR_ID_LBN 0
8987 #define MC_CMD_MUM_IN_READ_SENSORS_NUM_SENSORS_OFST 4
8994 /* MC_CMD_MUM_IN_CMD_OFST 0 */
8995 /* MC_CMD_MUM_IN_CMD_LEN 4 */
8996 /* Bit-mask of clocks to be programmed */
8997 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_OFST 4
8998 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_MASK_LEN 4
8999 #define MC_CMD_MUM_CLOCK_ID_FPGA 0x0 /* enum */
9000 #define MC_CMD_MUM_CLOCK_ID_DDR 0x1 /* enum */
9001 #define MC_CMD_MUM_CLOCK_ID_NIC 0x2 /* enum */
9004 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_FLAGS_LEN 4
9006 #define MC_CMD_MUM_IN_PROGRAM_CLOCKS_OVERCLOCK_110_LBN 0
9018 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9019 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9021 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_OFST 4
9022 #define MC_CMD_MUM_IN_FPGA_LOAD_ENABLE_LEN 4
9025 #define MC_CMD_MUM_IN_READ_ATB_SENSOR_LEN 4
9027 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9028 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9033 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9034 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9035 #define MC_CMD_MUM_IN_QSFP_HDR_OFST 4
9036 #define MC_CMD_MUM_IN_QSFP_HDR_LEN 4
9037 #define MC_CMD_MUM_IN_QSFP_OPCODE_OFST 4
9038 #define MC_CMD_MUM_IN_QSFP_OPCODE_LBN 0
9039 #define MC_CMD_MUM_IN_QSFP_OPCODE_WIDTH 4
9040 #define MC_CMD_MUM_IN_QSFP_INIT 0x0 /* enum */
9041 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE 0x1 /* enum */
9042 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP 0x2 /* enum */
9043 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO 0x3 /* enum */
9044 #define MC_CMD_MUM_IN_QSFP_FILL_STATS 0x4 /* enum */
9045 #define MC_CMD_MUM_IN_QSFP_POLL_BIST 0x5 /* enum */
9047 #define MC_CMD_MUM_IN_QSFP_IDX_LEN 4
9051 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9052 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9053 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_OFST 4
9054 #define MC_CMD_MUM_IN_QSFP_INIT_HDR_LEN 4
9056 #define MC_CMD_MUM_IN_QSFP_INIT_IDX_LEN 4
9058 #define MC_CMD_MUM_IN_QSFP_INIT_CAGE_LEN 4
9062 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9063 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9064 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_OFST 4
9065 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_HDR_LEN 4
9067 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_IDX_LEN 4
9069 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_TX_DISABLE_LEN 4
9071 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LANES_LEN 4
9073 #define MC_CMD_MUM_IN_QSFP_RECONFIGURE_PORT_LINK_SPEED_LEN 4
9077 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9078 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9079 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_OFST 4
9080 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_HDR_LEN 4
9082 #define MC_CMD_MUM_IN_QSFP_GET_SUPPORTED_CAP_IDX_LEN 4
9086 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9087 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9088 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_OFST 4
9089 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_HDR_LEN 4
9091 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_IDX_LEN 4
9093 #define MC_CMD_MUM_IN_QSFP_GET_MEDIA_INFO_PAGE_LEN 4
9097 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9098 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9099 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_OFST 4
9100 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_HDR_LEN 4
9102 #define MC_CMD_MUM_IN_QSFP_FILL_STATS_IDX_LEN 4
9106 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9107 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9108 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_OFST 4
9109 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_HDR_LEN 4
9111 #define MC_CMD_MUM_IN_QSFP_POLL_BIST_IDX_LEN 4
9114 #define MC_CMD_MUM_IN_READ_DDR_INFO_LEN 4
9116 /* MC_CMD_MUM_IN_CMD_OFST 0 */
9117 /* MC_CMD_MUM_IN_CMD_LEN 4 */
9120 #define MC_CMD_MUM_OUT_LEN 0
9123 #define MC_CMD_MUM_OUT_NULL_LEN 0
9127 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_OFST 0
9128 #define MC_CMD_MUM_OUT_GET_VERSION_FIRMWARE_LEN 4
9129 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_OFST 4
9131 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_OFST 4
9132 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_LO_LEN 4
9136 #define MC_CMD_MUM_OUT_GET_VERSION_VERSION_HI_LEN 4
9144 #define MC_CMD_MUM_OUT_RAW_CMD_LEN(num) (0+1*(num))
9145 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_NUM(len) (((len)-0)/1)
9147 #define MC_CMD_MUM_OUT_RAW_CMD_DATA_OFST 0
9154 #define MC_CMD_MUM_OUT_READ_LENMIN 4
9157 #define MC_CMD_MUM_OUT_READ_LEN(num) (0+4*(num))
9158 #define MC_CMD_MUM_OUT_READ_BUFFER_NUM(len) (((len)-0)/4)
9159 #define MC_CMD_MUM_OUT_READ_BUFFER_OFST 0
9160 #define MC_CMD_MUM_OUT_READ_BUFFER_LEN 4
9166 #define MC_CMD_MUM_OUT_WRITE_LEN 0
9169 #define MC_CMD_MUM_OUT_LOG_LEN 0
9172 #define MC_CMD_MUM_OUT_LOG_OP_UART_LEN 0
9176 /* The first 32-bit word read from the GPIO IN register. */
9177 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_OFST 0
9178 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK1_LEN 4
9179 /* The second 32-bit word read from the GPIO IN register. */
9180 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_OFST 4
9181 #define MC_CMD_MUM_OUT_GPIO_IN_READ_GPIOMASK2_LEN 4
9184 #define MC_CMD_MUM_OUT_GPIO_OUT_WRITE_LEN 0
9188 /* The first 32-bit word read from the GPIO OUT register. */
9189 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_OFST 0
9190 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK1_LEN 4
9191 /* The second 32-bit word read from the GPIO OUT register. */
9192 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_OFST 4
9193 #define MC_CMD_MUM_OUT_GPIO_OUT_READ_GPIOMASK2_LEN 4
9196 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_WRITE_LEN 0
9200 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_OFST 0
9201 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK1_LEN 4
9202 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_OFST 4
9203 #define MC_CMD_MUM_OUT_GPIO_OUT_ENABLE_READ_GPIOMASK2_LEN 4
9206 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_LEN 4
9207 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_OFST 0
9208 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_READ_BIT_READ_LEN 4
9211 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_WRITE_LEN 0
9214 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_CONFIG_LEN 0
9217 #define MC_CMD_MUM_OUT_GPIO_OP_OUT_ENABLE_LEN 0
9220 #define MC_CMD_MUM_OUT_READ_SENSORS_LENMIN 4
9223 #define MC_CMD_MUM_OUT_READ_SENSORS_LEN(num) (0+4*(num))
9224 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_NUM(len) (((len)-0)/4)
9225 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_OFST 0
9226 #define MC_CMD_MUM_OUT_READ_SENSORS_DATA_LEN 4
9230 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_OFST 0
9231 #define MC_CMD_MUM_OUT_READ_SENSORS_READING_LBN 0
9233 #define MC_CMD_MUM_OUT_READ_SENSORS_STATE_OFST 0
9236 #define MC_CMD_MUM_OUT_READ_SENSORS_TYPE_OFST 0
9241 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_LEN 4
9242 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_OFST 0
9243 #define MC_CMD_MUM_OUT_PROGRAM_CLOCKS_OK_MASK_LEN 4
9246 #define MC_CMD_MUM_OUT_FPGA_LOAD_LEN 0
9249 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_LEN 4
9250 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_OFST 0
9251 #define MC_CMD_MUM_OUT_READ_ATB_SENSOR_RESULT_LEN 4
9254 #define MC_CMD_MUM_OUT_QSFP_INIT_LEN 0
9258 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_OFST 0
9259 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LP_CAP_LEN 4
9260 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_OFST 4
9261 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_FLAGS_LEN 4
9262 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_OFST 4
9263 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_READY_LBN 0
9265 #define MC_CMD_MUM_OUT_QSFP_RECONFIGURE_PORT_PHY_LINK_UP_OFST 4
9270 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_LEN 4
9271 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_OFST 0
9272 #define MC_CMD_MUM_OUT_QSFP_GET_SUPPORTED_CAP_PORT_PHY_LP_CAP_LEN 4
9278 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_LEN(num) (4+1*(num))
9279 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1)
9281 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_OFST 0
9282 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATALEN_LEN 4
9283 #define MC_CMD_MUM_OUT_QSFP_GET_MEDIA_INFO_DATA_OFST 4
9291 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_OFST 0
9292 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PMA_PMD_LINK_UP_LEN 4
9293 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_OFST 4
9294 #define MC_CMD_MUM_OUT_QSFP_FILL_STATS_PORT_PHY_STATS_PCS_LINK_UP_LEN 4
9297 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_LEN 4
9298 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_OFST 0
9299 #define MC_CMD_MUM_OUT_QSFP_POLL_BIST_TEST_LEN 4
9306 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_NUM(len) (((len)-8)/8)
9308 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_OFST 0
9309 #define MC_CMD_MUM_OUT_READ_DDR_INFO_DISCRETE_DDR_INFO_LEN 4
9310 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_OFST 0
9311 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VRATIO_LBN 0
9313 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RESERVED1_OFST 0
9317 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_OFST 4
9318 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_RECORDS_LEN 4
9323 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_LO_LEN 4
9327 #define MC_CMD_MUM_OUT_READ_DDR_INFO_SODIMM_INFO_RECORD_HI_LEN 4
9334 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK_ID_LBN 0
9337 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK1 0x0
9339 #define MC_CMD_MUM_OUT_READ_DDR_INFO_BANK2 0x1
9341 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NUM_BANKS 0x2
9347 #define MC_CMD_MUM_OUT_READ_DDR_INFO_RANK_WIDTH 4
9350 #define MC_CMD_MUM_OUT_READ_DDR_INFO_VOLTAGE_WIDTH 4
9351 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_POWERED 0x0 /* enum */
9352 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V25 0x1 /* enum */
9353 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V35 0x2 /* enum */
9354 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V5 0x3 /* enum */
9355 /* enum: Values 5-15 are reserved for future usage */
9356 #define MC_CMD_MUM_OUT_READ_DDR_INFO_1V8 0x4
9365 #define MC_CMD_MUM_OUT_READ_DDR_INFO_STATE_WIDTH 4
9367 #define MC_CMD_MUM_OUT_READ_DDR_INFO_ABSENT 0x0
9369 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_POWERED 0x1
9371 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_TYPE 0x2
9373 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_VOLTAGE 0x3
9375 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SPD 0x4
9377 #define MC_CMD_MUM_OUT_READ_DDR_INFO_PRESENT_BAD_SLOT 0x5
9380 #define MC_CMD_MUM_OUT_READ_DDR_INFO_NOT_REACHABLE 0x6
9390 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 0
9391 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 4
9392 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 0
9395 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 4
9396 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 4
9401 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 4
9406 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 4
9411 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 4
9416 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 4
9428 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 0
9429 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 4
9430 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 0
9432 /* A human-readable name for the sensor (zero terminated string, max 32 bytes)
9434 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 4
9442 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 4
9444 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x0
9446 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x1
9448 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x2
9450 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x3
9452 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x4
9467 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 0
9468 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 4
9469 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 0
9472 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 4
9473 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 4
9478 #define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 4
9480 #define MC_CMD_DYNAMIC_SENSORS_READING_OK 0x0
9482 #define MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x1
9484 #define MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x2
9486 #define MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x3
9488 #define MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x4
9490 #define MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x5
9492 #define MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x6
9502 * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors
9525 #define MC_CMD_DYNAMIC_SENSORS_LIST 0x66
9531 #define MC_CMD_DYNAMIC_SENSORS_LIST_IN_LEN 0
9537 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num))
9538 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4)
9542 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 0
9543 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 4
9547 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 4
9548 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 4
9551 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 4
9552 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 0
9570 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67
9576 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMIN 0
9579 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))
9580 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)
9582 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_OFST 0
9583 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 4
9584 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MINNUM 0
9589 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMIN 0
9592 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LEN(num) (0+64*(num))
9593 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)
9595 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_OFST 0
9597 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MINNUM 0
9619 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68
9625 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMIN 0
9628 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))
9629 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)
9631 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_OFST 0
9632 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 4
9633 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MINNUM 0
9638 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMIN 0
9641 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LEN(num) (0+12*(num))
9642 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)
9644 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_OFST 0
9646 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MINNUM 0
9656 #define MC_CMD_EVENT_CTRL 0x69
9662 #define MC_CMD_EVENT_CTRL_IN_LENMIN 0
9665 #define MC_CMD_EVENT_CTRL_IN_LEN(num) (0+4*(num))
9666 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_NUM(len) (((len)-0)/4)
9668 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_OFST 0
9669 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_LEN 4
9670 #define MC_CMD_EVENT_CTRL_IN_EVENT_TYPE_MINNUM 0
9674 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_LINKCHANGE 0x0
9677 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_SENSOREVT 0x1
9679 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_RX_ERR 0x2
9681 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_TX_ERR 0x3
9683 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_FWALERT 0x4
9685 #define MC_CMD_EVENT_CTRL_IN_MCDI_EVENT_CODE_MC_REBOOT 0x5
9688 #define MC_CMD_EVENT_CTRL_OUT_LEN 0
9691 #define EVB_PORT_ID_LEN 4
9692 #define EVB_PORT_ID_PORT_ID_OFST 0
9693 #define EVB_PORT_ID_PORT_ID_LEN 4
9695 #define EVB_PORT_ID_NULL 0x0
9697 #define EVB_PORT_ID_ASSIGNED 0x1000000
9698 /* enum: External network port 0 */
9699 #define EVB_PORT_ID_MAC0 0x2000000
9701 #define EVB_PORT_ID_MAC1 0x2000001
9703 #define EVB_PORT_ID_MAC2 0x2000002
9705 #define EVB_PORT_ID_MAC3 0x2000003
9706 #define EVB_PORT_ID_PORT_ID_LBN 0
9712 #define EVB_VLAN_TAG_VLAN_ID_LBN 0
9715 #define EVB_VLAN_TAG_MODE_WIDTH 4
9717 #define EVB_VLAN_TAG_INSERT 0x0
9719 #define EVB_VLAN_TAG_REPLACE 0x1
9724 #define BUFTBL_ENTRY_OID_OFST 0
9726 #define BUFTBL_ENTRY_OID_LBN 0
9733 /* the raw 64-bit address field from the SMC, not adjusted for page size */
9734 #define BUFTBL_ENTRY_RAWADDR_OFST 4
9736 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4
9737 #define BUFTBL_ENTRY_RAWADDR_LO_LEN 4
9741 #define BUFTBL_ENTRY_RAWADDR_HI_LEN 4
9749 #define NVRAM_PARTITION_TYPE_ID_OFST 0
9752 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
9755 #define NVRAM_PARTITION_TYPE_NMC_FIRMWARE 0x100
9757 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
9759 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
9761 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
9765 #define NVRAM_PARTITION_TYPE_FACTORY_CONFIG 0x400
9767 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
9771 #define NVRAM_PARTITION_TYPE_USER_CONFIG 0x500
9772 /* enum: Expansion ROM configuration data for port 0 */
9773 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
9775 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
9777 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
9779 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
9781 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
9782 /* enum: Non-volatile log output partition */
9783 #define NVRAM_PARTITION_TYPE_LOG 0x700
9784 /* enum: Non-volatile log output partition for NMC firmware (this is
9787 #define NVRAM_PARTITION_TYPE_NMC_LOG 0x700
9788 /* enum: Non-volatile log output of second core on dual-core device */
9789 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
9791 #define NVRAM_PARTITION_TYPE_DUMP 0x800
9793 #define NVRAM_PARTITION_TYPE_NMC_CRASH_LOG 0x801
9795 #define NVRAM_PARTITION_TYPE_LICENSE 0x900
9797 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
9799 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
9801 #define NVRAM_PARTITION_TYPE_FPGA 0xb00
9803 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
9805 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
9807 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
9808 /* enum: Non-volatile log output partition for FC */
9809 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
9811 #define NVRAM_PARTITION_TYPE_FPGA_STAGE1 0xb05
9813 #define NVRAM_PARTITION_TYPE_FPGA_STAGE2 0xb06
9814 /* enum: FPGA User XCLBIN / Programmable Region 0 bitstream */
9815 #define NVRAM_PARTITION_TYPE_FPGA_REGION0 0xb07
9817 #define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_USER 0xb07
9821 #define NVRAM_PARTITION_TYPE_FPGA_JUMP 0xb08
9823 #define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_VALIDATE 0xb09
9825 #define NVRAM_PARTITION_TYPE_FPGA_XOCL_CONFIG 0xb0a
9827 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
9831 #define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
9832 /* enum: MUM Non-volatile log output partition. */
9833 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
9834 /* enum: SUC Non-volatile log output partition (this is intentionally an alias
9837 #define NVRAM_PARTITION_TYPE_SUC_LOG 0xc01
9839 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
9841 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
9843 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
9845 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
9847 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
9849 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
9851 #define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
9852 /* enum: Non-volatile log output partition for Expansion ROM (this is
9855 #define NVRAM_PARTITION_TYPE_EXPROM_LOG 0x1000
9857 #define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
9859 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200
9863 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
9867 #define NVRAM_PARTITION_TYPE_DEPLOYMENT_CONFIG 0x1300
9868 /* enum: Spare partition 4 */
9869 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
9871 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500
9875 #define NVRAM_PARTITION_TYPE_STATUS 0x1600
9877 #define NVRAM_PARTITION_TYPE_SPARE_13 0x1700
9879 #define NVRAM_PARTITION_TYPE_SPARE_14 0x1800
9881 #define NVRAM_PARTITION_TYPE_SPARE_15 0x1900
9883 #define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
9885 #define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
9887 #define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
9889 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a
9892 #define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00
9894 #define NVRAM_PARTITION_TYPE_BUNDLE 0x1e00
9898 #define NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e01
9899 /* enum: Bundle update non-volatile log output partition */
9900 #define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
9902 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03
9904 #define NVRAM_PARTITION_TYPE_BUNDLE_SIGNATURE 0x1e04
9906 #define NVRAM_PARTITION_TYPE_SUC_TEST 0x1f00
9908 #define NVRAM_PARTITION_TYPE_SUC_FPGA_PRIMARY 0x1f01
9910 #define NVRAM_PARTITION_TYPE_SUC_FPGA_SECONDARY 0x1f02
9911 /* enum: System microcontroller access to primary System-on-Chip flash */
9912 #define NVRAM_PARTITION_TYPE_SUC_SOC_PRIMARY 0x1f03
9913 /* enum: System microcontroller access to secondary System-on-Chip flash (if
9916 #define NVRAM_PARTITION_TYPE_SUC_SOC_SECONDARY 0x1f04
9921 #define NVRAM_PARTITION_TYPE_SUC_FAILURE_LOG 0x1f05
9922 /* enum: System-on-Chip configuration information (see XN-200467-PS). */
9923 #define NVRAM_PARTITION_TYPE_SUC_SOC_CONFIG 0x1f07
9924 /* enum: System-on-Chip update information. */
9925 #define NVRAM_PARTITION_TYPE_SOC_UPDATE 0x2003
9927 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
9929 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
9931 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
9932 /* enum: Recovery Flash Partition Table, see SF-122606-TC. (this is
9935 #define NVRAM_PARTITION_TYPE_RECOVERY_FPT 0xfffe
9937 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
9938 /* enum: Flash Partition Table, see SF-122606-TC. (this is intentionally an
9941 #define NVRAM_PARTITION_TYPE_FPT 0xffff
9942 #define NVRAM_PARTITION_TYPE_ID_LBN 0
9946 #define LICENSED_APP_ID_LEN 4
9947 #define LICENSED_APP_ID_ID_OFST 0
9948 #define LICENSED_APP_ID_ID_LEN 4
9950 #define LICENSED_APP_ID_ONLOAD 0x1
9952 #define LICENSED_APP_ID_PTP 0x2
9954 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
9956 #define LICENSED_APP_ID_SOLARSECURE 0x8
9958 #define LICENSED_APP_ID_PERF_MONITOR 0x10
9960 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
9962 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
9964 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
9966 #define LICENSED_APP_ID_TCP_DIRECT 0x100
9968 #define LICENSED_APP_ID_LOW_LATENCY 0x200
9970 #define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
9972 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800
9974 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
9976 #define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000
9978 #define LICENSED_APP_ID_DSHBRD 0x4000
9980 #define LICENSED_APP_ID_SCATRD 0x8000
9981 #define LICENSED_APP_ID_ID_LBN 0
9987 #define LICENSED_FEATURES_MASK_OFST 0
9989 #define LICENSED_FEATURES_MASK_LO_OFST 0
9990 #define LICENSED_FEATURES_MASK_LO_LEN 4
9991 #define LICENSED_FEATURES_MASK_LO_LBN 0
9993 #define LICENSED_FEATURES_MASK_HI_OFST 4
9994 #define LICENSED_FEATURES_MASK_HI_LEN 4
9997 #define LICENSED_FEATURES_RX_CUT_THROUGH_OFST 0
9998 #define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0
10000 #define LICENSED_FEATURES_PIO_OFST 0
10003 #define LICENSED_FEATURES_EVQ_TIMER_OFST 0
10006 #define LICENSED_FEATURES_CLOCK_OFST 0
10009 #define LICENSED_FEATURES_RX_TIMESTAMPS_OFST 0
10010 #define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4
10012 #define LICENSED_FEATURES_TX_TIMESTAMPS_OFST 0
10015 #define LICENSED_FEATURES_RX_SNIFF_OFST 0
10018 #define LICENSED_FEATURES_TX_SNIFF_OFST 0
10021 #define LICENSED_FEATURES_PROXY_FILTER_OPS_OFST 0
10024 #define LICENSED_FEATURES_EVENT_CUT_THROUGH_OFST 0
10027 #define LICENSED_FEATURES_MASK_LBN 0
10033 #define LICENSED_V3_APPS_MASK_OFST 0
10035 #define LICENSED_V3_APPS_MASK_LO_OFST 0
10036 #define LICENSED_V3_APPS_MASK_LO_LEN 4
10037 #define LICENSED_V3_APPS_MASK_LO_LBN 0
10039 #define LICENSED_V3_APPS_MASK_HI_OFST 4
10040 #define LICENSED_V3_APPS_MASK_HI_LEN 4
10043 #define LICENSED_V3_APPS_ONLOAD_OFST 0
10044 #define LICENSED_V3_APPS_ONLOAD_LBN 0
10046 #define LICENSED_V3_APPS_PTP_OFST 0
10049 #define LICENSED_V3_APPS_SOLARCAPTURE_PRO_OFST 0
10052 #define LICENSED_V3_APPS_SOLARSECURE_OFST 0
10055 #define LICENSED_V3_APPS_PERF_MONITOR_OFST 0
10056 #define LICENSED_V3_APPS_PERF_MONITOR_LBN 4
10058 #define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_OFST 0
10061 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_OFST 0
10064 #define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_OFST 0
10067 #define LICENSED_V3_APPS_TCP_DIRECT_OFST 0
10070 #define LICENSED_V3_APPS_LOW_LATENCY_OFST 0
10073 #define LICENSED_V3_APPS_SOLARCAPTURE_TAP_OFST 0
10076 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_40G_OFST 0
10079 #define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_1G_OFST 0
10082 #define LICENSED_V3_APPS_SCALEOUT_ONLOAD_OFST 0
10085 #define LICENSED_V3_APPS_DSHBRD_OFST 0
10088 #define LICENSED_V3_APPS_SCATRD_OFST 0
10091 #define LICENSED_V3_APPS_MASK_LBN 0
10097 #define LICENSED_V3_FEATURES_MASK_OFST 0
10099 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0
10100 #define LICENSED_V3_FEATURES_MASK_LO_LEN 4
10101 #define LICENSED_V3_FEATURES_MASK_LO_LBN 0
10103 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4
10104 #define LICENSED_V3_FEATURES_MASK_HI_LEN 4
10107 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0
10108 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
10110 #define LICENSED_V3_FEATURES_PIO_OFST 0
10113 #define LICENSED_V3_FEATURES_EVQ_TIMER_OFST 0
10116 #define LICENSED_V3_FEATURES_CLOCK_OFST 0
10119 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_OFST 0
10120 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
10122 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_OFST 0
10125 #define LICENSED_V3_FEATURES_RX_SNIFF_OFST 0
10128 #define LICENSED_V3_FEATURES_TX_SNIFF_OFST 0
10131 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_OFST 0
10134 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_OFST 0
10137 #define LICENSED_V3_FEATURES_MASK_LBN 0
10143 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0
10145 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0
10152 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
10156 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11
10160 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12
10164 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13
10166 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
10168 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
10172 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4
10179 /* The RSS mode for a particular packet type is a value from 0 - 15 which can
10180 * be considered as 4 bits selecting which fields are included in the hash. (A
10181 * value 0 effectively disables RSS spreading for the packet type.) The YAML
10183 * but only 4 bits are relevant.
10185 #define RSS_MODE_HASH_SELECTOR_OFST 0
10187 #define RSS_MODE_HASH_SRC_ADDR_OFST 0
10188 #define RSS_MODE_HASH_SRC_ADDR_LBN 0
10190 #define RSS_MODE_HASH_DST_ADDR_OFST 0
10193 #define RSS_MODE_HASH_SRC_PORT_OFST 0
10196 #define RSS_MODE_HASH_DST_PORT_OFST 0
10199 #define RSS_MODE_HASH_SELECTOR_LBN 0
10203 #define CTPIO_STATS_MAP_LEN 4
10205 #define CTPIO_STATS_MAP_VI_OFST 0
10207 #define CTPIO_STATS_MAP_VI_LBN 0
10220 #define MC_CMD_READ_REGS 0x50
10226 #define MC_CMD_READ_REGS_IN_LEN 0
10231 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0
10233 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,
10237 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4
10244 * end with an address for each 4k of host memory required to back the EVQ.
10246 #define MC_CMD_INIT_EVQ 0x80
10256 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
10258 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
10259 #define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
10261 * local queue index. The calling client must be the currently-assigned user of
10264 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
10265 #define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
10269 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4
10270 /* The reload value is ignored in one-shot modes */
10272 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4
10275 #define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4
10277 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
10289 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
10298 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4
10300 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
10302 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
10304 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
10305 /* enum: Hold-off */
10306 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
10309 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4
10315 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4
10318 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4
10320 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
10322 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
10324 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
10326 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
10329 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4
10330 /* 64-bit address of 4k of 4k-aligned host memory buffer */
10334 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LEN 4
10338 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LEN 4
10346 #define MC_CMD_INIT_EVQ_OUT_LEN 4
10348 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
10349 #define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4
10356 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
10358 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
10359 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
10361 * local queue index. The calling client must be the currently-assigned user of
10364 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
10365 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
10369 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4
10370 /* The reload value is ignored in one-shot modes */
10372 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4
10375 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4
10377 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
10389 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
10399 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
10401 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0
10403 * over-ridden by firmware based on licenses and firmware variant in order to
10407 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1
10409 * over-ridden by firmware based on licenses and firmware variant in order to
10413 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2
10414 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
10418 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
10423 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4
10425 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0
10427 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1
10429 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2
10430 /* enum: Hold-off */
10431 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3
10434 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4
10440 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4
10443 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4
10445 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0
10447 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1
10449 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2
10451 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3
10454 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4
10455 /* 64-bit address of 4k of 4k-aligned host memory buffer */
10459 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LEN 4
10463 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LEN 4
10473 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0
10474 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4
10476 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
10477 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4
10478 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_OFST 4
10479 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
10481 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_OFST 4
10484 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_OFST 4
10487 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
10491 /* MC_CMD_INIT_EVQ_V3_IN msgrequest: Extended request to specify per-queue
10496 #define MC_CMD_INIT_EVQ_V3_IN_SIZE_OFST 0
10497 #define MC_CMD_INIT_EVQ_V3_IN_SIZE_LEN 4
10499 * local queue index. The calling client must be the currently-assigned user of
10502 #define MC_CMD_INIT_EVQ_V3_IN_INSTANCE_OFST 4
10503 #define MC_CMD_INIT_EVQ_V3_IN_INSTANCE_LEN 4
10507 #define MC_CMD_INIT_EVQ_V3_IN_TMR_LOAD_LEN 4
10508 /* The reload value is ignored in one-shot modes */
10510 #define MC_CMD_INIT_EVQ_V3_IN_TMR_RELOAD_LEN 4
10513 #define MC_CMD_INIT_EVQ_V3_IN_FLAGS_LEN 4
10515 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_INTERRUPTING_LBN 0
10527 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_RX_MERGE_LBN 4
10537 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_WIDTH 4
10539 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_MANUAL 0x0
10541 * over-ridden by firmware based on licenses and firmware variant in order to
10545 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_LOW_LATENCY 0x1
10547 * over-ridden by firmware based on licenses and firmware variant in order to
10551 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_THROUGHPUT 0x2
10552 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
10556 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_AUTO 0x3
10561 #define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_LEN 4
10563 #define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_DIS 0x0
10565 #define MC_CMD_INIT_EVQ_V3_IN_TMR_IMMED_START 0x1
10567 #define MC_CMD_INIT_EVQ_V3_IN_TMR_TRIG_START 0x2
10568 /* enum: Hold-off */
10569 #define MC_CMD_INIT_EVQ_V3_IN_TMR_INT_HLDOFF 0x3
10572 #define MC_CMD_INIT_EVQ_V3_IN_TARGET_EVQ_LEN 4
10578 #define MC_CMD_INIT_EVQ_V3_IN_IRQ_NUM_LEN 4
10581 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_LEN 4
10583 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_DIS 0x0
10585 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_RX 0x1
10587 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_TX 0x2
10589 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_RXTX 0x3
10592 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_THRSHLD_LEN 4
10593 /* 64-bit address of 4k of 4k-aligned host memory buffer */
10597 #define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_LEN 4
10601 #define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_LEN 4
10608 * and granularity are device specific. Specify 0 to use the firmware's default
10609 * value. This field is ignored and per-queue merging is disabled if
10613 #define MC_CMD_INIT_EVQ_V3_IN_RX_MERGE_TIMEOUT_NS_LEN 4
10615 * and granularity are device specific. Specify 0 to use the firmware's default
10616 * value. This field is ignored and per-queue merging is disabled if
10620 #define MC_CMD_INIT_EVQ_V3_IN_TX_MERGE_TIMEOUT_NS_LEN 4
10625 #define MC_CMD_INIT_EVQ_V3_OUT_IRQ_OFST 0
10626 #define MC_CMD_INIT_EVQ_V3_OUT_IRQ_LEN 4
10628 #define MC_CMD_INIT_EVQ_V3_OUT_FLAGS_OFST 4
10629 #define MC_CMD_INIT_EVQ_V3_OUT_FLAGS_LEN 4
10630 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_OFST 4
10631 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_LBN 0
10633 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_OFST 4
10636 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_TX_MERGE_OFST 4
10639 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
10645 #define QUEUE_CRC_MODE_MODE_LBN 0
10646 #define QUEUE_CRC_MODE_MODE_WIDTH 4
10648 #define QUEUE_CRC_MODE_NONE 0x0
10650 #define QUEUE_CRC_MODE_FCOE 0x1
10652 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2
10654 #define QUEUE_CRC_MODE_ISCSI 0x3
10656 #define QUEUE_CRC_MODE_FCOIPOE 0x4
10658 #define QUEUE_CRC_MODE_MPA 0x5
10659 #define QUEUE_CRC_MODE_SPARE_LBN 4
10660 #define QUEUE_CRC_MODE_SPARE_WIDTH 4
10666 * arguments end with an address for each 4k of host memory required to back
10669 #define MC_CMD_INIT_RXQ 0x81
10681 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
10683 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
10684 #define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4
10687 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
10688 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4
10691 #define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
10693 * local queue index. The calling client must be the currently-assigned user of
10697 #define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
10700 #define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4
10702 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
10712 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
10727 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4
10728 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
10730 #define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4
10731 /* 64-bit address of 4k of 4k-aligned host memory buffer */
10735 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LEN 4
10739 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LEN 4
10751 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
10752 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4
10756 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
10757 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4
10763 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
10765 * local queue index. The calling client must be the currently-assigned user of
10769 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
10772 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4
10774 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
10784 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
10796 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
10798 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
10800 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
10803 * multiple fixed-size packet buffers within each bucket. For a full
10804 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
10807 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
10809 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
10816 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
10817 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
10818 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
10819 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
10820 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
10832 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
10833 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
10835 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4
10836 /* 64-bit address of 4k of 4k-aligned host memory buffer */
10840 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LEN 4
10844 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LEN 4
10847 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_MINNUM 0
10852 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4
10857 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0
10858 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4
10862 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4
10863 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4
10869 #define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
10871 * local queue index. The calling client must be the currently-assigned user of
10875 #define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
10878 #define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4
10880 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0
10890 #define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4
10902 #define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4
10904 #define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0
10906 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1
10909 * multiple fixed-size packet buffers within each bucket. For a full
10910 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
10913 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
10915 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
10922 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
10923 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
10924 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
10925 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
10926 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
10938 #define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
10939 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
10941 #define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4
10942 /* 64-bit address of 4k of 4k-aligned host memory buffer */
10946 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LEN 4
10950 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LEN 4
10953 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_MINNUM 0
10958 #define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4
10964 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
10971 #define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4
10977 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4
10980 * are still no descriptors then the packet will be dropped. A timeout of 0
10985 #define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
10992 #define MC_CMD_INIT_RXQ_V4_IN_SIZE_OFST 0
10993 #define MC_CMD_INIT_RXQ_V4_IN_SIZE_LEN 4
10997 #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_OFST 4
10998 #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_LEN 4
11004 #define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4
11006 * local queue index. The calling client must be the currently-assigned user of
11010 #define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4
11013 #define MC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 4
11015 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_LBN 0
11025 #define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 4
11037 #define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 4
11039 #define MC_CMD_INIT_RXQ_V4_IN_SINGLE_PACKET 0x0
11041 #define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM 0x1
11044 * multiple fixed-size packet buffers within each bucket. For a full
11045 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11048 #define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11050 #define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11057 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_1M 0x0 /* enum */
11058 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_512K 0x1 /* enum */
11059 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_256K 0x2 /* enum */
11060 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_128K 0x3 /* enum */
11061 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_64K 0x4 /* enum */
11073 #define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4
11074 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
11076 #define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_LEN 4
11077 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11081 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LEN 4
11085 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LEN 4
11088 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_MINNUM 0
11093 #define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_LEN 4
11099 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
11106 #define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_LEN 4
11112 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_LEN 4
11115 * are still no descriptors then the packet will be dropped. A timeout of 0
11120 #define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
11123 #define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_LEN 4
11125 * to zero if using this message on non-QDMA based platforms. Currently in
11127 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
11133 #define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 4
11140 #define MC_CMD_INIT_RXQ_V5_IN_SIZE_OFST 0
11141 #define MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 4
11145 #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 4
11146 #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 4
11152 #define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4
11154 * local queue index. The calling client must be the currently-assigned user of
11158 #define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4
11161 #define MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 4
11163 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 0
11173 #define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 4
11185 #define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 4
11187 #define MC_CMD_INIT_RXQ_V5_IN_SINGLE_PACKET 0x0
11189 #define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM 0x1
11192 * multiple fixed-size packet buffers within each bucket. For a full
11193 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11196 #define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11198 #define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11205 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */
11206 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_512K 0x1 /* enum */
11207 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */
11208 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */
11209 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */
11221 #define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4
11222 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
11224 #define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 4
11225 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11229 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LEN 4
11233 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LEN 4
11236 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_MINNUM 0
11241 #define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 4
11247 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
11254 #define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 4
11260 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 4
11263 * are still no descriptors then the packet will be dropped. A timeout of 0
11268 #define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
11271 #define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 4
11273 * to zero if using this message on non-QDMA based platforms. Currently in
11275 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
11281 #define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 4
11288 #define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 4
11291 #define MC_CMD_INIT_RXQ_OUT_LEN 0
11294 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
11297 #define MC_CMD_INIT_RXQ_V3_OUT_LEN 0
11300 #define MC_CMD_INIT_RXQ_V4_OUT_LEN 0
11303 #define MC_CMD_INIT_RXQ_V5_OUT_LEN 0
11309 #define MC_CMD_INIT_TXQ 0x82
11321 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
11323 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
11324 #define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4
11328 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
11329 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4
11332 #define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
11334 * local queue index. The calling client must be the currently-assigned user of
11338 #define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
11341 #define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4
11343 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
11355 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
11356 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
11371 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4
11372 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
11374 #define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4
11375 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11379 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LEN 4
11383 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LEN 4
11395 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0
11396 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4
11400 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4
11401 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4
11404 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
11406 * local queue index. The calling client must be the currently-assigned user of
11410 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
11413 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4
11415 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
11427 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
11428 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
11461 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4
11462 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
11464 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4
11465 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11469 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LEN 4
11473 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LEN 4
11476 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 0
11481 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4
11483 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
11490 #define MC_CMD_INIT_TXQ_OUT_LEN 0
11500 #define MC_CMD_FINI_EVQ 0x83
11506 #define MC_CMD_FINI_EVQ_IN_LEN 4
11510 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
11511 #define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4
11514 #define MC_CMD_FINI_EVQ_OUT_LEN 0
11521 #define MC_CMD_FINI_RXQ 0x84
11527 #define MC_CMD_FINI_RXQ_IN_LEN 4
11529 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
11530 #define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4
11533 #define MC_CMD_FINI_RXQ_OUT_LEN 0
11540 #define MC_CMD_FINI_TXQ 0x85
11546 #define MC_CMD_FINI_TXQ_IN_LEN 4
11548 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
11549 #define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4
11552 #define MC_CMD_FINI_TXQ_OUT_LEN 0
11559 #define MC_CMD_DRIVER_EVENT 0x86
11567 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
11568 #define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4
11569 /* Bits 0 - 63 of event */
11570 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
11572 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
11573 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LEN 4
11577 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LEN 4
11582 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0
11592 #define MC_CMD_PROXY_CMD 0x5b
11598 #define MC_CMD_PROXY_CMD_IN_LEN 4
11600 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
11601 #define MC_CMD_PROXY_CMD_IN_TARGET_LEN 4
11602 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_OFST 0
11603 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0
11605 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_OFST 0
11608 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
11611 #define MC_CMD_PROXY_CMD_OUT_LEN 0
11618 #define MC_PROXY_STATUS_BUFFER_HANDLE_OFST 0
11619 #define MC_PROXY_STATUS_BUFFER_HANDLE_LEN 4
11621 #define MC_PROXY_STATUS_BUFFER_HANDLE_INVALID 0x0
11622 #define MC_PROXY_STATUS_BUFFER_HANDLE_LBN 0
11625 #define MC_PROXY_STATUS_BUFFER_PF_OFST 4
11650 #define MC_PROXY_STATUS_BUFFER_GRANTED_PRIVILEGES_LEN 4
11660 #define MC_CMD_PROXY_CONFIGURE 0x58
11667 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_OFST 0
11668 #define MC_CMD_PROXY_CONFIGURE_IN_FLAGS_LEN 4
11669 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_OFST 0
11670 #define MC_CMD_PROXY_CONFIGURE_IN_ENABLE_LBN 0
11675 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_OFST 4
11677 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_OFST 4
11678 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_LO_LEN 4
11682 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BUFF_ADDR_HI_LEN 4
11687 #define MC_CMD_PROXY_CONFIGURE_IN_STATUS_BLOCK_SIZE_LEN 4
11694 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_LO_LEN 4
11698 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BUFF_ADDR_HI_LEN 4
11703 #define MC_CMD_PROXY_CONFIGURE_IN_REQUEST_BLOCK_SIZE_LEN 4
11711 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_LO_LEN 4
11715 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BUFF_ADDR_HI_LEN 4
11720 #define MC_CMD_PROXY_CONFIGURE_IN_REPLY_BLOCK_SIZE_LEN 4
11723 #define MC_CMD_PROXY_CONFIGURE_IN_NUM_BLOCKS_LEN 4
11730 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_OFST 0
11731 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_FLAGS_LEN 4
11732 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_OFST 0
11733 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_ENABLE_LBN 0
11738 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_OFST 4
11740 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_OFST 4
11741 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_LO_LEN 4
11745 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BUFF_ADDR_HI_LEN 4
11750 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_STATUS_BLOCK_SIZE_LEN 4
11757 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_LO_LEN 4
11761 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BUFF_ADDR_HI_LEN 4
11766 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REQUEST_BLOCK_SIZE_LEN 4
11774 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_LO_LEN 4
11778 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BUFF_ADDR_HI_LEN 4
11783 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_REPLY_BLOCK_SIZE_LEN 4
11786 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_NUM_BLOCKS_LEN 4
11791 #define MC_CMD_PROXY_CONFIGURE_EXT_IN_RESERVED_LEN 4
11794 #define MC_CMD_PROXY_CONFIGURE_OUT_LEN 0
11804 #define MC_CMD_PROXY_COMPLETE 0x5f
11811 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_OFST 0
11812 #define MC_CMD_PROXY_COMPLETE_IN_BLOCK_INDEX_LEN 4
11813 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_OFST 4
11814 #define MC_CMD_PROXY_COMPLETE_IN_STATUS_LEN 4
11818 #define MC_CMD_PROXY_COMPLETE_IN_COMPLETE 0x0
11822 #define MC_CMD_PROXY_COMPLETE_IN_AUTHORIZED 0x1
11824 #define MC_CMD_PROXY_COMPLETE_IN_DECLINED 0x2
11828 #define MC_CMD_PROXY_COMPLETE_IN_TIMEDOUT 0x3
11830 #define MC_CMD_PROXY_COMPLETE_IN_HANDLE_LEN 4
11833 #define MC_CMD_PROXY_COMPLETE_OUT_LEN 0
11842 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
11850 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
11851 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_LEN 4
11855 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
11856 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_LEN 4
11860 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
11861 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_LEN 4
11862 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
11863 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_LEN 4
11866 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_LEN 4
11873 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
11883 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_NUM(len) (((len)-12)/8)
11884 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
11885 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_LEN 4
11887 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
11888 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
11891 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
11896 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_LEN 4
11900 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_LEN 4
11908 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
11914 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89
11920 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
11921 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
11922 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_LEN 4
11925 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
11932 #define MC_CMD_FILTER_OP 0x8a
11940 #define MC_CMD_FILTER_OP_IN_OP_OFST 0
11941 #define MC_CMD_FILTER_OP_IN_OP_LEN 4
11942 /* enum: single-recipient filter insert */
11943 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
11944 /* enum: single-recipient filter remove */
11945 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
11946 /* enum: multi-recipient filter subscribe */
11947 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
11948 /* enum: multi-recipient filter unsubscribe */
11949 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
11950 /* enum: replace one recipient with another (warning - the filter handle may
11953 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
11955 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
11957 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
11958 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_LEN 4
11962 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_LEN 4
11965 /* The port ID associated with the v-adaptor which should contain this filter.
11968 #define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4
11971 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4
11973 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
11985 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
12019 #define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4
12021 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
12023 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
12025 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
12026 /* enum: loop back to TXDP 0 */
12027 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
12029 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
12032 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4
12035 #define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4
12037 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
12039 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
12041 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
12044 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12050 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4
12051 /* transmit domain (reserved; set to 0) */
12053 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4
12059 #define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4
12061 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
12063 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
12089 /* IP protocol to match (in low byte; set high byte to 0) */
12092 /* Firmware defined register 0 to match (reserved; set to 0) */
12094 #define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4
12095 /* Firmware defined register 1 to match (reserved; set to 0) */
12097 #define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4
12099 * 0 for IPv4 address)
12104 * bytes to 0 for IPv4 address)
12115 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0
12116 #define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4
12120 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
12122 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
12123 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LEN 4
12127 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LEN 4
12130 /* The port ID associated with the v-adaptor which should contain this filter.
12133 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4
12136 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4
12138 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
12150 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
12226 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4
12228 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
12230 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
12232 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
12233 /* enum: loop back to TXDP 0 */
12234 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
12236 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
12239 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4
12242 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4
12244 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
12246 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
12248 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
12251 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12257 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4
12258 /* transmit domain (reserved; set to 0) */
12260 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4
12266 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4
12268 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
12270 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
12296 /* IP protocol to match (in low byte; set high byte to 0) */
12299 /* Firmware defined register 0 to match (reserved; set to 0) */
12301 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4
12303 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
12307 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4
12309 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
12315 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
12317 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
12319 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
12321 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
12327 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
12329 * 0 for IPv4 address)
12334 * bytes to 0 for IPv4 address)
12369 * 0)
12373 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
12374 * to 0)
12377 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4
12379 * to 0)
12382 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4
12384 * order; set last 12 bytes to 0 for IPv4 address)
12389 * order; set last 12 bytes to 0 for IPv4 address)
12403 #define MC_CMD_FILTER_OP_V3_IN_OP_OFST 0
12404 #define MC_CMD_FILTER_OP_V3_IN_OP_LEN 4
12408 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
12410 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
12411 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LEN 4
12415 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LEN 4
12418 /* The port ID associated with the v-adaptor which should contain this filter.
12421 #define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4
12424 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4
12426 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0
12438 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4
12514 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4
12516 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0
12518 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1
12520 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2
12521 /* enum: loop back to TXDP 0 */
12522 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3
12524 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4
12527 #define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4
12530 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4
12532 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0
12534 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1
12536 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2
12539 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12545 #define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4
12546 /* transmit domain (reserved; set to 0) */
12548 #define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4
12554 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4
12556 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
12558 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0
12584 /* IP protocol to match (in low byte; set high byte to 0) */
12587 /* Firmware defined register 0 to match (reserved; set to 0) */
12589 #define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4
12591 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
12595 #define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4
12597 #define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0
12603 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0
12605 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
12607 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
12609 #define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0
12615 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0
12617 * 0 for IPv4 address)
12622 * bytes to 0 for IPv4 address)
12657 * 0)
12661 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
12662 * to 0)
12665 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4
12667 * to 0)
12670 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4
12672 * order; set last 12 bytes to 0 for IPv4 address)
12677 * order; set last 12 bytes to 0 for IPv4 address)
12684 * else user_flag = req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark
12685 * = 0; else if (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK
12692 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_LEN 4
12694 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_LBN 0
12706 #define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_LBN 4
12709 * functionality of this field in an ABI-backwards-compatible manner, and
12714 * Firmware Driver Interface (SF-119419-TC). Requesting anything other than
12719 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4
12721 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0
12726 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1
12731 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
12737 #define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
12742 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0
12743 #define MC_CMD_FILTER_OP_OUT_OP_LEN 4
12748 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
12750 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
12752 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
12753 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LEN 4
12757 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LEN 4
12761 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
12763 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
12768 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0
12769 #define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4
12774 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
12776 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
12778 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
12779 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LEN 4
12783 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LEN 4
12792 * Get information related to the parser-dispatcher subsystem
12794 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4
12800 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
12802 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
12803 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4
12805 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
12809 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
12810 /* enum: read properties relating to security rules (Medford-only; for use by
12811 * SolarSecure apps, not directly by drivers. See SF-114946-SW.)
12813 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
12818 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
12822 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5
12824 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_TYPES 0x6
12830 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
12831 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
12833 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
12834 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4
12838 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
12839 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4
12844 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
12845 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
12852 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0
12853 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4
12857 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4
12858 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4
12859 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 4
12860 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0
12872 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num))
12873 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
12875 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_OFST 0
12876 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 4
12880 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 4
12881 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 4
12886 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 4
12887 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MINNUM 0
12896 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_OP_OFST 0
12897 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_OP_LEN 4
12900 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
12901 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
12902 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_OFST 4
12903 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_LBN 0
12905 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_OFST 4
12908 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_GENEVE_OFST 4
12911 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_L2GRE_OFST 4
12918 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging.
12925 #define MC_CMD_PARSER_DISP_RW 0xe5
12933 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0
12934 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_LEN 4
12936 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0
12938 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1
12944 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2
12946 #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3
12948 #define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0
12950 #define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4
12952 #define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5
12954 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4
12955 #define MC_CMD_PARSER_DISP_RW_IN_OP_LEN 4
12957 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0
12961 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1
12962 /* enum: Read-modify-write a word of DICPU DMEM (not valid for LUE). Not
12965 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2
12968 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_LEN 4
12971 #define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_LEN 4
12973 #define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1
12976 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_LEN 4
12977 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */
12979 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_LEN 4
12980 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */
12982 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_LEN 4
12985 #define MC_CMD_PARSER_DISP_RW_IN_LUE_READ_METADATA_VERSION_LEN 4
12993 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0
12994 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_LEN 4
12996 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0
12998 /* up to 8 32-bit words of additional soft state from the LUE manager (the
12999 * exact content is firmware-dependent and intended only for debug use)
13004 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0
13005 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4
13006 #define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4
13007 #define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */
13008 #define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */
13015 #define MC_CMD_GET_PF_COUNT 0xb6
13021 #define MC_CMD_GET_PF_COUNT_IN_LEN 0
13026 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0
13034 #define MC_CMD_SET_PF_COUNT 0xb7
13037 #define MC_CMD_SET_PF_COUNT_IN_LEN 4
13039 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0
13040 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_LEN 4
13043 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0
13050 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
13056 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
13059 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
13063 * sense - e.g. virtio-blk), in which case the return value is NULL_PORT.
13065 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
13066 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4
13068 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_NULL_PORT 0xffffffff
13075 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
13081 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
13083 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
13084 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_LEN 4
13087 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
13094 #define MC_CMD_ALLOC_VIS 0x8b
13102 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
13103 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4
13105 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
13106 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4
13108 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.
13113 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
13114 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4
13118 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
13119 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4
13124 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0
13125 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4
13129 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4
13130 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4
13131 /* Function's port vi_shift value (always 0 on Huntington) */
13133 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4
13141 #define MC_CMD_FREE_VIS 0x8c
13147 #define MC_CMD_FREE_VIS_IN_LEN 0
13150 #define MC_CMD_FREE_VIS_OUT_LEN 0
13157 #define MC_CMD_GET_SRIOV_CFG 0xba
13163 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0
13168 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
13169 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4
13171 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
13172 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4
13174 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4
13176 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
13180 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4
13183 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4
13190 #define MC_CMD_SET_SRIOV_CFG 0xbb
13198 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
13199 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_LEN 4
13201 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
13202 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_LEN 4
13204 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_LEN 4
13206 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
13208 /* RID offset of first VF from PF, or 0 for no change, or
13212 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_LEN 4
13213 /* RID offset of each subsequent VF from the previous, 0 for no change, or
13217 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_LEN 4
13220 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
13229 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d
13235 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0
13240 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0
13241 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_LEN 4
13245 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4
13246 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_LEN 4
13247 /* Function's port vi_shift value (always 0 on Huntington) */
13249 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_SHIFT_LEN 4
13258 #define MC_CMD_DUMP_VI_STATE 0x8e
13264 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4
13266 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0
13267 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_LEN 4
13272 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
13278 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4
13293 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_LEN 4
13297 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_LEN 4
13304 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_LEN 4
13308 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_LEN 4
13313 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_LEN 4
13315 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0
13327 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_LEN 4
13331 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_LEN 4
13338 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_LEN 4
13342 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_LEN 4
13349 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_LEN 4
13353 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_LEN 4
13360 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_LEN 4
13364 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_LEN 4
13368 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
13386 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_LEN 4
13390 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_LEN 4
13397 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_LEN 4
13401 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_LEN 4
13404 /* Reserved, currently 0. */
13408 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_LEN 4
13412 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_LEN 4
13419 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_LEN 4
13423 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_LEN 4
13427 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
13440 #define MC_CMD_DUMP_VI_STATE_OUT_USER_CLIENT_ID_LEN 4
13447 #define MC_CMD_ALLOC_PIOBUF 0x8f
13453 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0
13456 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
13458 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
13459 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4
13466 #define MC_CMD_FREE_PIOBUF 0x90
13472 #define MC_CMD_FREE_PIOBUF_IN_LEN 4
13474 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
13475 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
13478 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0
13484 * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
13487 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
13493 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
13495 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
13496 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
13499 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4
13501 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0
13518 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0
13519 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_LEN 4
13525 * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
13528 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
13536 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
13537 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
13539 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4
13556 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4
13557 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_LEN 4
13560 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
13567 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
13573 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4
13574 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
13575 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
13577 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
13579 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
13581 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
13583 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3
13587 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0
13588 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_LEN 4
13592 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4
13593 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_LEN 4
13594 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_OFST 4
13595 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0
13597 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_OFST 4
13600 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_OFST 4
13601 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0
13603 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_OFST 4
13606 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_OFST 4
13609 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_OFST 4
13612 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_OFST 4
13613 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4
13615 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_OFST 4
13616 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0
13618 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_OFST 4
13621 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_OFST 4
13624 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_OFST 4
13627 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_OFST 4
13628 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0
13630 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_OFST 4
13633 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_OFST 4
13634 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4
13636 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_OFST 4
13639 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_OFST 4
13642 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_OFST 4
13651 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
13658 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
13659 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_LEN 4
13663 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4
13664 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_LEN 4
13665 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_OFST 4
13666 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0
13668 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_OFST 4
13669 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0
13671 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_OFST 4
13674 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_OFST 4
13677 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_OFST 4
13680 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_OFST 4
13681 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0
13683 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_OFST 4
13686 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_OFST 4
13689 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_OFST 4
13690 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0
13692 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_OFST 4
13695 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_OFST 4
13696 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4
13698 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_OFST 4
13701 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_OFST 4
13704 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_OFST 4
13709 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0
13716 #define MC_CMD_SATELLITE_DOWNLOAD 0x91
13724 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.
13726 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download
13728 * be a checksum (a simple 32-bit sum) of the transferred data. An individual
13731 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15),
13734 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.
13742 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))
13743 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_NUM(len) (((len)-16)/4)
13747 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0
13748 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_LEN 4
13749 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */
13750 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */
13751 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */
13752 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */
13753 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */
13757 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4
13758 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_LEN 4
13760 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0
13762 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1
13764 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2
13766 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3
13768 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4
13770 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5
13772 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6
13774 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7
13776 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8
13778 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9
13780 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa
13782 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb
13784 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc
13786 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd
13788 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe
13790 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf
13791 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */
13792 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff
13795 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LEN 4
13797 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff
13799 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe
13802 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_LEN 4
13805 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4
13812 /* Same as MC_CMD_ERR field, but included as 0 in success cases */
13813 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0
13814 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_LEN 4
13816 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4
13817 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_LEN 4
13819 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0
13821 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1
13823 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2
13825 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100
13827 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101
13829 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200
13831 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201
13833 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300
13843 #define MC_CMD_GET_CAPABILITIES 0xbe
13849 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0
13854 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
13855 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4
13856 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_OFST 0
13859 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_OFST 0
13860 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4
13862 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_OFST 0
13865 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
13868 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_OFST 0
13871 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_OFST 0
13874 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_OFST 0
13877 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
13880 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
13883 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
13886 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_OFST 0
13889 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_OFST 0
13892 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
13895 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_OFST 0
13898 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_OFST 0
13901 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_OFST 0
13904 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_OFST 0
13907 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_OFST 0
13910 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_OFST 0
13913 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_OFST 0
13916 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_OFST 0
13919 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_OFST 0
13922 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_OFST 0
13925 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_OFST 0
13928 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_OFST 0
13931 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_OFST 0
13934 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
13937 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_OFST 0
13940 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_OFST 0
13944 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
13947 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
13949 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
13951 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
13953 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
13955 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6
13957 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
13959 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
13961 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
13963 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
13964 /* enum: RXDP Test firmware image 4 */
13965 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
13967 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
13969 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
13971 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
13973 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
13975 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
13977 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c
13982 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
13984 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
13986 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
13988 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
13990 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6
13992 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
13994 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
13996 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
13998 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
14002 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
14006 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14007 /* enum: reserved value - do not use (may indicate alternative interpretation
14010 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
14014 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14017 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14018 /* enum: RX PD firmware with approximately Siena-compatible behaviour
14021 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14023 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14025 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14029 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14031 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14033 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14037 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14039 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14040 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14041 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14043 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa
14045 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14049 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14053 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
14057 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14058 /* enum: reserved value - do not use (may indicate alternative interpretation
14061 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
14065 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14068 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14069 /* enum: TX PD firmware with approximately Siena-compatible behaviour
14072 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14074 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14076 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14080 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14081 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14085 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14087 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14088 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14089 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14091 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa
14093 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14096 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4
14099 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4
14102 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0
14107 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0
14108 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4
14109 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_OFST 0
14112 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_OFST 0
14113 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4
14115 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_OFST 0
14118 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14121 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_OFST 0
14124 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14127 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_OFST 0
14130 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14133 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14136 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14139 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_OFST 0
14142 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_OFST 0
14145 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14148 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_OFST 0
14151 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_OFST 0
14154 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_OFST 0
14157 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_OFST 0
14160 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_OFST 0
14163 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_OFST 0
14166 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_OFST 0
14169 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_OFST 0
14172 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_OFST 0
14175 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_OFST 0
14178 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_OFST 0
14181 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14184 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_OFST 0
14187 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14190 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_OFST 0
14193 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_OFST 0
14197 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4
14200 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
14202 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
14204 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
14206 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
14208 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6
14210 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
14212 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14214 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14216 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14217 /* enum: RXDP Test firmware image 4 */
14218 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14220 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
14222 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14224 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14226 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14228 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14230 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c
14235 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
14237 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
14239 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
14241 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
14243 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6
14245 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
14247 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14249 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14251 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
14255 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
14259 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14260 /* enum: reserved value - do not use (may indicate alternative interpretation
14263 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
14267 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14270 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14271 /* enum: RX PD firmware with approximately Siena-compatible behaviour
14274 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14276 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14278 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14282 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14284 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14286 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14290 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14292 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14293 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14294 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14296 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa
14298 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14302 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14306 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
14310 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14311 /* enum: reserved value - do not use (may indicate alternative interpretation
14314 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
14318 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14321 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14322 /* enum: TX PD firmware with approximately Siena-compatible behaviour
14325 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14327 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14329 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14333 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14334 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14338 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14340 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14341 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14342 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14344 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa
14346 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14349 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4
14352 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4
14355 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4
14357 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0
14369 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4
14471 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
14473 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
14475 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
14482 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14490 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
14492 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
14496 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
14517 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0
14518 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4
14519 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_OFST 0
14522 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_OFST 0
14523 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4
14525 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_OFST 0
14528 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14531 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_OFST 0
14534 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14537 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_OFST 0
14540 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14543 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14546 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14549 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_OFST 0
14552 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_OFST 0
14555 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14558 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_OFST 0
14561 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_OFST 0
14564 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_OFST 0
14567 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_OFST 0
14570 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_OFST 0
14573 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_OFST 0
14576 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_OFST 0
14579 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_OFST 0
14582 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_OFST 0
14585 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_OFST 0
14588 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_OFST 0
14591 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14594 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_OFST 0
14597 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14600 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_OFST 0
14603 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_OFST 0
14607 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4
14610 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0
14612 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1
14614 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
14616 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
14618 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6
14620 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
14622 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14624 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14626 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14627 /* enum: RXDP Test firmware image 4 */
14628 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14630 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105
14632 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14634 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14636 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14638 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14640 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c
14645 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0
14647 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1
14649 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
14651 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
14653 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6
14655 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
14657 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14659 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14661 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
14665 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0
14669 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14670 /* enum: reserved value - do not use (may indicate alternative interpretation
14673 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0
14677 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14680 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14681 /* enum: RX PD firmware with approximately Siena-compatible behaviour
14684 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14686 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14688 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14692 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14694 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14696 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14700 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14702 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14703 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14704 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14706 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa
14708 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14712 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14716 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0
14720 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14721 /* enum: reserved value - do not use (may indicate alternative interpretation
14724 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0
14728 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14731 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14732 /* enum: TX PD firmware with approximately Siena-compatible behaviour
14735 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14737 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14739 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14743 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14744 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14748 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14750 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14751 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14752 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14754 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa
14756 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14759 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4
14762 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4
14765 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4
14767 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0
14779 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4
14881 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff
14883 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe
14885 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd
14892 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14900 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
14902 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
14906 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4
14925 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
14930 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
14933 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0
14934 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
14935 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1
14936 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
14937 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2
14939 * (SF-115995-SW) in the present configuration of firmware and port mode.
14944 * (SF-115995-SW) in the present configuration of firmware and port mode.
14952 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0
14953 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4
14954 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_OFST 0
14957 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_OFST 0
14958 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4
14960 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_OFST 0
14963 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14966 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_OFST 0
14969 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14972 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_OFST 0
14975 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14978 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14981 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14984 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_OFST 0
14987 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_OFST 0
14990 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14993 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_OFST 0
14996 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_OFST 0
14999 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_OFST 0
15002 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_OFST 0
15005 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_OFST 0
15008 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_OFST 0
15011 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_OFST 0
15014 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_OFST 0
15017 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_OFST 0
15020 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_OFST 0
15023 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_OFST 0
15026 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15029 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_OFST 0
15032 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15035 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_OFST 0
15038 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_OFST 0
15042 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4
15045 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0
15047 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1
15049 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
15051 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
15053 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6
15055 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
15057 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15059 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15061 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15062 /* enum: RXDP Test firmware image 4 */
15063 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15065 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105
15067 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15069 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15071 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15073 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15075 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c
15080 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0
15082 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1
15084 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
15086 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
15088 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6
15090 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
15092 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15094 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15096 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
15100 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0
15104 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15105 /* enum: reserved value - do not use (may indicate alternative interpretation
15108 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0
15112 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
15115 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15116 /* enum: RX PD firmware with approximately Siena-compatible behaviour
15119 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
15121 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
15123 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3
15127 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15129 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
15131 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
15135 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
15137 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
15138 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15139 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9
15141 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa
15143 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15147 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
15151 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0
15155 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
15156 /* enum: reserved value - do not use (may indicate alternative interpretation
15159 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0
15163 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
15166 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15167 /* enum: TX PD firmware with approximately Siena-compatible behaviour
15170 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
15172 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
15174 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3
15178 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15179 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
15183 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
15185 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
15186 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15187 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9
15189 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa
15191 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15194 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4
15197 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4
15200 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4
15202 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0
15214 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4
15316 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff
15318 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe
15320 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd
15327 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
15335 /* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
15337 /* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
15341 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4
15360 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
15365 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
15368 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0
15369 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
15370 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1
15371 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
15372 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2
15374 * (SF-115995-SW) in the present configuration of firmware and port mode.
15379 * (SF-115995-SW) in the present configuration of firmware and port mode.
15385 * hold at least this many 64-bit stats values, if they wish to receive all
15395 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 0
15396 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 4
15397 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_OFST 0
15400 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_OFST 0
15401 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 4
15403 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_OFST 0
15406 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
15409 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_OFST 0
15412 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_OFST 0
15415 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_OFST 0
15418 #define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
15421 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
15424 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
15427 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_OFST 0
15430 #define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_OFST 0
15433 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
15436 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_OFST 0
15439 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_OFST 0
15442 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_OFST 0
15445 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_OFST 0
15448 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_OFST 0
15451 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_OFST 0
15454 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_OFST 0
15457 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_OFST 0
15460 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_OFST 0
15463 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_OFST 0
15466 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_OFST 0
15469 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15472 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_OFST 0
15475 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15478 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_OFST 0
15481 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_OFST 0
15485 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 4
15488 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x0
15490 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x1
15492 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x2
15494 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x5
15496 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x6
15498 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a
15500 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15502 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15504 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15505 /* enum: RXDP Test firmware image 4 */
15506 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15508 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x105
15510 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15512 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15514 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15516 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15518 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c
15523 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x0
15525 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x1
15527 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x3
15529 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x5
15531 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x6
15533 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d
15535 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15537 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15539 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x103
15543 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 0
15547 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15548 /* enum: reserved value - do not use (may indicate alternative interpretation
15551 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x0
15555 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
15558 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15559 /* enum: RX PD firmware with approximately Siena-compatible behaviour
15562 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
15564 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
15566 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x3
15570 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15572 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
15574 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
15578 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
15580 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
15581 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15582 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x9
15584 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa
15586 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15590 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
15594 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 0
15598 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
15599 /* enum: reserved value - do not use (may indicate alternative interpretation
15602 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x0
15606 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
15609 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15610 /* enum: TX PD firmware with approximately Siena-compatible behaviour
15613 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
15615 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
15617 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x3
15621 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15622 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
15626 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
15628 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
15629 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15630 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x9
15632 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa
15634 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15637 #define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 4
15640 #define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 4
15643 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 4
15645 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 0
15657 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 4
15759 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff
15761 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe
15763 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd
15770 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
15778 /* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */
15780 /* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */
15784 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4
15803 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
15808 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
15811 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x0
15812 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
15813 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x1
15814 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
15815 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x2
15817 * (SF-115995-SW) in the present configuration of firmware and port mode.
15822 * (SF-115995-SW) in the present configuration of firmware and port mode.
15828 * hold at least this many 64-bit stats values, if they wish to receive all
15835 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
15838 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4
15843 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_OFST 0
15844 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 4
15845 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_OFST 0
15848 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_OFST 0
15849 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 4
15851 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_OFST 0
15854 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
15857 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_OFST 0
15860 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_OFST 0
15863 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_OFST 0
15866 #define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
15869 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
15872 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
15875 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_OFST 0
15878 #define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_OFST 0
15881 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
15884 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_OFST 0
15887 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_OFST 0
15890 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_OFST 0
15893 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_OFST 0
15896 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_OFST 0
15899 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_OFST 0
15902 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_OFST 0
15905 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_OFST 0
15908 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_OFST 0
15911 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_OFST 0
15914 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_OFST 0
15917 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15920 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_OFST 0
15923 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15926 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_OFST 0
15929 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_OFST 0
15933 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_OFST 4
15936 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP 0x0
15938 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_LOW_LATENCY 0x1
15940 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_PACKED_STREAM 0x2
15942 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_RULES_ENGINE 0x5
15944 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_DPDK 0x6
15946 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_BIST 0x10a
15948 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15950 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15952 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15953 /* enum: RXDP Test firmware image 4 */
15954 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15956 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_BACKPRESSURE 0x105
15958 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15960 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15962 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15964 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15966 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_SLOW 0x10c
15971 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP 0x0
15973 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_LOW_LATENCY 0x1
15975 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_HIGH_PACKET_RATE 0x3
15977 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_RULES_ENGINE 0x5
15979 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_DPDK 0x6
15981 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_BIST 0x12d
15983 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15985 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15987 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_CSR 0x103
15991 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_LBN 0
15995 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15996 /* enum: reserved value - do not use (may indicate alternative interpretation
15999 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RESERVED 0x0
16003 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
16006 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16007 /* enum: RX PD firmware with approximately Siena-compatible behaviour
16010 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
16012 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
16014 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_VSWITCH 0x3
16018 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16020 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
16022 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
16026 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
16028 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
16029 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16030 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_L3XUDP 0x9
16032 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_DPDK 0xa
16034 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16038 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
16042 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_LBN 0
16046 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
16047 /* enum: reserved value - do not use (may indicate alternative interpretation
16050 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RESERVED 0x0
16054 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
16057 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16058 /* enum: TX PD firmware with approximately Siena-compatible behaviour
16061 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
16063 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
16065 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_VSWITCH 0x3
16069 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16070 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
16074 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
16076 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
16077 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16078 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_L3XUDP 0x9
16080 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_DPDK 0xa
16082 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16085 #define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_LEN 4
16088 #define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_LEN 4
16091 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 4
16093 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_LBN 0
16105 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 4
16207 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff
16209 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe
16211 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_ASSIGNED 0xfd
16218 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
16226 /* MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */
16228 /* MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */
16232 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4
16251 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
16256 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
16259 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_8K 0x0
16260 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
16261 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_16K 0x1
16262 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
16263 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_64K 0x2
16265 * (SF-115995-SW) in the present configuration of firmware and port mode.
16270 * (SF-115995-SW) in the present configuration of firmware and port mode.
16276 * hold at least this many 64-bit stats values, if they wish to receive all
16283 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
16286 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_LEN 4
16296 #define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
16302 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_OFST 0
16303 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_LEN 4
16304 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_OFST 0
16307 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_OFST 0
16308 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_LBN 4
16310 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_OFST 0
16313 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
16316 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_OFST 0
16319 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_OFST 0
16322 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_OFST 0
16325 #define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
16328 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
16331 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
16334 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_OFST 0
16337 #define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_OFST 0
16340 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
16343 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_OFST 0
16346 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_OFST 0
16349 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_OFST 0
16352 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_OFST 0
16355 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_OFST 0
16358 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_OFST 0
16361 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_OFST 0
16364 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_OFST 0
16367 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_OFST 0
16370 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_OFST 0
16373 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_OFST 0
16376 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_OFST 0
16379 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_OFST 0
16382 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
16385 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_OFST 0
16388 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_OFST 0
16392 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_OFST 4
16395 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP 0x0
16397 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_LOW_LATENCY 0x1
16399 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_PACKED_STREAM 0x2
16401 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_RULES_ENGINE 0x5
16403 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_DPDK 0x6
16405 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_BIST 0x10a
16407 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
16409 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
16411 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
16412 /* enum: RXDP Test firmware image 4 */
16413 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
16415 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_BACKPRESSURE 0x105
16417 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
16419 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
16421 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
16423 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
16425 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_SLOW 0x10c
16430 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP 0x0
16432 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_LOW_LATENCY 0x1
16434 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_HIGH_PACKET_RATE 0x3
16436 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_RULES_ENGINE 0x5
16438 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_DPDK 0x6
16440 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_BIST 0x12d
16442 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
16444 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
16446 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_CSR 0x103
16450 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_LBN 0
16454 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
16455 /* enum: reserved value - do not use (may indicate alternative interpretation
16458 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RESERVED 0x0
16462 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
16465 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16466 /* enum: RX PD firmware with approximately Siena-compatible behaviour
16469 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
16471 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
16473 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_VSWITCH 0x3
16477 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16479 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
16481 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
16485 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
16487 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
16488 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16489 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_L3XUDP 0x9
16491 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_DPDK 0xa
16493 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16497 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
16501 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_LBN 0
16505 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
16506 /* enum: reserved value - do not use (may indicate alternative interpretation
16509 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RESERVED 0x0
16513 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
16516 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16517 /* enum: TX PD firmware with approximately Siena-compatible behaviour
16520 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
16522 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
16524 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_VSWITCH 0x3
16528 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16529 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
16533 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
16535 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
16536 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16537 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_L3XUDP 0x9
16539 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_DPDK 0xa
16541 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16544 #define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_LEN 4
16547 #define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_LEN 4
16550 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_LEN 4
16552 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_LBN 0
16564 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_LBN 4
16666 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff
16668 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe
16670 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_ASSIGNED 0xfd
16677 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
16685 /* MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */
16687 /* MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */
16691 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4
16710 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
16715 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
16718 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_8K 0x0
16719 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
16720 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_16K 0x1
16721 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
16722 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_64K 0x2
16724 * (SF-115995-SW) in the present configuration of firmware and port mode.
16729 * (SF-115995-SW) in the present configuration of firmware and port mode.
16735 * hold at least this many 64-bit stats values, if they wish to receive all
16742 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
16745 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_LEN 4
16755 #define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
16759 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_LEN 4
16761 #define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_LBN 0
16773 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_LBN 4
16806 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST 0
16807 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_LEN 4
16808 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_OFST 0
16811 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_OFST 0
16812 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_LBN 4
16814 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_OFST 0
16817 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
16820 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_OFST 0
16823 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_OFST 0
16826 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_OFST 0
16829 #define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
16832 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
16835 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
16838 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_OFST 0
16841 #define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_OFST 0
16844 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
16847 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_OFST 0
16850 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_OFST 0
16853 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_OFST 0
16856 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_OFST 0
16859 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_OFST 0
16862 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_OFST 0
16865 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_OFST 0
16868 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_OFST 0
16871 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_OFST 0
16874 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_OFST 0
16877 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_OFST 0
16880 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_OFST 0
16883 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_OFST 0
16886 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
16889 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_OFST 0
16892 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_OFST 0
16896 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_OFST 4
16899 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP 0x0
16901 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_LOW_LATENCY 0x1
16903 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_PACKED_STREAM 0x2
16905 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_RULES_ENGINE 0x5
16907 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_DPDK 0x6
16909 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_BIST 0x10a
16911 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
16913 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
16915 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
16916 /* enum: RXDP Test firmware image 4 */
16917 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
16919 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_BACKPRESSURE 0x105
16921 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
16923 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
16925 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
16927 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
16929 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_SLOW 0x10c
16934 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP 0x0
16936 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_LOW_LATENCY 0x1
16938 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_HIGH_PACKET_RATE 0x3
16940 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_RULES_ENGINE 0x5
16942 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_DPDK 0x6
16944 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_BIST 0x12d
16946 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
16948 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
16950 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_CSR 0x103
16954 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_LBN 0
16958 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
16959 /* enum: reserved value - do not use (may indicate alternative interpretation
16962 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RESERVED 0x0
16966 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
16969 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16970 /* enum: RX PD firmware with approximately Siena-compatible behaviour
16973 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
16975 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
16977 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_VSWITCH 0x3
16981 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16983 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
16985 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
16989 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
16991 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
16992 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16993 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_L3XUDP 0x9
16995 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_DPDK 0xa
16997 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17001 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
17005 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_LBN 0
17009 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
17010 /* enum: reserved value - do not use (may indicate alternative interpretation
17013 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RESERVED 0x0
17017 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
17020 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17021 /* enum: TX PD firmware with approximately Siena-compatible behaviour
17024 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
17026 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
17028 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_VSWITCH 0x3
17032 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17033 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
17037 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
17039 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
17040 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17041 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_L3XUDP 0x9
17043 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_DPDK 0xa
17045 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17048 #define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_LEN 4
17051 #define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_LEN 4
17054 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_LEN 4
17056 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_LBN 0
17068 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_LBN 4
17170 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff
17172 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe
17174 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_ASSIGNED 0xfd
17181 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
17189 /* MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */
17191 /* MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */
17195 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4
17214 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
17219 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
17222 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_8K 0x0
17223 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
17224 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_16K 0x1
17225 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
17226 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_64K 0x2
17228 * (SF-115995-SW) in the present configuration of firmware and port mode.
17233 * (SF-115995-SW) in the present configuration of firmware and port mode.
17239 * hold at least this many 64-bit stats values, if they wish to receive all
17246 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
17249 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_LEN 4
17259 #define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
17263 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_LEN 4
17265 #define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_LBN 0
17277 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_LBN 4
17306 /* These bits are reserved for communicating test-specific capabilities to
17307 * host-side test software. All production drivers should treat this field as
17313 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LEN 4
17317 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LEN 4
17324 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_OFST 0
17325 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_LEN 4
17326 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_OFST 0
17329 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_OFST 0
17330 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_LBN 4
17332 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_OFST 0
17335 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
17338 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_OFST 0
17341 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_OFST 0
17344 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_OFST 0
17347 #define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
17350 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
17353 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
17356 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_OFST 0
17359 #define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_OFST 0
17362 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
17365 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_OFST 0
17368 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_OFST 0
17371 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_OFST 0
17374 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_OFST 0
17377 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_OFST 0
17380 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_OFST 0
17383 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_OFST 0
17386 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_OFST 0
17389 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_OFST 0
17392 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_OFST 0
17395 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_OFST 0
17398 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_OFST 0
17401 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_OFST 0
17404 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
17407 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_OFST 0
17410 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_OFST 0
17414 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_OFST 4
17417 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP 0x0
17419 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_LOW_LATENCY 0x1
17421 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_PACKED_STREAM 0x2
17423 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_RULES_ENGINE 0x5
17425 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_DPDK 0x6
17427 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_BIST 0x10a
17429 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
17431 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
17433 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
17434 /* enum: RXDP Test firmware image 4 */
17435 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
17437 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_BACKPRESSURE 0x105
17439 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
17441 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
17443 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
17445 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
17447 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_SLOW 0x10c
17452 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP 0x0
17454 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_LOW_LATENCY 0x1
17456 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_HIGH_PACKET_RATE 0x3
17458 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_RULES_ENGINE 0x5
17460 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_DPDK 0x6
17462 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_BIST 0x12d
17464 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
17466 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
17468 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_CSR 0x103
17472 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_LBN 0
17476 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
17477 /* enum: reserved value - do not use (may indicate alternative interpretation
17480 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RESERVED 0x0
17484 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
17487 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17488 /* enum: RX PD firmware with approximately Siena-compatible behaviour
17491 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
17493 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
17495 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_VSWITCH 0x3
17499 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17501 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
17503 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
17507 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
17509 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
17510 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17511 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_L3XUDP 0x9
17513 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_DPDK 0xa
17515 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17519 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
17523 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_LBN 0
17527 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
17528 /* enum: reserved value - do not use (may indicate alternative interpretation
17531 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RESERVED 0x0
17535 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
17538 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17539 /* enum: TX PD firmware with approximately Siena-compatible behaviour
17542 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
17544 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
17546 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_VSWITCH 0x3
17550 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17551 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
17555 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
17557 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
17558 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17559 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_L3XUDP 0x9
17561 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_DPDK 0xa
17563 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17566 #define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_LEN 4
17569 #define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_LEN 4
17572 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_LEN 4
17574 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_LBN 0
17586 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_LBN 4
17688 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff
17690 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe
17692 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_ASSIGNED 0xfd
17699 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
17707 /* MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */
17709 /* MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */
17713 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4
17732 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
17737 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
17740 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_8K 0x0
17741 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
17742 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_16K 0x1
17743 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
17744 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_64K 0x2
17746 * (SF-115995-SW) in the present configuration of firmware and port mode.
17751 * (SF-115995-SW) in the present configuration of firmware and port mode.
17757 * hold at least this many 64-bit stats values, if they wish to receive all
17764 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
17767 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_LEN 4
17777 #define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
17781 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_LEN 4
17783 #define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_LBN 0
17795 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_LBN 4
17824 /* These bits are reserved for communicating test-specific capabilities to
17825 * host-side test software. All production drivers should treat this field as
17831 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LEN 4
17835 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LEN 4
17843 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
17849 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
17855 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
17856 /* The maximum number of queues that can be used by an RSS context in even-
17857 * spreading mode. In even-spreading mode the context has no indirection table
17861 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
17867 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_LEN 4
17872 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_LEN 4
17877 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_OFST 0
17878 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_LEN 4
17879 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_OFST 0
17882 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_OFST 0
17883 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_LBN 4
17885 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_OFST 0
17888 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
17891 #define MC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_OFST 0
17894 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_OFST 0
17897 #define MC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_OFST 0
17900 …efine MC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
17903 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
17906 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
17909 #define MC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_OFST 0
17912 #define MC_CMD_GET_CAPABILITIES_V10_OUT_QBB_OFST 0
17915 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
17918 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_OFST 0
17921 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_OFST 0
17924 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_OFST 0
17927 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_OFST 0
17930 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_OFST 0
17933 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_OFST 0
17936 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_OFST 0
17939 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_OFST 0
17942 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_OFST 0
17945 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_OFST 0
17948 #define MC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_OFST 0
17951 #define MC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_OFST 0
17954 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_OFST 0
17957 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
17960 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_OFST 0
17963 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_OFST 0
17967 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DPCPU_FW_ID_OFST 4
17970 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP 0x0
17972 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_LOW_LATENCY 0x1
17974 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_PACKED_STREAM 0x2
17976 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_RULES_ENGINE 0x5
17978 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_DPDK 0x6
17980 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_BIST 0x10a
17982 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
17984 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
17986 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
17987 /* enum: RXDP Test firmware image 4 */
17988 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
17990 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_BACKPRESSURE 0x105
17992 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
17994 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
17996 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
17998 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
18000 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_SLOW 0x10c
18005 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP 0x0
18007 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_LOW_LATENCY 0x1
18009 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_HIGH_PACKET_RATE 0x3
18011 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_RULES_ENGINE 0x5
18013 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_DPDK 0x6
18015 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_BIST 0x12d
18017 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
18019 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
18021 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_CSR 0x103
18025 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_LBN 0
18029 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
18030 /* enum: reserved value - do not use (may indicate alternative interpretation
18033 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RESERVED 0x0
18037 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
18040 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
18041 /* enum: RX PD firmware with approximately Siena-compatible behaviour
18044 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
18046 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
18048 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_VSWITCH 0x3
18052 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
18054 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
18056 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
18060 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
18062 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
18063 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
18064 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_L3XUDP 0x9
18066 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_DPDK 0xa
18068 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
18072 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
18076 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_LBN 0
18080 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
18081 /* enum: reserved value - do not use (may indicate alternative interpretation
18084 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RESERVED 0x0
18088 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
18091 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
18092 /* enum: TX PD firmware with approximately Siena-compatible behaviour
18095 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
18097 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
18099 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_VSWITCH 0x3
18103 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
18104 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
18108 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
18110 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
18111 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
18112 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_L3XUDP 0x9
18114 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_DPDK 0xa
18116 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
18119 #define MC_CMD_GET_CAPABILITIES_V10_OUT_HW_CAPABILITIES_LEN 4
18122 #define MC_CMD_GET_CAPABILITIES_V10_OUT_LICENSE_CAPABILITIES_LEN 4
18125 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS2_LEN 4
18127 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_LBN 0
18139 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_LBN 4
18241 #define MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff
18243 #define MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe
18245 #define MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_ASSIGNED 0xfd
18252 #define MC_CMD_GET_CAPABILITIES_V10_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
18260 /* MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff */
18262 /* MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe */
18266 #define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_NUM 4
18285 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
18290 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
18293 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_8K 0x0
18294 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
18295 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_16K 0x1
18296 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
18297 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_64K 0x2
18299 * (SF-115995-SW) in the present configuration of firmware and port mode.
18304 * (SF-115995-SW) in the present configuration of firmware and port mode.
18310 * hold at least this many 64-bit stats values, if they wish to receive all
18317 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
18320 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_MAX_LEN 4
18330 #define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
18334 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS3_LEN 4
18336 #define MC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_LBN 0
18348 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_LBN 4
18377 /* These bits are reserved for communicating test-specific capabilities to
18378 * host-side test software. All production drivers should treat this field as
18384 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LEN 4
18388 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LEN 4
18396 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
18402 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
18408 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
18409 /* The maximum number of queues that can be used by an RSS context in even-
18410 * spreading mode. In even-spreading mode the context has no indirection table
18414 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
18420 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_NUM_CONTEXTS_LEN 4
18425 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_TABLE_POOL_SIZE_LEN 4
18433 #define MC_CMD_GET_CAPABILITIES_V10_OUT_SUPPORTED_QUEUE_SIZES_LEN 4
18439 #define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
18446 #define MC_CMD_V2_EXTN 0x7f
18449 #define MC_CMD_V2_EXTN_IN_LEN 4
18451 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
18464 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
18466 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
18470 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1
18477 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2
18483 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0
18486 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4
18488 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0
18489 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_LEN 4
18496 #define MC_CMD_TCM_BUCKET_FREE 0xb3
18502 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4
18504 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0
18505 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_LEN 4
18508 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0
18515 #define MC_CMD_TCM_BUCKET_INIT 0xb4
18523 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0
18524 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_LEN 4
18526 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4
18527 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_LEN 4
18532 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_OFST 0
18533 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_BUCKET_LEN 4
18535 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_OFST 4
18536 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_RATE_LEN 4
18539 #define MC_CMD_TCM_BUCKET_INIT_EXT_IN_MAX_FILL_LEN 4
18542 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0
18549 #define MC_CMD_TCM_TXQ_INIT 0xb5
18557 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0
18558 #define MC_CMD_TCM_TXQ_INIT_IN_QID_LEN 4
18560 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4
18561 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_LEN 4
18564 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_LEN 4
18566 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAG_GUARANTEED_LBN 0
18576 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_LEN 4
18581 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_LEN 4
18586 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_LEN 4
18589 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_LEN 4
18594 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_OFST 0
18595 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_QID_LEN 4
18597 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_OFST 4
18598 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_NORMAL_LEN 4
18601 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAGS_LEN 4
18603 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_PQ_FLAG_GUARANTEED_LBN 0
18613 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_RP_BKT_LEN 4
18618 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT1_LEN 4
18623 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MAX_BKT2_LEN 4
18626 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_MIN_BKT_LEN 4
18629 #define MC_CMD_TCM_TXQ_INIT_EXT_IN_LABEL_GUARANTEED_LEN 4
18632 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0
18639 #define MC_CMD_LINK_PIOBUF 0x92
18647 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
18648 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
18650 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
18651 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
18654 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0
18661 #define MC_CMD_UNLINK_PIOBUF 0x93
18667 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4
18669 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
18670 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
18673 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
18678 * allocate and initialise a v-switch.
18680 #define MC_CMD_VSWITCH_ALLOC 0x94
18687 /* The port to connect to the v-switch's upstream port. */
18688 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
18689 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
18690 /* The type of v-switch to create. */
18691 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
18692 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4
18694 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
18696 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
18698 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
18700 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
18702 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
18703 /* Flags controlling v-port creation */
18705 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4
18707 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
18709 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,
18710 * this must be one or greated, and the attached v-ports must have exactly this
18711 * number of tags. For other v-switch types, this must be zero of greater, and
18712 * is an upper limit on the number of VLAN tags for attached v-ports. An error
18714 * v-ports with this number of tags.
18717 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
18720 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
18725 * de-allocate a v-switch.
18727 #define MC_CMD_VSWITCH_FREE 0x95
18733 #define MC_CMD_VSWITCH_FREE_IN_LEN 4
18734 /* The port to which the v-switch is connected. */
18735 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
18736 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4
18739 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0
18744 * read some config of v-switch. For now this command is an empty placeholder.
18745 * It may be used to check if a v-switch is connected to a given EVB port (if
18748 #define MC_CMD_VSWITCH_QUERY 0x63
18754 #define MC_CMD_VSWITCH_QUERY_IN_LEN 4
18755 /* The port to which the v-switch is connected. */
18756 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
18757 #define MC_CMD_VSWITCH_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
18760 #define MC_CMD_VSWITCH_QUERY_OUT_LEN 0
18765 * allocate a v-port.
18767 #define MC_CMD_VPORT_ALLOC 0x96
18774 /* The port to which the v-switch is connected. */
18775 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
18776 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
18777 /* The type of the new v-port. */
18778 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
18779 #define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4
18781 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
18783 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
18785 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
18786 /* enum: A normal v-port receives packets which match a specified MAC and/or
18789 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
18790 /* enum: An expansion v-port packets traffic which don't match any other
18791 * v-port.
18793 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
18794 /* enum: An test v-port receives packets which match any filters installed by
18797 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
18798 /* Flags controlling v-port creation */
18800 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4
18802 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
18809 * v-switch.
18812 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
18815 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4
18817 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
18824 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4
18825 /* The handle of the new v-port */
18826 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
18827 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4
18832 * de-allocate a v-port.
18834 #define MC_CMD_VPORT_FREE 0x97
18840 #define MC_CMD_VPORT_FREE_IN_LEN 4
18841 /* The handle of the v-port */
18842 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
18843 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4
18846 #define MC_CMD_VPORT_FREE_OUT_LEN 0
18851 * allocate a v-adaptor.
18853 #define MC_CMD_VADAPTOR_ALLOC 0x98
18860 /* The port to connect to the v-adaptor's port. */
18861 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
18862 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
18863 /* Flags controlling v-adaptor creation */
18865 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4
18867 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
18874 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4
18877 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
18880 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4
18882 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
18887 /* The MAC address to assign to this v-adaptor */
18891 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
18894 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
18899 * de-allocate a v-adaptor.
18901 #define MC_CMD_VADAPTOR_FREE 0x99
18907 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4
18908 /* The port to which the v-adaptor is connected. */
18909 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
18910 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4
18913 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0
18918 * assign a new MAC address to a v-adaptor.
18920 #define MC_CMD_VADAPTOR_SET_MAC 0x5d
18927 /* The port to which the v-adaptor is connected. */
18928 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
18929 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
18930 /* The new MAC address to assign to this v-adaptor */
18931 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4
18935 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0
18940 * read the MAC address assigned to a v-adaptor.
18942 #define MC_CMD_VADAPTOR_GET_MAC 0x5e
18948 #define MC_CMD_VADAPTOR_GET_MAC_IN_LEN 4
18949 /* The port to which the v-adaptor is connected. */
18950 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
18951 #define MC_CMD_VADAPTOR_GET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
18955 /* The MAC address assigned to this v-adaptor */
18956 #define MC_CMD_VADAPTOR_GET_MAC_OUT_MACADDR_OFST 0
18962 * read some config of v-adaptor.
18964 #define MC_CMD_VADAPTOR_QUERY 0x61
18970 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4
18971 /* The port to which the v-adaptor is connected. */
18972 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
18973 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
18978 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0
18979 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4
18980 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */
18981 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4
18982 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4
18985 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
18992 #define MC_CMD_EVB_PORT_ASSIGN 0x9a
19000 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
19001 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4
19003 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
19004 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4
19005 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_OFST 4
19006 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
19008 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_OFST 4
19013 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
19020 #define MC_CMD_RDWR_A64_REGIONS 0x9b
19027 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0
19028 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_LEN 4
19029 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4
19030 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_LEN 4
19032 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_LEN 4
19034 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_LEN 4
19035 /* Write enable bits 0-3, set to write, clear to read. */
19037 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4
19045 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0
19046 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_LEN 4
19047 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4
19048 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_LEN 4
19050 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_LEN 4
19052 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_LEN 4
19059 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
19065 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4
19067 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19068 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19071 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4
19073 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0
19074 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_LEN 4
19081 #define MC_CMD_ONLOAD_STACK_FREE 0x9d
19087 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4
19089 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0
19090 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_LEN 4
19093 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0
19100 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
19108 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19109 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19111 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
19112 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4
19116 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
19118 * queues, but the key and indirection table are pre-configured and may not be
19119 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
19121 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
19126 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EVEN_SPREADING 0x2
19131 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
19138 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4
19143 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_OFST 0
19144 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_LEN 4
19146 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_OFST 4
19147 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_LEN 4
19151 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EXCLUSIVE 0x0
19153 * queues, but the key and indirection table are pre-configured and may not be
19154 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
19156 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_SHARED 0x1
19161 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EVEN_SPREADING 0x2
19166 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
19173 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_LEN 4
19182 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_LEN 4
19185 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
19187 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
19190 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
19191 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4
19193 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff
19200 #define MC_CMD_RSS_CONTEXT_FREE 0x9f
19206 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
19208 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
19209 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4
19212 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
19219 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
19227 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
19228 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4
19229 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
19230 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
19234 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
19241 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
19247 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
19249 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
19250 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4
19254 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
19255 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
19265 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
19273 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
19274 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
19275 /* The 128-byte indirection table (1 byte per entry) */
19276 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
19280 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
19289 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
19295 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
19297 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
19298 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
19302 /* The 128-byte indirection table (1 byte per entry) */
19303 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
19309 * Write a portion of a selectable-size indirection table for an RSS context.
19313 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE 0x13e
19322 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_LEN(num) (4+4*(num))
19323 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_NUM(len) (((len)-4)/4)
19325 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_OFST 0
19326 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_RSS_CONTEXT_ID_LEN 4
19327 /* An array of index-value pairs to be written to the table. Structure is
19330 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_OFST 4
19331 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_IN_ENTRIES_LEN 4
19337 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_OUT_LEN 0
19340 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_LEN 4
19342 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_OFST 0
19344 #define MC_CMD_RSS_CONTEXT_WRITE_TABLE_ENTRY_INDEX_LBN 0
19355 * Read a portion of a selectable-size indirection table for an RSS context.
19359 #define MC_CMD_RSS_CONTEXT_READ_TABLE 0x13f
19368 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_LEN(num) (4+2*(num))
19369 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_NUM(len) (((len)-4)/2)
19371 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_OFST 0
19372 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_RSS_CONTEXT_ID_LEN 4
19374 #define MC_CMD_RSS_CONTEXT_READ_TABLE_IN_INDICES_OFST 4
19384 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_LEN(num) (0+2*(num))
19385 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_NUM(len) (((len)-0)/2)
19387 #define MC_CMD_RSS_CONTEXT_READ_TABLE_OUT_DATA_OFST 0
19398 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
19406 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
19407 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
19410 * in this case, the MODE fields may be set to non-zero values, and will take
19414 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In
19420 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
19421 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4
19422 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_OFST 4
19423 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
19425 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_OFST 4
19428 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_OFST 4
19431 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_OFST 4
19434 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_OFST 4
19435 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4
19436 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4
19437 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_OFST 4
19439 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4
19440 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_OFST 4
19442 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4
19443 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_OFST 4
19445 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4
19446 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_OFST 4
19448 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4
19449 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_OFST 4
19451 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4
19452 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_OFST 4
19454 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4
19457 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
19464 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
19470 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
19472 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
19473 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
19479 * capability), the _EN bits report the state. If any _MODE bits are non-zero
19482 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS
19490 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
19491 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4
19492 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_OFST 4
19493 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
19495 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_OFST 4
19498 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_OFST 4
19501 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_OFST 4
19504 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_OFST 4
19505 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4
19506 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4
19507 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_OFST 4
19509 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4
19510 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_OFST 4
19512 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4
19513 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_OFST 4
19515 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4
19516 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_OFST 4
19518 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4
19519 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_OFST 4
19521 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4
19522 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_OFST 4
19524 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4
19531 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
19539 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19540 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19541 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed
19542 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and
19545 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4
19546 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_LEN 4
19549 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4
19551 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
19554 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0
19555 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_LEN 4
19557 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_INVALID 0xffffffff
19564 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5
19570 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4
19572 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0
19573 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_LEN 4
19576 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0
19583 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
19591 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
19592 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
19593 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
19596 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4
19600 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0
19607 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
19613 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4
19615 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
19616 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_LEN 4
19620 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
19623 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4
19631 #define MC_CMD_GET_VECTOR_CFG 0xbf
19637 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0
19642 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0
19643 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_LEN 4
19645 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4
19646 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_LEN 4
19649 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_LEN 4
19656 #define MC_CMD_SET_VECTOR_CFG 0xc0
19666 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0
19667 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_LEN 4
19669 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4
19670 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_LEN 4
19673 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_LEN 4
19676 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0
19681 * Add a MAC address to a v-port
19683 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
19690 /* The handle of the v-port */
19691 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
19692 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4
19694 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
19698 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
19703 * Delete a MAC address from a v-port
19705 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
19712 /* The handle of the v-port */
19713 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
19714 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4
19716 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
19720 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
19725 * Delete a MAC address from a v-port
19727 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
19733 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
19734 /* The handle of the v-port */
19735 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
19736 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4
19739 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
19742 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
19743 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_NUM(len) (((len)-4)/6)
19745 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
19746 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4
19748 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
19750 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
19757 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port
19758 * has already been passed to another function (v-port's user), then that
19761 #define MC_CMD_VPORT_RECONFIGURE 0xeb
19768 /* The handle of the v-port */
19769 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0
19770 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4
19772 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4
19773 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4
19774 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_OFST 4
19775 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0
19777 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_OFST 4
19782 * v-switch.
19785 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4
19788 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4
19790 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0
19797 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4
19801 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4
19804 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4
19805 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0
19806 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4
19807 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_OFST 0
19808 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0
19814 * read some config of v-port.
19816 #define MC_CMD_EVB_PORT_QUERY 0x62
19822 #define MC_CMD_EVB_PORT_QUERY_IN_LEN 4
19823 /* The handle of the v-port */
19824 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_OFST 0
19825 #define MC_CMD_EVB_PORT_QUERY_IN_PORT_ID_LEN 4
19830 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_OFST 0
19831 #define MC_CMD_EVB_PORT_QUERY_OUT_PORT_FLAGS_LEN 4
19832 /* The number of VLAN tags that may be used on a v-adaptor connected to this
19835 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_OFST 4
19836 #define MC_CMD_EVB_PORT_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
19846 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
19854 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0
19855 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_LEN 4
19857 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4
19858 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_LEN 4
19864 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))
19865 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_NUM(len) (((len)-0)/12)
19867 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0
19878 #define MC_CMD_SET_RXDP_CONFIG 0xc1
19884 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4
19885 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0
19886 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_LEN 4
19887 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_OFST 0
19888 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0
19890 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_LEN_OFST 0
19894 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64 0x0
19896 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128 0x1
19898 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256 0x2
19901 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0
19908 #define MC_CMD_GET_RXDP_CONFIG 0xc2
19914 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0
19917 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4
19918 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0
19919 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_LEN 4
19920 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_OFST 0
19921 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0
19923 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_LEN_OFST 0
19934 #define MC_CMD_GET_CLOCK 0xac
19940 #define MC_CMD_GET_CLOCK_IN_LEN 0
19945 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
19946 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4
19948 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
19949 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4
19956 #define MC_CMD_SET_CLOCK 0xad
19964 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0
19965 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_LEN 4
19967 #define MC_CMD_SET_CLOCK_IN_SYS_DOMAIN_DONT_CHANGE 0x0
19968 /* Requested frequency in MHz for inter-core clock domain */
19969 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4
19970 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_LEN 4
19971 /* enum: Leave the inter-core clock domain frequency unchanged */
19972 #define MC_CMD_SET_CLOCK_IN_ICORE_DOMAIN_DONT_CHANGE 0x0
19975 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_LEN 4
19977 #define MC_CMD_SET_CLOCK_IN_DPCPU_DOMAIN_DONT_CHANGE 0x0
19980 #define MC_CMD_SET_CLOCK_IN_PCS_FREQ_LEN 4
19982 #define MC_CMD_SET_CLOCK_IN_PCS_DOMAIN_DONT_CHANGE 0x0
19985 #define MC_CMD_SET_CLOCK_IN_MC_FREQ_LEN 4
19987 #define MC_CMD_SET_CLOCK_IN_MC_DOMAIN_DONT_CHANGE 0x0
19990 #define MC_CMD_SET_CLOCK_IN_RMON_FREQ_LEN 4
19992 #define MC_CMD_SET_CLOCK_IN_RMON_DOMAIN_DONT_CHANGE 0x0
19995 #define MC_CMD_SET_CLOCK_IN_VSWITCH_FREQ_LEN 4
19997 #define MC_CMD_SET_CLOCK_IN_VSWITCH_DOMAIN_DONT_CHANGE 0x0
20002 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0
20003 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_LEN 4
20005 #define MC_CMD_SET_CLOCK_OUT_SYS_DOMAIN_UNSUPPORTED 0x0
20006 /* Resulting inter-core frequency in MHz */
20007 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4
20008 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_LEN 4
20009 /* enum: The inter-core clock domain doesn't exist / isn't used */
20010 #define MC_CMD_SET_CLOCK_OUT_ICORE_DOMAIN_UNSUPPORTED 0x0
20013 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_LEN 4
20015 #define MC_CMD_SET_CLOCK_OUT_DPCPU_DOMAIN_UNSUPPORTED 0x0
20018 #define MC_CMD_SET_CLOCK_OUT_PCS_FREQ_LEN 4
20020 #define MC_CMD_SET_CLOCK_OUT_PCS_DOMAIN_UNSUPPORTED 0x0
20023 #define MC_CMD_SET_CLOCK_OUT_MC_FREQ_LEN 4
20025 #define MC_CMD_SET_CLOCK_OUT_MC_DOMAIN_UNSUPPORTED 0x0
20028 #define MC_CMD_SET_CLOCK_OUT_RMON_FREQ_LEN 4
20030 #define MC_CMD_SET_CLOCK_OUT_RMON_DOMAIN_UNSUPPORTED 0x0
20033 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_FREQ_LEN 4
20035 #define MC_CMD_SET_CLOCK_OUT_VSWITCH_DOMAIN_UNSUPPORTED 0x0
20042 #define MC_CMD_DPCPU_RPC 0xae
20049 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0
20050 #define MC_CMD_DPCPU_RPC_IN_CPU_LEN 4
20052 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX0 0x0
20054 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1
20056 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2
20058 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX1 0x3
20062 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x80
20066 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX 0x81
20067 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be
20070 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4
20072 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_OFST 4
20075 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
20076 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */
20077 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */
20078 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */
20079 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */
20080 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */
20081 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
20082 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
20083 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
20084 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_OFST 4
20087 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_OFST 4
20090 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_OFST 4
20093 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_OFST 4
20096 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_OFST 4
20099 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
20100 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */
20101 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
20102 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
20103 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
20104 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_OFST 4
20107 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_OFST 4
20110 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_OFST 4
20113 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_OFST 4
20116 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
20117 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
20118 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
20119 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_OFST 4
20124 /* Register data to write. Only valid in write/write-read. */
20126 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_LEN 4
20129 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_LEN 4
20133 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0
20134 #define MC_CMD_DPCPU_RPC_OUT_RC_LEN 4
20136 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4
20138 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_OFST 4
20141 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_OFST 4
20147 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_LEN 4
20149 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_LEN 4
20151 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_LEN 4
20153 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_LEN 4
20160 #define MC_CMD_TRIGGER_INTERRUPT 0xe3
20166 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
20168 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
20169 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4
20172 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
20179 #define MC_CMD_SHMBOOT_OP 0xe6
20185 #define MC_CMD_SHMBOOT_OP_IN_LEN 4
20187 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_OFST 0
20188 #define MC_CMD_SHMBOOT_OP_IN_SHMBOOT_OP_LEN 4
20190 #define MC_CMD_SHMBOOT_OP_IN_PUSH_SLAVE_DATA 0x0
20193 #define MC_CMD_SHMBOOT_OP_OUT_LEN 0
20200 #define MC_CMD_CAP_BLK_READ 0xe7
20207 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_OFST 0
20208 #define MC_CMD_CAP_BLK_READ_IN_CAP_REG_LEN 4
20209 #define MC_CMD_CAP_BLK_READ_IN_ADDR_OFST 4
20210 #define MC_CMD_CAP_BLK_READ_IN_ADDR_LEN 4
20212 #define MC_CMD_CAP_BLK_READ_IN_COUNT_LEN 4
20218 #define MC_CMD_CAP_BLK_READ_OUT_LEN(num) (0+8*(num))
20219 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_NUM(len) (((len)-0)/8)
20220 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_OFST 0
20222 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_OFST 0
20223 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LEN 4
20224 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_LO_LBN 0
20226 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_OFST 4
20227 #define MC_CMD_CAP_BLK_READ_OUT_BUFFER_HI_LEN 4
20239 #define MC_CMD_DUMP_DO 0xe8
20246 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0
20247 #define MC_CMD_DUMP_DO_IN_PADDING_LEN 4
20248 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4
20249 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4
20250 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
20251 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
20253 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
20254 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
20255 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
20256 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
20257 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
20259 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20261 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
20263 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20265 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20267 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20268 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
20270 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20272 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20273 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
20275 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
20279 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff
20281 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
20283 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4
20284 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
20285 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
20287 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
20291 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20293 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
20295 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20297 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20299 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20301 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20303 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20305 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
20307 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
20310 #define MC_CMD_DUMP_DO_OUT_LEN 4
20311 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0
20312 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4
20319 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
20326 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0
20327 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4
20328 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4
20329 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4
20333 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
20337 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20339 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
20341 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20343 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20345 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20347 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20349 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20351 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
20353 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
20355 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4
20359 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
20363 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20365 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
20367 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20369 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20371 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20373 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20375 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20377 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
20379 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
20384 * Adjusts power supply parameters. This is a warranty-voiding operation.
20388 #define MC_CMD_SET_PSU 0xea
20395 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0
20396 #define MC_CMD_SET_PSU_IN_PARAM_LEN 4
20397 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
20398 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4
20399 #define MC_CMD_SET_PSU_IN_RAIL_LEN 4
20400 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
20401 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
20404 #define MC_CMD_SET_PSU_IN_VALUE_LEN 4
20407 #define MC_CMD_SET_PSU_OUT_LEN 0
20414 #define MC_CMD_GET_FUNCTION_INFO 0xec
20420 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
20424 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
20425 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4
20426 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
20427 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4
20431 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_PF_OFST 0
20432 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_PF_LEN 4
20433 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_VF_OFST 4
20434 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_VF_LEN 4
20439 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_INTF_LEN 4
20448 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed
20454 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
20457 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
20463 * should we wish to make this reliable; currently requests are fire-and-
20466 #define MC_CMD_UART_SEND_DATA 0xee
20476 #define MC_CMD_UART_SEND_DATA_OUT_DATA_NUM(len) (((len)-16)/1)
20478 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_OFST 0
20479 #define MC_CMD_UART_SEND_DATA_OUT_CHECKSUM_LEN 4
20481 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_OFST 4
20482 #define MC_CMD_UART_SEND_DATA_OUT_OFFSET_LEN 4
20485 #define MC_CMD_UART_SEND_DATA_OUT_LENGTH_LEN 4
20488 #define MC_CMD_UART_SEND_DATA_OUT_RESERVED_LEN 4
20491 #define MC_CMD_UART_SEND_DATA_OUT_DATA_MINNUM 0
20496 #define MC_CMD_UART_SEND_DATA_IN_LEN 0
20504 #define MC_CMD_UART_RECV_DATA 0xef
20512 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_OFST 0
20513 #define MC_CMD_UART_RECV_DATA_OUT_CHECKSUM_LEN 4
20515 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_OFST 4
20516 #define MC_CMD_UART_RECV_DATA_OUT_OFFSET_LEN 4
20519 #define MC_CMD_UART_RECV_DATA_OUT_LENGTH_LEN 4
20522 #define MC_CMD_UART_RECV_DATA_OUT_RESERVED_LEN 4
20529 #define MC_CMD_UART_RECV_DATA_IN_DATA_NUM(len) (((len)-16)/1)
20531 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_OFST 0
20532 #define MC_CMD_UART_RECV_DATA_IN_CHECKSUM_LEN 4
20534 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_OFST 4
20535 #define MC_CMD_UART_RECV_DATA_IN_RESERVED1_LEN 4
20538 #define MC_CMD_UART_RECV_DATA_IN_RESERVED2_LEN 4
20541 #define MC_CMD_UART_RECV_DATA_IN_RESERVED3_LEN 4
20544 #define MC_CMD_UART_RECV_DATA_IN_DATA_MINNUM 0
20551 * Read data programmed into the device One-Time-Programmable (OTP) Fuses
20553 #define MC_CMD_READ_FUSES 0xf0
20561 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0
20562 #define MC_CMD_READ_FUSES_IN_OFFSET_LEN 4
20564 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4
20565 #define MC_CMD_READ_FUSES_IN_LENGTH_LEN 4
20568 #define MC_CMD_READ_FUSES_OUT_LENMIN 4
20571 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
20572 #define MC_CMD_READ_FUSES_OUT_DATA_NUM(len) (((len)-4)/1)
20574 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
20575 #define MC_CMD_READ_FUSES_OUT_LENGTH_LEN 4
20577 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4
20579 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0
20588 #define MC_CMD_KR_TUNE 0xf1
20594 #define MC_CMD_KR_TUNE_IN_LENMIN 4
20597 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
20598 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_NUM(len) (((len)-4)/4)
20600 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
20603 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
20605 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
20607 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
20609 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
20611 #define MC_CMD_KR_TUNE_IN_RECAL 0x4
20615 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5
20620 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
20622 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7
20624 #define MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8
20626 #define MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9
20631 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4
20632 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4
20633 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0
20638 #define MC_CMD_KR_TUNE_OUT_LEN 0
20641 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4
20643 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0
20650 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4
20653 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
20654 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
20656 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
20657 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
20661 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0
20662 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
20664 /* enum: Attenuation (0-15, Huntington) */
20665 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
20666 /* enum: CTLE Boost (0-15, Huntington) */
20667 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
20668 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
20669 * positive, Medford - 0-31)
20671 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
20672 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
20673 * positive, Medford - 0-31)
20675 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
20676 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
20677 * positive, Medford - 0-16)
20679 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
20680 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
20681 * positive, Medford - 0-16)
20683 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
20684 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
20685 * positive, Medford - 0-16)
20687 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
20688 /* enum: Edge DFE DLEV (0-128 for Medford) */
20689 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7
20690 /* enum: Variable Gain Amplifier (0-15, Medford) */
20691 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8
20692 /* enum: CTLE EQ Capacitor (0-15, Medford) */
20693 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
20694 /* enum: CTLE EQ Resistor (0-7, Medford) */
20695 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
20696 /* enum: CTLE gain (0-31, Medford2) */
20697 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb
20698 /* enum: CTLE pole (0-31, Medford2) */
20699 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc
20700 /* enum: CTLE peaking (0-31, Medford2) */
20701 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd
20702 /* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */
20703 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe
20704 /* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */
20705 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf
20706 /* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */
20707 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10
20708 /* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */
20709 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11
20710 /* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */
20711 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12
20712 /* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */
20713 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13
20714 /* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */
20715 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14
20716 /* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */
20717 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15
20718 /* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */
20719 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16
20720 /* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */
20721 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17
20722 /* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */
20723 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18
20724 /* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */
20725 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19
20726 /* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */
20727 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a
20728 /* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */
20729 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b
20731 * (Medford2 - 6 bit signed (-29 - +29)))
20733 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c
20735 * (Medford2 - 6 bit signed (-29 - +29)))
20737 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d
20739 * (Medford2 - 6 bit signed (-29 - +29)))
20741 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e
20743 * (Medford2 - 6 bit signed (-29 - +29)))
20745 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f
20747 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20
20749 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21
20750 /* enum: CTLE Boost stages - retimer lineside (Medford2 with DS250x retimer - 4
20753 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_LS 0x22
20754 /* enum: DFE Tap1 - retimer lineside (Medford2 with DS250x retimer (-31 - 31))
20756 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_LS 0x23
20757 /* enum: DFE Tap2 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20759 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_LS 0x24
20760 /* enum: DFE Tap3 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20762 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_LS 0x25
20763 /* enum: DFE Tap4 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20765 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_LS 0x26
20766 /* enum: DFE Tap5 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20768 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_LS 0x27
20769 /* enum: CTLE Boost stages - retimer hostside (Medford2 with DS250x retimer - 4
20772 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_HS 0x28
20773 /* enum: DFE Tap1 - retimer hostside (Medford2 with DS250x retimer (-31 - 31))
20775 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_HS 0x29
20776 /* enum: DFE Tap2 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20778 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_HS 0x2a
20779 /* enum: DFE Tap3 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20781 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_HS 0x2b
20782 /* enum: DFE Tap4 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20784 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_HS 0x2c
20785 /* enum: DFE Tap5 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20787 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_HS 0x2d
20788 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0
20791 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
20792 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
20793 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
20794 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
20795 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
20796 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0
20799 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0
20801 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4
20802 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_OFST 0
20805 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0
20813 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
20814 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
20816 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
20822 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4
20823 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4
20827 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4
20828 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
20832 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4
20837 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4
20840 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_OFST 4
20842 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4
20843 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4
20846 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4
20851 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0
20854 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4
20856 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0
20863 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4
20866 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
20867 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
20869 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
20870 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
20874 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0
20875 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
20878 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0
20879 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
20880 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1
20881 /* enum: De-Emphasis Tap1 Fine */
20882 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2
20883 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
20884 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3
20885 /* enum: De-Emphasis Tap2 Fine (Huntington) */
20886 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4
20887 /* enum: Pre-Emphasis Magnitude (Huntington) */
20888 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5
20889 /* enum: Pre-Emphasis Fine (Huntington) */
20890 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6
20892 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7
20894 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8
20896 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9
20898 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa
20899 /* enum: Pre-cursor Tap (Medford, Medford2) */
20900 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb
20901 /* enum: Post-cursor Tap (Medford, Medford2) */
20902 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc
20904 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_LS 0xd
20905 /* enum: Pre-cursor Tap (Retimer Lineside) */
20906 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_LS 0xe
20907 /* enum: Post-cursor Tap (Retimer Lineside) */
20908 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_LS 0xf
20910 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_HS 0x10
20911 /* enum: Pre-cursor Tap (Retimer Hostside) */
20912 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_HS 0x11
20913 /* enum: Post-cursor Tap (Retimer Hostside) */
20914 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_HS 0x12
20915 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0
20918 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
20919 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
20920 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
20921 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
20922 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
20923 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0
20926 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_OFST 0
20929 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_OFST 0
20937 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))
20938 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
20940 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0
20946 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4
20947 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4
20951 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_OFST 4
20952 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0
20956 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_OFST 4
20961 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_OFST 4
20964 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_OFST 4
20967 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_OFST 4
20972 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0
20975 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4
20977 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0
20984 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0
20989 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
20994 /* Port-relative lane to scan eye on */
20995 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
20996 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
21001 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0
21006 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4
21007 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4
21008 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_OFST 4
21009 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0
21011 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_OFST 4
21016 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4
21019 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0
21022 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4
21024 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
21031 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
21034 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
21035 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
21036 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
21038 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
21045 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0
21050 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4
21051 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4
21052 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_OFST 4
21053 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0
21055 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_OFST 4
21060 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4
21061 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0
21062 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4
21067 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_OFST 0
21072 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4
21073 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4
21074 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */
21075 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */
21080 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_OFST 0
21085 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_OFST 4
21086 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_LEN 4
21089 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_LEN 4
21092 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_LEN 4
21093 /* C(-1) request */
21095 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4
21096 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */
21097 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */
21098 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */
21099 /* C(0) request */
21101 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4
21106 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_LEN 4
21112 /* C(-1) status */
21113 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0
21114 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4
21115 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */
21116 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */
21117 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */
21118 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */
21119 /* C(0) status */
21120 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4
21121 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4
21126 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_LEN 4
21129 /* C(-1) value */
21131 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_LEN 4
21132 /* C(0) value */
21134 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_LEN 4
21137 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4
21144 #define MC_CMD_PCIE_TUNE 0xf2
21150 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4
21153 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num))
21154 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_NUM(len) (((len)-4)/4)
21156 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0
21159 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0
21161 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1
21163 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2
21165 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3
21167 #define MC_CMD_PCIE_TUNE_IN_START_EYE_PLOT 0x5
21172 #define MC_CMD_PCIE_TUNE_IN_POLL_EYE_PLOT 0x6
21174 #define MC_CMD_PCIE_TUNE_IN_BIST_SQUARE_WAVE 0x7
21179 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4
21180 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4
21181 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0
21186 #define MC_CMD_PCIE_TUNE_OUT_LEN 0
21189 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4
21191 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
21198 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4
21201 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
21202 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
21204 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
21205 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
21209 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0
21210 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
21212 /* enum: Attenuation (0-15) */
21213 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0
21214 /* enum: CTLE Boost (0-15) */
21215 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1
21216 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
21217 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2
21218 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
21219 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3
21220 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
21221 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4
21222 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
21223 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5
21224 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
21225 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6
21227 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7
21229 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8
21231 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
21233 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
21234 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0
21237 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
21238 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
21239 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
21240 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
21241 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */
21242 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */
21243 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */
21244 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */
21245 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */
21246 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */
21247 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */
21248 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */
21249 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */
21250 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */
21251 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */
21252 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */
21253 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */
21254 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0
21257 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0
21260 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0
21268 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
21269 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
21271 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0
21277 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4
21278 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4
21282 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4
21283 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
21287 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4
21292 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4
21295 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_OFST 4
21298 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4
21301 #define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4
21306 #define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0
21309 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4
21311 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
21318 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4
21321 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
21322 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
21324 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
21325 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
21329 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0
21330 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
21333 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0
21335 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1
21336 /* enum: De-emphasis coefficient C(-1) (PIPE) */
21337 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2
21338 /* enum: De-emphasis coefficient C(0) (PIPE) */
21339 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3
21340 /* enum: De-emphasis coefficient C(+1) (PIPE) */
21341 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4
21342 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0
21344 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4
21347 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0
21350 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_OFST 0
21357 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
21362 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
21363 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
21366 #define MC_CMD_PCIE_TUNE_START_EYE_PLOT_OUT_LEN 0
21369 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_LEN 4
21371 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_IN_PCIE_TUNE_OP_OFST 0
21378 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
21381 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
21382 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
21383 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
21385 #define MC_CMD_PCIE_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
21390 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_IN_LEN 0
21393 #define MC_CMD_PCIE_TUNE_BIST_SQUARE_WAVE_OUT_LEN 0
21399 * - not used for V3 licensing
21401 #define MC_CMD_LICENSING 0xf3
21407 #define MC_CMD_LICENSING_IN_LEN 4
21409 #define MC_CMD_LICENSING_IN_OP_OFST 0
21410 #define MC_CMD_LICENSING_IN_OP_LEN 4
21411 /* enum: re-read and apply licenses after a license key partition update; note
21412 * that this operation returns a zero-length response
21414 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
21416 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
21421 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
21422 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4
21426 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
21427 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4
21430 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4
21433 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4
21437 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4
21442 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4
21443 /* licensing subsystem self-test report (for manftest) */
21445 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4
21446 /* enum: licensing subsystem self-test failed */
21447 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
21448 /* enum: licensing subsystem self-test passed */
21449 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
21455 * - V3 licensing (Medford)
21457 #define MC_CMD_LICENSING_V3 0xd0
21463 #define MC_CMD_LICENSING_V3_IN_LEN 4
21465 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0
21466 #define MC_CMD_LICENSING_V3_IN_OP_LEN 4
21467 /* enum: re-read and apply licenses after a license key partition update; note
21468 * that this operation returns a zero-length response
21470 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
21474 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1
21479 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0
21480 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4
21484 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4
21485 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4
21488 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4
21491 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4
21496 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4
21497 /* licensing subsystem self-test report (for manftest) */
21499 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4
21500 /* enum: licensing subsystem self-test failed */
21501 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
21502 /* enum: licensing subsystem self-test passed */
21503 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
21508 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LEN 4
21512 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LEN 4
21522 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LEN 4
21526 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LEN 4
21537 * partition - V3 licensing (Medford)
21539 #define MC_CMD_LICENSING_GET_ID_V3 0xd1
21545 #define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0
21552 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_NUM(len) (((len)-8)/1)
21554 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0
21555 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_LEN 4
21557 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4
21558 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_LEN 4
21562 #define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0
21569 * Execute an arbitrary MCDI command on the slave MC of a dual-core device.
21570 * This will fail on a single-core system.
21572 #define MC_CMD_MC2MC_PROXY 0xf4
21578 #define MC_CMD_MC2MC_PROXY_IN_LEN 0
21581 #define MC_CMD_MC2MC_PROXY_OUT_LEN 0
21590 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5
21596 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4
21598 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0
21599 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4
21602 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4
21604 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
21605 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4
21607 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
21609 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
21618 #define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2
21628 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0
21630 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0
21631 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LEN 4
21632 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_LBN 0
21634 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4
21635 #define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_LEN 4
21640 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4
21642 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0
21643 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_LEN 4
21645 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0
21647 #define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1
21656 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3
21666 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0
21668 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0
21669 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LEN 4
21670 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_LBN 0
21672 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4
21673 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_LEN 4
21679 /* states of these features - bit set for licensed, clear for not licensed */
21680 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0
21682 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0
21683 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LEN 4
21684 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_LBN 0
21686 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4
21687 #define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_LEN 4
21694 * Perform an action for an individual licensed application - not used for V3
21697 #define MC_CMD_LICENSED_APP_OP 0xf6
21706 #define MC_CMD_LICENSED_APP_OP_IN_LEN(num) (8+4*(num))
21707 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_NUM(len) (((len)-8)/4)
21709 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_OFST 0
21710 #define MC_CMD_LICENSED_APP_OP_IN_APP_ID_LEN 4
21712 #define MC_CMD_LICENSED_APP_OP_IN_OP_OFST 4
21713 #define MC_CMD_LICENSED_APP_OP_IN_OP_LEN 4
21715 #define MC_CMD_LICENSED_APP_OP_IN_OP_VALIDATE 0x0
21717 #define MC_CMD_LICENSED_APP_OP_IN_OP_MASK 0x1
21720 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_LEN 4
21721 #define MC_CMD_LICENSED_APP_OP_IN_ARGS_MINNUM 0
21726 #define MC_CMD_LICENSED_APP_OP_OUT_LENMIN 0
21729 #define MC_CMD_LICENSED_APP_OP_OUT_LEN(num) (0+4*(num))
21730 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_NUM(len) (((len)-0)/4)
21732 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_OFST 0
21733 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_LEN 4
21734 #define MC_CMD_LICENSED_APP_OP_OUT_RESULT_MINNUM 0
21741 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_OFST 0
21742 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_APP_ID_LEN 4
21744 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_OFST 4
21745 #define MC_CMD_LICENSED_APP_OP_VALIDATE_IN_OP_LEN 4
21753 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_OFST 0
21754 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_EXPIRY_LEN 4
21756 #define MC_CMD_LICENSED_APP_OP_VALIDATE_OUT_RESPONSE_OFST 4
21762 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_OFST 0
21763 #define MC_CMD_LICENSED_APP_OP_MASK_IN_APP_ID_LEN 4
21765 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_OFST 4
21766 #define MC_CMD_LICENSED_APP_OP_MASK_IN_OP_LEN 4
21769 #define MC_CMD_LICENSED_APP_OP_MASK_IN_FLAG_LEN 4
21772 #define MC_CMD_LICENSED_APP_OP_MASK_OUT_LEN 0
21777 * Perform validation for an individual licensed application - V3 licensing
21780 #define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4
21788 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 0
21794 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_LEN 4
21798 #define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_LEN 4
21805 * of two 384-bit integers, r and s, in big-endian order. The signature signs a
21806 * SHA-384 digest of a message constructed from the concatenation of the input
21808 * bytes] ... expiry_time[4 bytes] ...
21810 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 0
21814 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_LEN 4
21817 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_LEN 4
21819 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0
21821 #define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1
21828 /* MAC address of v-adaptor associated with the client. If no such v-adapator
21829 * exists, then the field is filled with 0xFF.
21837 * Mask features - V3 licensing (Medford)
21839 #define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5
21847 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0
21849 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0
21850 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LEN 4
21851 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_LBN 0
21853 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4
21854 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_LEN 4
21859 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_LEN 4
21861 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0
21863 #define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1
21866 #define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0
21873 * SF-116124-SW for an overview of how this could be used. The license is
21877 #define MC_CMD_LICENSING_V3_TEMPORARY 0xd6
21883 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_LEN 4
21885 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_OFST 0
21886 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_OP_LEN 4
21891 #define MC_CMD_LICENSING_V3_TEMPORARY_SET 0x0
21895 #define MC_CMD_LICENSING_V3_TEMPORARY_CLEAR 0x1
21899 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS 0x2
21903 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_OFST 0
21904 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_OP_LEN 4
21906 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_SET_LICENSE_OFST 4
21910 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_LEN 4
21911 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_OFST 0
21912 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_CLEAR_OP_LEN 4
21915 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_LEN 4
21916 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_OFST 0
21917 #define MC_CMD_LICENSING_V3_TEMPORARY_IN_STATUS_OP_LEN 4
21922 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_OFST 0
21923 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_STATUS_LEN 4
21925 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_OK 0x0
21927 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_IN_PROGRESS 0x1
21931 #define MC_CMD_LICENSING_V3_TEMPORARY_STATUS_ERROR 0x2
21933 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_OFST 4
21935 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_OFST 4
21936 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_LO_LEN 4
21940 #define MC_CMD_LICENSING_V3_TEMPORARY_OUT_STATUS_LICENSED_FEATURES_HI_LEN 4
21949 * configuration. A copy of all traffic delivered to the host (non-promiscuous
21953 #define MC_CMD_SET_PORT_SNIFF_CONFIG 0xf7
21961 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
21962 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
21963 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0
21964 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
21966 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_PROMISCUOUS_OFST 0
21970 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
21971 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
21974 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
21976 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
21978 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
21981 * of 0xFFFFFFFF is guaranteed never to be a valid handle.
21984 #define MC_CMD_SET_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
21987 #define MC_CMD_SET_PORT_SNIFF_CONFIG_OUT_LEN 0
21996 #define MC_CMD_GET_PORT_SNIFF_CONFIG 0xf8
22002 #define MC_CMD_GET_PORT_SNIFF_CONFIG_IN_LEN 0
22007 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
22008 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
22009 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0
22010 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
22012 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_PROMISCUOUS_OFST 0
22016 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
22017 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
22020 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
22022 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
22024 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
22027 #define MC_CMD_GET_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
22032 * Change configuration related to the parser-dispatcher subsystem.
22034 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
22043 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
22044 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_NUM(len) (((len)-8)/4)
22046 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
22047 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
22048 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible
22051 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
22052 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the
22056 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
22060 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
22061 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
22066 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4
22072 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0
22077 * Read configuration related to the parser-dispatcher subsystem.
22079 #define MC_CMD_GET_PARSER_DISP_CONFIG 0xfa
22087 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
22088 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
22094 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
22095 #define MC_CMD_GET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
22098 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LENMIN 4
22101 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_LEN(num) (0+4*(num))
22102 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_NUM(len) (((len)-0)/4)
22106 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_OFST 0
22107 #define MC_CMD_GET_PARSER_DISP_CONFIG_OUT_VALUE_LEN 4
22123 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG 0xfb
22131 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_OFST 0
22132 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_FLAGS_LEN 4
22133 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_OFST 0
22134 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_ENABLE_LBN 0
22137 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_OFST 4
22138 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_QUEUE_LEN 4
22141 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_LEN 4
22143 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_SIMPLE 0x0
22145 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_MODE_RSS 0x1
22148 * of 0xFFFFFFFF is guaranteed never to be a valid handle.
22151 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_IN_RX_CONTEXT_LEN 4
22154 #define MC_CMD_SET_TX_PORT_SNIFF_CONFIG_OUT_LEN 0
22163 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG 0xfc
22169 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_IN_LEN 0
22174 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_OFST 0
22175 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_FLAGS_LEN 4
22176 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_OFST 0
22177 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_ENABLE_LBN 0
22180 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_OFST 4
22181 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_QUEUE_LEN 4
22184 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_LEN 4
22186 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_SIMPLE 0x0
22188 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_MODE_RSS 0x1
22191 #define MC_CMD_GET_TX_PORT_SNIFF_CONFIG_OUT_RX_CONTEXT_LEN 4
22198 #define MC_CMD_RMON_STATS_RX_ERRORS 0xfe
22206 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_OFST 0
22207 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RX_QUEUE_LEN 4
22208 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_OFST 4
22209 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_FLAGS_LEN 4
22210 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_OFST 4
22211 #define MC_CMD_RMON_STATS_RX_ERRORS_IN_RST_LBN 0
22216 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_OFST 0
22217 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_CRC_ERRORS_LEN 4
22218 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_OFST 4
22219 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_TRUNC_ERRORS_LEN 4
22221 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_NO_DESC_DROPS_LEN 4
22223 #define MC_CMD_RMON_STATS_RX_ERRORS_OUT_RX_ABORT_LEN 4
22230 #define MC_CMD_GET_PCIE_RESOURCE_INFO 0xfd
22236 #define MC_CMD_GET_PCIE_RESOURCE_INFO_IN_LEN 0
22241 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_OFST 0
22242 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PFS_LEN 4
22244 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_OFST 4
22245 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VFS_LEN 4
22246 /* The maximum number of MSI-X vectors the device can provide in total */
22248 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VECTORS_LEN 4
22249 /* the number of MSI-X vectors the device will allocate by default to each PF
22252 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_PF_VECTORS_LEN 4
22253 /* the number of MSI-X vectors the device will allocate by default to each VF
22256 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_DEFAULT_VF_VECTORS_LEN 4
22257 /* the maximum number of MSI-X vectors the device can allocate to any one PF */
22259 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_PF_VECTORS_LEN 4
22260 /* the maximum number of MSI-X vectors the device can allocate to any one VF */
22262 #define MC_CMD_GET_PCIE_RESOURCE_INFO_OUT_MAX_VF_VECTORS_LEN 4
22269 #define MC_CMD_GET_PORT_MODES 0xff
22275 #define MC_CMD_GET_PORT_MODES_IN_LEN 0
22282 #define MC_CMD_GET_PORT_MODES_OUT_MODES_OFST 0
22283 #define MC_CMD_GET_PORT_MODES_OUT_MODES_LEN 4
22285 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_OFST 4
22286 #define MC_CMD_GET_PORT_MODES_OUT_DEFAULT_MODE_LEN 4
22289 #define MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_LEN 4
22296 #define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_OFST 0
22297 #define MC_CMD_GET_PORT_MODES_OUT_V2_MODES_LEN 4
22299 #define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_OFST 4
22300 #define MC_CMD_GET_PORT_MODES_OUT_V2_DEFAULT_MODE_LEN 4
22303 #define MC_CMD_GET_PORT_MODES_OUT_V2_CURRENT_MODE_LEN 4
22314 #define MC_CMD_GET_PORT_MODES_OUT_V2_ENGINEERING_MODES_LEN 4
22325 #define MC_CMD_OVERRIDE_PORT_MODE 0x137
22332 #define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_OFST 0
22333 #define MC_CMD_OVERRIDE_PORT_MODE_IN_FLAGS_LEN 4
22334 #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_OFST 0
22335 #define MC_CMD_OVERRIDE_PORT_MODE_IN_ENABLE_LBN 0
22338 #define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_OFST 4
22339 #define MC_CMD_OVERRIDE_PORT_MODE_IN_MODE_LEN 4
22342 #define MC_CMD_OVERRIDE_PORT_MODE_OUT_LEN 0
22349 #define MC_CMD_READ_ATB 0x100
22356 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_OFST 0
22357 #define MC_CMD_READ_ATB_IN_SIGNAL_BUS_LEN 4
22358 #define MC_CMD_READ_ATB_IN_BUS_CCOM 0x0 /* enum */
22359 #define MC_CMD_READ_ATB_IN_BUS_CKR 0x1 /* enum */
22360 #define MC_CMD_READ_ATB_IN_BUS_CPCIE 0x8 /* enum */
22361 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_OFST 4
22362 #define MC_CMD_READ_ATB_IN_SIGNAL_EN_BITNO_LEN 4
22364 #define MC_CMD_READ_ATB_IN_SIGNAL_SEL_LEN 4
22366 #define MC_CMD_READ_ATB_IN_SETTLING_TIME_US_LEN 4
22369 #define MC_CMD_READ_ATB_OUT_LEN 4
22370 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_OFST 0
22371 #define MC_CMD_READ_ATB_OUT_SAMPLE_MV_LEN 4
22379 #define MC_CMD_GET_WORKAROUNDS 0x59
22388 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
22389 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4
22390 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
22391 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4
22393 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
22395 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
22397 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
22399 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10
22401 * - before adding code that queries this workaround, remember that there's
22405 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20
22407 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40
22409 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80
22416 #define MC_CMD_PRIVILEGE_MASK 0x5a
22423 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF
22424 * 1,3 = 0x00030001
22426 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0
22427 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4
22428 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_OFST 0
22429 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0
22431 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_OFST 0
22434 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
22438 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4
22439 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4
22440 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
22441 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
22442 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
22443 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
22444 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
22446 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
22447 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
22448 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
22449 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
22450 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
22451 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
22455 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
22459 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
22465 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
22469 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
22471 * administrator-level operations that are not allowed from the local host once
22473 * SF-117064-DG for background).
22475 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
22476 /* enum: Control the Match-Action Engine if present. See mcdi_mae.yml. */
22477 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE 0x10000
22481 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALLOC_CLIENT 0x20000
22485 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_FUNC_DMA 0x40000
22487 * the device and to on-device DDR. It allows clients to use TX-DESC2CMPT-DESC
22488 * descriptors, and to use TX-SEG-DESC and TX-MEM2MEM-DESC with an address
22491 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ARBITRARY_DMA 0x80000
22495 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000
22498 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4
22500 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0
22501 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4
22508 #define MC_CMD_LINK_STATE_MODE 0x5c
22516 * e.g. VF 1,3 = 0x00030001
22518 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
22519 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4
22520 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_OFST 0
22521 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
22523 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_OFST 0
22527 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
22528 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4
22529 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
22530 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
22531 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
22534 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
22537 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4
22538 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0
22539 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4
22547 #define MC_CMD_GET_SNAPSHOT_LENGTH 0x101
22553 #define MC_CMD_GET_SNAPSHOT_LENGTH_IN_LEN 0
22558 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_OFST 0
22559 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MIN_LEN 4
22561 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_OFST 4
22562 #define MC_CMD_GET_SNAPSHOT_LENGTH_OUT_RX_SNAPLEN_MAX_LEN 4
22569 #define MC_CMD_FUSE_DIAGS 0x102
22575 #define MC_CMD_FUSE_DIAGS_IN_LEN 0
22579 /* Total number of mismatched bits between pairs in area 0 */
22580 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_OFST 0
22581 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_MISMATCH_BITS_LEN 4
22582 /* Total number of unexpectedly clear (set in B but not A) bits in area 0 */
22583 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_OFST 4
22584 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_A_BAD_BITS_LEN 4
22585 /* Total number of unexpectedly clear (set in A but not B) bits in area 0 */
22587 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_PAIR_B_BAD_BITS_LEN 4
22588 /* Checksum of data after logical OR of pairs in area 0 */
22590 #define MC_CMD_FUSE_DIAGS_OUT_AREA0_CHECKSUM_LEN 4
22593 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_MISMATCH_BITS_LEN 4
22596 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_A_BAD_BITS_LEN 4
22599 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_PAIR_B_BAD_BITS_LEN 4
22602 #define MC_CMD_FUSE_DIAGS_OUT_AREA1_CHECKSUM_LEN 4
22605 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_MISMATCH_BITS_LEN 4
22608 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_A_BAD_BITS_LEN 4
22611 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_PAIR_B_BAD_BITS_LEN 4
22614 #define MC_CMD_FUSE_DIAGS_OUT_AREA2_CHECKSUM_LEN 4
22620 * only effects non-admin functions unless the admin privilege itself is
22623 #define MC_CMD_PRIVILEGE_MODIFY 0x60
22631 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_OFST 0
22632 #define MC_CMD_PRIVILEGE_MODIFY_IN_FN_GROUP_LEN 4
22633 #define MC_CMD_PRIVILEGE_MODIFY_IN_NONE 0x0 /* enum */
22634 #define MC_CMD_PRIVILEGE_MODIFY_IN_ALL 0x1 /* enum */
22635 #define MC_CMD_PRIVILEGE_MODIFY_IN_PFS_ONLY 0x2 /* enum */
22636 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_ONLY 0x3 /* enum */
22637 #define MC_CMD_PRIVILEGE_MODIFY_IN_VFS_OF_PF 0x4 /* enum */
22638 #define MC_CMD_PRIVILEGE_MODIFY_IN_ONE 0x5 /* enum */
22640 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_OFST 4
22641 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_LEN 4
22642 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_OFST 4
22643 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_PF_LBN 0
22645 #define MC_CMD_PRIVILEGE_MODIFY_IN_FUNCTION_VF_OFST 4
22652 #define MC_CMD_PRIVILEGE_MODIFY_IN_ADD_MASK_LEN 4
22657 #define MC_CMD_PRIVILEGE_MODIFY_IN_REMOVE_MASK_LEN 4
22660 #define MC_CMD_PRIVILEGE_MODIFY_OUT_LEN 0
22667 #define MC_CMD_XPM_READ_BYTES 0x103
22675 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_OFST 0
22676 #define MC_CMD_XPM_READ_BYTES_IN_ADDR_LEN 4
22678 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_OFST 4
22679 #define MC_CMD_XPM_READ_BYTES_IN_COUNT_LEN 4
22682 #define MC_CMD_XPM_READ_BYTES_OUT_LENMIN 0
22685 #define MC_CMD_XPM_READ_BYTES_OUT_LEN(num) (0+1*(num))
22686 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_NUM(len) (((len)-0)/1)
22688 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_OFST 0
22690 #define MC_CMD_XPM_READ_BYTES_OUT_DATA_MINNUM 0
22699 #define MC_CMD_XPM_WRITE_BYTES 0x104
22709 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_NUM(len) (((len)-8)/1)
22711 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_OFST 0
22712 #define MC_CMD_XPM_WRITE_BYTES_IN_ADDR_LEN 4
22714 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_OFST 4
22715 #define MC_CMD_XPM_WRITE_BYTES_IN_COUNT_LEN 4
22719 #define MC_CMD_XPM_WRITE_BYTES_IN_DATA_MINNUM 0
22724 #define MC_CMD_XPM_WRITE_BYTES_OUT_LEN 0
22731 #define MC_CMD_XPM_READ_SECTOR 0x105
22739 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_OFST 0
22740 #define MC_CMD_XPM_READ_SECTOR_IN_INDEX_LEN 4
22742 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_OFST 4
22743 #define MC_CMD_XPM_READ_SECTOR_IN_SIZE_LEN 4
22746 #define MC_CMD_XPM_READ_SECTOR_OUT_LENMIN 4
22749 #define MC_CMD_XPM_READ_SECTOR_OUT_LEN(num) (4+1*(num))
22750 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_NUM(len) (((len)-4)/1)
22752 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_OFST 0
22753 #define MC_CMD_XPM_READ_SECTOR_OUT_TYPE_LEN 4
22754 #define MC_CMD_XPM_READ_SECTOR_OUT_BLANK 0x0 /* enum */
22755 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_128 0x1 /* enum */
22756 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_KEY_256 0x2 /* enum */
22757 #define MC_CMD_XPM_READ_SECTOR_OUT_CRYPTO_DATA 0x3 /* enum */
22758 #define MC_CMD_XPM_READ_SECTOR_OUT_INVALID 0xff /* enum */
22760 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_OFST 4
22762 #define MC_CMD_XPM_READ_SECTOR_OUT_DATA_MINNUM 0
22771 #define MC_CMD_XPM_WRITE_SECTOR 0x106
22781 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_NUM(len) (((len)-12)/1)
22783 * sectors (or until no more space available). If 0, only one write attempt is
22784 * made. Note that uncorrectable errors are unlikely, thanks to XPM self-repair
22787 #define MC_CMD_XPM_WRITE_SECTOR_IN_RETRIES_OFST 0
22792 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_OFST 4
22793 #define MC_CMD_XPM_WRITE_SECTOR_IN_TYPE_LEN 4
22798 #define MC_CMD_XPM_WRITE_SECTOR_IN_SIZE_LEN 4
22802 #define MC_CMD_XPM_WRITE_SECTOR_IN_DATA_MINNUM 0
22807 #define MC_CMD_XPM_WRITE_SECTOR_OUT_LEN 4
22809 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_OFST 0
22810 #define MC_CMD_XPM_WRITE_SECTOR_OUT_INDEX_LEN 4
22817 #define MC_CMD_XPM_INVALIDATE_SECTOR 0x107
22823 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_LEN 4
22825 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_OFST 0
22826 #define MC_CMD_XPM_INVALIDATE_SECTOR_IN_INDEX_LEN 4
22829 #define MC_CMD_XPM_INVALIDATE_SECTOR_OUT_LEN 0
22834 * Blank-check XPM memory and report bad locations
22836 #define MC_CMD_XPM_BLANK_CHECK 0x108
22844 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_OFST 0
22845 #define MC_CMD_XPM_BLANK_CHECK_IN_ADDR_LEN 4
22847 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_OFST 4
22848 #define MC_CMD_XPM_BLANK_CHECK_IN_COUNT_LEN 4
22851 #define MC_CMD_XPM_BLANK_CHECK_OUT_LENMIN 4
22854 #define MC_CMD_XPM_BLANK_CHECK_OUT_LEN(num) (4+2*(num))
22855 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_NUM(len) (((len)-4)/2)
22856 /* Total number of bad (non-blank) locations */
22857 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_OFST 0
22858 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_COUNT_LEN 4
22862 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_OFST 4
22864 #define MC_CMD_XPM_BLANK_CHECK_OUT_BAD_ADDR_MINNUM 0
22871 * Blank-check and repair XPM memory
22873 #define MC_CMD_XPM_REPAIR 0x109
22881 #define MC_CMD_XPM_REPAIR_IN_ADDR_OFST 0
22882 #define MC_CMD_XPM_REPAIR_IN_ADDR_LEN 4
22884 #define MC_CMD_XPM_REPAIR_IN_COUNT_OFST 4
22885 #define MC_CMD_XPM_REPAIR_IN_COUNT_LEN 4
22888 #define MC_CMD_XPM_REPAIR_OUT_LEN 0
22896 #define MC_CMD_XPM_DECODER_TEST 0x10a
22902 #define MC_CMD_XPM_DECODER_TEST_IN_LEN 0
22905 #define MC_CMD_XPM_DECODER_TEST_OUT_LEN 0
22916 #define MC_CMD_XPM_WRITE_TEST 0x10b
22922 #define MC_CMD_XPM_WRITE_TEST_IN_LEN 0
22925 #define MC_CMD_XPM_WRITE_TEST_OUT_LEN 0
22937 #define MC_CMD_EXEC_SIGNED 0x10c
22945 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_OFST 0
22946 #define MC_CMD_EXEC_SIGNED_IN_CODELEN_LEN 4
22948 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_OFST 4
22949 #define MC_CMD_EXEC_SIGNED_IN_DATALEN_LEN 4
22952 #define MC_CMD_EXEC_SIGNED_IN_KEYSECTOR_LEN 4
22958 #define MC_CMD_EXEC_SIGNED_OUT_LEN 0
22967 #define MC_CMD_PREPARE_SIGNED 0x10d
22973 #define MC_CMD_PREPARE_SIGNED_IN_LEN 4
22975 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_OFST 0
22976 #define MC_CMD_PREPARE_SIGNED_IN_DATALEN_LEN 4
22979 #define MC_CMD_PREPARE_SIGNED_OUT_LEN 0
22983 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4
22985 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0
22988 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
22990 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
22991 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0
22997 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
22999 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
23007 * parser-dispatcher will attempt to parse traffic on these ports as tunnel
23012 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
23018 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
23021 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
23022 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_NUM(len) (((len)-4)/4)
23024 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
23026 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_OFST 0
23027 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
23035 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4
23036 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
23037 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
23044 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
23046 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_OFST 0
23047 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
23058 #define MC_CMD_RX_BALANCING 0x118
23066 #define MC_CMD_RX_BALANCING_IN_PORT_OFST 0
23067 #define MC_CMD_RX_BALANCING_IN_PORT_LEN 4
23069 #define MC_CMD_RX_BALANCING_IN_PRIORITY_OFST 4
23070 #define MC_CMD_RX_BALANCING_IN_PRIORITY_LEN 4
23073 #define MC_CMD_RX_BALANCING_IN_SRC_DST_LEN 4
23076 #define MC_CMD_RX_BALANCING_IN_ENG_LEN 4
23079 #define MC_CMD_RX_BALANCING_OUT_LEN 0
23087 #define MC_CMD_NVRAM_PRIVATE_APPEND 0x11c
23097 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_DATA_BUFFER_NUM(len) (((len)-8)/1)
23099 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_OFST 0
23100 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_TAG_LEN 4
23102 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_OFST 4
23103 #define MC_CMD_NVRAM_PRIVATE_APPEND_IN_LENGTH_LEN 4
23112 #define MC_CMD_NVRAM_PRIVATE_APPEND_OUT_LEN 0
23121 #define MC_CMD_XPM_VERIFY_CONTENTS 0x11b
23127 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_LEN 4
23129 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_OFST 0
23130 #define MC_CMD_XPM_VERIFY_CONTENTS_IN_DATA_TYPE_LEN 4
23137 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_NUM(len) (((len)-12)/1)
23139 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_OFST 0
23140 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_SECTORS_LEN 4
23142 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_OFST 4
23143 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_NUM_BYTES_LEN 4
23146 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIG_LENGTH_LEN 4
23150 #define MC_CMD_XPM_VERIFY_CONTENTS_OUT_SIGNATURE_MINNUM 0
23164 #define MC_CMD_SET_EVQ_TMR 0x120
23171 /* Function-relative queue instance */
23172 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0
23173 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4
23175 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4
23176 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4
23179 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4
23182 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4
23183 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */
23184 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */
23185 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */
23186 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */
23191 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0
23192 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4
23194 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4
23195 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4
23202 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
23208 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0
23213 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0
23214 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4
23220 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4
23221 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4
23226 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4
23232 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4
23237 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4
23242 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4
23250 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4
23256 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4
23263 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4
23271 #define MC_CMD_ALLOCATE_TX_VFIFO_CP 0x11d
23279 * local queue index. The calling client must be the currently-assigned user of
23282 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_OFST 0
23283 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INSTANCE_LEN 4
23285 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_OFST 4
23286 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_MODE_LEN 4
23287 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_ENABLED 0x1 /* enum */
23289 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_DISABLED 0x0
23292 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_SIZE_LEN 4
23295 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_INGRESS_LEN 4
23297 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1
23300 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_EGRESS_LEN 4
23302 /* MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_USE_FUNCTION_VALUE -0x1 */
23303 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT0 0x0 /* enum */
23304 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT1 0x1 /* enum */
23305 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT2 0x2 /* enum */
23306 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_PORT3 0x3 /* enum */
23307 /* enum: To enable Switch loopback with Rx engine 0 */
23308 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE0 0x4
23310 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_IN_RX_ENGINE1 0x5
23313 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_LEN 4
23315 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_OFST 0
23316 #define MC_CMD_ALLOCATE_TX_VFIFO_CP_OUT_CP_ID_LEN 4
23324 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO 0x11e
23333 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_OFST 0
23334 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_CP_LEN 4
23336 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_OFST 4
23337 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_EGRESS_LEN 4
23339 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_USE_CP_VALUE -0x1
23340 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT0 0x0 /* enum */
23341 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT1 0x1 /* enum */
23342 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT2 0x2 /* enum */
23343 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PORT3 0x3 /* enum */
23344 /* enum: To enable Switch loopback with Rx engine 0 */
23345 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE0 0x4
23347 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_RX_ENGINE1 0x5
23350 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_SIZE_LEN 4
23352 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_NO_MINIMUM 0x0
23355 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_MODE_LEN 4
23358 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_PRIORITY_LEN 4
23360 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_IN_LOWEST_AVAILABLE -0x1
23365 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_OFST 0
23366 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_VID_LEN 4
23368 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_OFST 4
23369 #define MC_CMD_ALLOCATE_TX_VFIFO_VFIFO_OUT_PRIORITY_LEN 4
23375 * ready to be re-used.
23377 #define MC_CMD_TEARDOWN_TX_VFIFO_VF 0x11f
23383 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_LEN 4
23385 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_OFST 0
23386 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_IN_VFIFO_LEN 4
23389 #define MC_CMD_TEARDOWN_TX_VFIFO_VF_OUT_LEN 0
23395 * it ready to be re-used.
23397 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP 0x121
23403 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_LEN 4
23405 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_OFST 0
23406 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_IN_POOL_ID_LEN 4
23409 #define MC_CMD_DEALLOCATE_TX_VFIFO_CP_OUT_LEN 0
23417 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS 0x124
23423 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_IN_LEN 0
23428 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_OFST 0
23429 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_NET_LEN 4
23431 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_OFST 4
23432 #define MC_CMD_SWITCH_GET_UNASSIGNED_BUFFERS_OUT_ENG_LEN 4
23439 #define MC_CMD_SUC_VERSION 0x134
23445 #define MC_CMD_SUC_VERSION_IN_LEN 0
23449 /* The SUC firmware version as four numbers - a.b.c.d */
23450 #define MC_CMD_SUC_VERSION_OUT_VERSION_OFST 0
23451 #define MC_CMD_SUC_VERSION_OUT_VERSION_LEN 4
23452 #define MC_CMD_SUC_VERSION_OUT_VERSION_NUM 4
23457 #define MC_CMD_SUC_VERSION_OUT_BUILD_DATE_LEN 4
23459 * indicates family, memory sizes etc. See SF-116728-SW for further details.
23462 #define MC_CMD_SUC_VERSION_OUT_CHIP_ID_LEN 4
23467 #define MC_CMD_SUC_BOOT_VERSION_IN_LEN 4
23468 #define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_OFST 0
23469 #define MC_CMD_SUC_BOOT_VERSION_IN_MAGIC_LEN 4
23471 #define MC_CMD_SUC_VERSION_GET_BOOT_VERSION 0xb007700b
23474 #define MC_CMD_SUC_BOOT_VERSION_OUT_LEN 4
23476 #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_OFST 0
23477 #define MC_CMD_SUC_BOOT_VERSION_OUT_VERSION_LEN 4
23485 * combination of fields, then this command returns a list of prefix-ids,
23488 * supported, returns ENOTSUP. If the firmware can't create any new prefix-ids
23491 #define MC_CMD_GET_RX_PREFIX_ID 0x13b
23499 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_OFST 0
23501 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_OFST 0
23502 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LEN 4
23503 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_LO_LBN 0
23505 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_OFST 4
23506 #define MC_CMD_GET_RX_PREFIX_ID_IN_FIELDS_HI_LEN 4
23509 #define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_OFST 0
23510 #define MC_CMD_GET_RX_PREFIX_ID_IN_LENGTH_LBN 0
23512 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_VALID_OFST 0
23515 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_FLAG_OFST 0
23518 #define MC_CMD_GET_RX_PREFIX_ID_IN_CLASS_OFST 0
23521 #define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_OFST 0
23522 #define MC_CMD_GET_RX_PREFIX_ID_IN_PARTIAL_TSTAMP_LBN 4
23524 #define MC_CMD_GET_RX_PREFIX_ID_IN_RSS_HASH_OFST 0
23527 #define MC_CMD_GET_RX_PREFIX_ID_IN_USER_MARK_OFST 0
23530 #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_MPORT_OFST 0
23533 #define MC_CMD_GET_RX_PREFIX_ID_IN_INGRESS_VPORT_OFST 0
23536 #define MC_CMD_GET_RX_PREFIX_ID_IN_CSUM_FRAME_OFST 0
23539 #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIP_TCI_OFST 0
23542 #define MC_CMD_GET_RX_PREFIX_ID_IN_VLAN_STRIPPED_OFST 0
23545 #define MC_CMD_GET_RX_PREFIX_ID_IN_VSWITCH_STATUS_OFST 0
23553 #define MC_CMD_GET_RX_PREFIX_ID_OUT_LEN(num) (4+4*(num))
23554 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_NUM(len) (((len)-4)/4)
23555 /* Number of prefix-ids returned */
23556 #define MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_OFST 0
23557 #define MC_CMD_GET_RX_PREFIX_ID_OUT_NUM_RX_PREFIX_IDS_LEN 4
23561 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_OFST 4
23562 #define MC_CMD_GET_RX_PREFIX_ID_OUT_RX_PREFIX_ID_LEN 4
23570 #define RX_PREFIX_FIELD_INFO_LEN 4
23572 #define RX_PREFIX_FIELD_INFO_OFFSET_BITS_OFST 0
23574 #define RX_PREFIX_FIELD_INFO_OFFSET_BITS_LBN 0
23586 #define RX_PREFIX_FIELD_INFO_LENGTH 0x0 /* enum */
23587 #define RX_PREFIX_FIELD_INFO_RSS_HASH_VALID 0x1 /* enum */
23588 #define RX_PREFIX_FIELD_INFO_USER_FLAG 0x2 /* enum */
23589 #define RX_PREFIX_FIELD_INFO_CLASS 0x3 /* enum */
23590 #define RX_PREFIX_FIELD_INFO_PARTIAL_TSTAMP 0x4 /* enum */
23591 #define RX_PREFIX_FIELD_INFO_RSS_HASH 0x5 /* enum */
23592 #define RX_PREFIX_FIELD_INFO_USER_MARK 0x6 /* enum */
23593 #define RX_PREFIX_FIELD_INFO_INGRESS_MPORT 0x7 /* enum */
23594 #define RX_PREFIX_FIELD_INFO_INGRESS_VPORT 0x7 /* enum */
23595 #define RX_PREFIX_FIELD_INFO_CSUM_FRAME 0x8 /* enum */
23596 #define RX_PREFIX_FIELD_INFO_VLAN_STRIP_TCI 0x9 /* enum */
23597 #define RX_PREFIX_FIELD_INFO_VLAN_STRIPPED 0xa /* enum */
23598 #define RX_PREFIX_FIELD_INFO_VSWITCH_STATUS 0xb /* enum */
23605 #define RX_PREFIX_FIXED_RESPONSE_LENMIN 4
23608 #define RX_PREFIX_FIXED_RESPONSE_LEN(num) (4+4*(num))
23609 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_NUM(len) (((len)-4)/4)
23611 #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_OFST 0
23613 #define RX_PREFIX_FIXED_RESPONSE_PREFIX_LENGTH_BYTES_LBN 0
23625 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_OFST 4
23626 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_LEN 4
23627 #define RX_PREFIX_FIXED_RESPONSE_FIELDS_MINNUM 0
23640 #define MC_CMD_QUERY_RX_PREFIX_ID 0x13c
23646 #define MC_CMD_QUERY_RX_PREFIX_ID_IN_LEN 4
23648 #define MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_OFST 0
23649 #define MC_CMD_QUERY_RX_PREFIX_ID_IN_RX_PREFIX_ID_LEN 4
23652 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LENMIN 4
23655 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_LEN(num) (4+1*(num))
23656 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_NUM(len) (((len)-4)/1)
23658 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_OFST 0
23661 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_TYPE_FIXED 0x0
23665 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_OFST 4
23667 #define MC_CMD_QUERY_RX_PREFIX_ID_OUT_RESPONSE_MINNUM 0
23674 * A command to perform various bundle-related operations on insecure cards.
23676 #define MC_CMD_BUNDLE 0x13d
23682 #define MC_CMD_BUNDLE_IN_LEN 4
23683 /* Sub-command code */
23684 #define MC_CMD_BUNDLE_IN_OP_OFST 0
23685 #define MC_CMD_BUNDLE_IN_OP_LEN 4
23687 #define MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_GET 0x0
23689 #define MC_CMD_BUNDLE_IN_OP_COMPONENT_ACCESS_SET 0x1
23696 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_LEN 4
23697 /* Sub-command code. Must be OP_COMPONENT_ACCESS_GET. */
23698 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_OFST 0
23699 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_IN_OP_LEN 4
23704 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_LEN 4
23706 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_OFST 0
23707 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_GET_OUT_ACCESS_MODE_LEN 4
23708 /* enum: Component partitions are read-only from the host. */
23709 #define MC_CMD_BUNDLE_COMPONENTS_READ_ONLY 0x0
23710 /* enum: Component partitions can read read-from written-to by the host. */
23711 #define MC_CMD_BUNDLE_COMPONENTS_READ_WRITE 0x1
23715 * read-only on firmware built with bundle support. This command marks these
23721 /* Sub-command code. Must be OP_COMPONENT_ACCESS_SET. */
23722 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_OFST 0
23723 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_OP_LEN 4
23725 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_OFST 4
23726 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_IN_ACCESS_MODE_LEN 4
23731 #define MC_CMD_BUNDLE_OP_COMPONENT_ACCESS_SET_OUT_LEN 0
23738 #define MC_CMD_GET_VPD 0x165
23744 #define MC_CMD_GET_VPD_IN_LEN 4
23748 #define MC_CMD_GET_VPD_IN_ADDR_OFST 0
23749 #define MC_CMD_GET_VPD_IN_ADDR_LEN 4
23752 #define MC_CMD_GET_VPD_OUT_LENMIN 0
23755 #define MC_CMD_GET_VPD_OUT_LEN(num) (0+1*(num))
23756 #define MC_CMD_GET_VPD_OUT_DATA_NUM(len) (((len)-0)/1)
23758 #define MC_CMD_GET_VPD_OUT_DATA_OFST 0
23760 #define MC_CMD_GET_VPD_OUT_DATA_MINNUM 0
23767 * Provide information about the NC-SI stack
23769 #define MC_CMD_GET_NCSI_INFO 0x167
23777 #define MC_CMD_GET_NCSI_INFO_IN_OP_OFST 0
23778 #define MC_CMD_GET_NCSI_INFO_IN_OP_LEN 4
23780 #define MC_CMD_GET_NCSI_INFO_IN_OP_LINK 0x0
23782 #define MC_CMD_GET_NCSI_INFO_IN_OP_STATISTICS 0x1
23783 /* The NC-SI channel on which the operation is to be performed */
23784 #define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_OFST 4
23785 #define MC_CMD_GET_NCSI_INFO_IN_CHANNEL_LEN 4
23790 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_OFST 0
23791 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_SETTINGS_LEN 4
23793 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_OFST 4
23794 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ADV_CAP_LEN 4
23797 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATUS_LEN 4
23799 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_STATE_LBN 0
23808 #define MC_CMD_GET_NCSI_INFO_LINK_OUT_ATTACHED_LBN 4
23813 /* The number of NC-SI commands received. */
23814 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_OFST 0
23815 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMDS_RX_LEN 4
23816 /* The number of NC-SI commands dropped. */
23817 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_OFST 4
23818 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_PKTS_DROPPED_LEN 4
23819 /* The number of invalid NC-SI commands received. */
23821 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_TYPE_ERRS_LEN 4
23824 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_CMD_CSUM_ERRS_LEN 4
23825 /* The number of NC-SI requests received. */
23827 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_RX_PKTS_LEN 4
23828 /* The number of NC-SI responses sent (includes AENs) */
23830 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_NCSI_TX_PKTS_LEN 4
23831 /* The number of NC-SI AENs sent */
23833 #define MC_CMD_GET_NCSI_INFO_STATISTICS_OUT_AENS_SENT_LEN 4
23839 * be found within XN-200418-TC.
23841 #define CLIENT_HANDLE_LEN 4
23842 #define CLIENT_HANDLE_OPAQUE_OFST 0
23843 #define CLIENT_HANDLE_OPAQUE_LEN 4
23845 #define CLIENT_HANDLE_NULL 0xffffffff
23847 #define CLIENT_HANDLE_SELF 0xfffffffe
23848 #define CLIENT_HANDLE_OPAQUE_LBN 0
23854 #define CLOCK_INFO_CLOCK_ID_OFST 0
23857 #define CLOCK_INFO_CLOCK_CMC 0x0
23859 #define CLOCK_INFO_CLOCK_NMC 0x1
23861 #define CLOCK_INFO_CLOCK_SDNET 0x2
23863 #define CLOCK_INFO_CLOCK_SDNET_LUT 0x3
23865 #define CLOCK_INFO_CLOCK_SDNET_CTRL 0x4
23867 #define CLOCK_INFO_CLOCK_SSS 0x5
23869 #define CLOCK_INFO_CLOCK_MAC 0x6
23870 #define CLOCK_INFO_CLOCK_ID_LBN 0
23876 #define CLOCK_INFO_SETTABLE_LBN 0
23881 #define CLOCK_INFO_FREQUENCY_OFST 4
23883 #define CLOCK_INFO_FREQUENCY_LO_OFST 4
23884 #define CLOCK_INFO_FREQUENCY_LO_LEN 4
23888 #define CLOCK_INFO_FREQUENCY_HI_LEN 4
23893 /* Human-readable ASCII name for clock, with NUL termination */
23902 /* The instance of the scheduler. Refer to XN-200389-AW for the location of
23905 #define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_OFST 0
23907 #define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_A 0x0 /* enum */
23908 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_A 0x1 /* enum */
23909 #define SCHED_CREDIT_CHECK_RESULT_HUB_B 0x2 /* enum */
23910 #define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_C 0x3 /* enum */
23911 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_TX 0x4 /* enum */
23912 #define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_D 0x5 /* enum */
23913 #define SCHED_CREDIT_CHECK_RESULT_HUB_REPLAY 0x6 /* enum */
23914 #define SCHED_CREDIT_CHECK_RESULT_DMAC_H2C 0x7 /* enum */
23915 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_B 0x8 /* enum */
23916 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_REPLAY 0x9 /* enum */
23917 #define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LBN 0
23923 #define SCHED_CREDIT_CHECK_RESULT_DEST 0x0
23925 #define SCHED_CREDIT_CHECK_RESULT_SOURCE 0x1
23928 /* Level of node in scheduler hierarchy (level 0 is the bottom of the
23936 #define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_OFST 4
23937 #define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LEN 4
23942 #define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LEN 4
23947 #define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LEN 4
23956 #define MC_CMD_GET_CLOCKS_INFO 0x166
23962 #define MC_CMD_GET_CLOCKS_INFO_IN_LEN 0
23965 #define MC_CMD_GET_CLOCKS_INFO_OUT_LENMIN 0
23968 #define MC_CMD_GET_CLOCKS_INFO_OUT_LEN(num) (0+28*(num))
23969 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_NUM(len) (((len)-0)/28)
23971 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_OFST 0
23973 #define MC_CMD_GET_CLOCKS_INFO_OUT_INFOS_MINNUM 0
23981 * only affects checksum validation in VNIC RX - on TX the send descriptor
23982 * explicitly specifies encapsulation. These rules are per-VNIC, i.e. only
23991 * combinations. Each driver may only have a limited set of active rules -
23994 #define MC_CMD_VNIC_ENCAP_RULE_ADD 0x16d
24002 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_OFST 0
24003 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MPORT_SELECTOR_LEN 4
24004 /* Any non-zero bits other than the ones named below or an unsupported
24008 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_OFST 4
24009 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_FLAGS_LEN 4
24010 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_OFST 4
24011 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_ETHER_TYPE_LBN 0
24013 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_OUTER_VLAN_OFST 4
24016 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_IP_OFST 4
24019 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_IP_PROTO_OFST 4
24022 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_OFST 4
24023 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_MATCH_DST_PORT_LBN 4
24026 * Currently only IPv4 (0x0800) and IPv6 (0x86DD) ethertypes may be used.
24039 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_OUTER_VLAN_VID_LBN 0
24042 * case of IPv4, the IP should be in the first 4 bytes and all other bytes
24054 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_STRIP_OUTER_VLAN_LBN 0
24067 #define MC_CMD_VNIC_ENCAP_RULE_ADD_IN_ENCAP_TYPE_LEN 4
24070 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_LEN 4
24072 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_OFST 0
24073 #define MC_CMD_VNIC_ENCAP_RULE_ADD_OUT_HANDLE_LEN 4
24082 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE 0x16e
24088 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_LEN 4
24090 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_OFST 0
24091 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_IN_HANDLE_LEN 4
24094 #define MC_CMD_VNIC_ENCAP_RULE_REMOVE_OUT_LEN 0
24097 * the endianness specified by the RFC; users should ignore the broken-out
24101 #define UUID_TIME_LOW_OFST 0
24102 #define UUID_TIME_LOW_LEN 4
24103 #define UUID_TIME_LOW_LBN 0
24105 #define UUID_TIME_MID_OFST 4
24112 #define UUID_VERSION_WIDTH 4
24126 * currently-loaded plugin offering the given functionality (as identified by
24132 * the newest and that is the one opened. See SF-123625-SW for architectural
24135 #define MC_CMD_PLUGIN_ALLOC 0x1ad
24143 #define MC_CMD_PLUGIN_ALLOC_IN_UUID_OFST 0
24147 #define MC_CMD_PLUGIN_ALLOC_IN_FLAGS_LEN 4
24149 #define MC_CMD_PLUGIN_ALLOC_IN_FLAG_INFO_ONLY_LBN 0
24163 #define MC_CMD_PLUGIN_ALLOC_IN_ANY 0xffff
24169 #define MC_CMD_PLUGIN_ALLOC_OUT_LEN 4
24171 #define MC_CMD_PLUGIN_ALLOC_OUT_HANDLE_OFST 0
24172 #define MC_CMD_PLUGIN_ALLOC_OUT_HANDLE_LEN 4
24179 #define MC_CMD_PLUGIN_FREE 0x1ae
24185 #define MC_CMD_PLUGIN_FREE_IN_LEN 4
24187 #define MC_CMD_PLUGIN_FREE_IN_HANDLE_OFST 0
24188 #define MC_CMD_PLUGIN_FREE_IN_HANDLE_LEN 4
24191 #define MC_CMD_PLUGIN_FREE_OUT_LEN 0
24199 #define MC_CMD_PLUGIN_GET_META_GLOBAL 0x1af
24205 #define MC_CMD_PLUGIN_GET_META_GLOBAL_IN_LEN 4
24207 #define MC_CMD_PLUGIN_GET_META_GLOBAL_IN_HANDLE_OFST 0
24208 #define MC_CMD_PLUGIN_GET_META_GLOBAL_IN_HANDLE_LEN 4
24215 #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_UUID_OFST 0
24217 /* semver sub-version of this plugin extension */
24220 /* semver micro-version of this plugin extension */
24225 #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_NUM_MSGS_LEN 4
24229 /* Number of bytes mapped through to the plugin's CSRs. 0 if that feature was
24237 #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAGS_LEN 4
24239 #define MC_CMD_PLUGIN_GET_META_GLOBAL_OUT_MAPPED_CSR_FLAG_READ_LBN 0
24266 * extension in a human-readable way. Contrast with
24270 #define MC_CMD_PLUGIN_GET_META_PUBLISHER 0x1b0
24278 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_HANDLE_OFST 0
24279 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_HANDLE_LEN 4
24281 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_SUBTYPE_OFST 4
24282 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_SUBTYPE_LEN 4
24283 /* enum: Top-level information about the extension. The returned data is an
24285 * the extension. The data is a back-to-back list of zero-terminated strings;
24286 * the even-numbered fields (0,2,4,...) are keys and their following odd-
24288 * nominally UTF-8. Per RFC5013, the same key may be repeated any number of
24290 * and the UTF-8 encoding) may have been provided by the plugin author, so
24292 * top-level structure to separate out the keys and values; the contents of the
24293 * values is not expected to be machine-readable.
24295 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_EXTENSION_KVS 0x0
24300 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_IN_OFFSET_LEN 4
24303 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_LENMIN 4
24306 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_LEN(num) (4+1*(num))
24307 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_NUM(len) (((len)-4)/1)
24309 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_TOTAL_SIZE_OFST 0
24310 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_TOTAL_SIZE_LEN 4
24312 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_OFST 4
24314 #define MC_CMD_PLUGIN_GET_META_PUBLISHER_OUT_DATA_MINNUM 0
24325 #define MC_CMD_PLUGIN_GET_META_MSG 0x1b1
24333 #define MC_CMD_PLUGIN_GET_META_MSG_IN_HANDLE_OFST 0
24334 #define MC_CMD_PLUGIN_GET_META_MSG_IN_HANDLE_LEN 4
24336 #define MC_CMD_PLUGIN_GET_META_MSG_IN_ID_OFST 4
24337 #define MC_CMD_PLUGIN_GET_META_MSG_IN_ID_LEN 4
24344 #define MC_CMD_PLUGIN_GET_META_MSG_OUT_ID_OFST 0
24345 #define MC_CMD_PLUGIN_GET_META_MSG_OUT_ID_LEN 4
24349 #define MC_CMD_PLUGIN_GET_META_MSG_OUT_INDEX_OFST 4
24350 #define MC_CMD_PLUGIN_GET_META_MSG_OUT_INDEX_LEN 4
24351 /* Short human-readable codename for this message. This is conventionally
24353 * bytes at the end set to 0, however this convention is not enforced by the MC
24366 #define MC_CMD_PLUGIN_GET_META_MSG_OUT_DATA_SIZE_LEN 4
24372 #define PLUGIN_EXTENSION_UUID_OFST 0
24374 #define PLUGIN_EXTENSION_UUID_LBN 0
24395 #define MC_CMD_PLUGIN_GET_ALL 0x1b2
24401 #define MC_CMD_PLUGIN_GET_ALL_IN_LEN 4
24405 #define MC_CMD_PLUGIN_GET_ALL_IN_FLAGS_OFST 0
24406 #define MC_CMD_PLUGIN_GET_ALL_IN_FLAGS_LEN 4
24407 #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_ENABLED_OFST 0
24408 #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_ENABLED_LBN 0
24410 #define MC_CMD_PLUGIN_GET_ALL_IN_FLAG_INCLUDE_DISABLED_OFST 0
24415 #define MC_CMD_PLUGIN_GET_ALL_OUT_LENMIN 0
24418 #define MC_CMD_PLUGIN_GET_ALL_OUT_LEN(num) (0+20*(num))
24419 #define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_NUM(len) (((len)-0)/20)
24423 #define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_OFST 0
24425 #define MC_CMD_PLUGIN_GET_ALL_OUT_EXTENSIONS_MINNUM 0
24434 * identified by a 32-bit ID.
24436 #define MC_CMD_PLUGIN_REQ 0x1b3
24446 #define MC_CMD_PLUGIN_REQ_IN_DATA_NUM(len) (((len)-8)/1)
24448 #define MC_CMD_PLUGIN_REQ_IN_HANDLE_OFST 0
24449 #define MC_CMD_PLUGIN_REQ_IN_HANDLE_LEN 4
24451 #define MC_CMD_PLUGIN_REQ_IN_ID_OFST 4
24452 #define MC_CMD_PLUGIN_REQ_IN_ID_LEN 4
24458 #define MC_CMD_PLUGIN_REQ_IN_DATA_MINNUM 0
24463 #define MC_CMD_PLUGIN_REQ_OUT_LENMIN 0
24466 #define MC_CMD_PLUGIN_REQ_OUT_LEN(num) (0+1*(num))
24467 #define MC_CMD_PLUGIN_REQ_OUT_DATA_NUM(len) (((len)-0)/1)
24471 #define MC_CMD_PLUGIN_REQ_OUT_DATA_OFST 0
24473 #define MC_CMD_PLUGIN_REQ_OUT_DATA_MINNUM 0
24480 * WINDOW_SIZE_LOG2) map to TRGT_ADDR = DESC_ADDR - DESC_ADDR_BASE +
24485 #define DESC_ADDR_REGION_DESC_ADDR_BASE_OFST 0
24487 #define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_OFST 0
24488 #define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LEN 4
24489 #define DESC_ADDR_REGION_DESC_ADDR_BASE_LO_LBN 0
24491 #define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_OFST 4
24492 #define DESC_ADDR_REGION_DESC_ADDR_BASE_HI_LEN 4
24495 #define DESC_ADDR_REGION_DESC_ADDR_BASE_LBN 0
24503 #define DESC_ADDR_REGION_TRGT_ADDR_BASE_LO_LEN 4
24507 #define DESC_ADDR_REGION_TRGT_ADDR_BASE_HI_LEN 4
24514 #define DESC_ADDR_REGION_WINDOW_SIZE_LOG2_LEN 4
24521 #define DESC_ADDR_REGION_TRGT_ADDR_ALIGN_LOG2_LEN 4
24527 #define DESC_ADDR_REGION_RSVD_LO_LEN 4
24531 #define DESC_ADDR_REGION_RSVD_HI_LEN 4
24542 #define MC_CMD_GET_DESC_ADDR_INFO 0x1b7
24548 #define MC_CMD_GET_DESC_ADDR_INFO_IN_LEN 0
24551 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_LEN 4
24552 /* The type of mapping; see SF-nnnnnn-xx (EF100 driver writer's guide, once
24555 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_OFST 0
24556 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_LEN 4
24558 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_FLAT 0x0
24562 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_REGIONED 0x1
24569 #define MC_CMD_GET_DESC_ADDR_REGIONS 0x1b8
24575 #define MC_CMD_GET_DESC_ADDR_REGIONS_IN_LEN 0
24581 #define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LEN(num) (0+32*(num))
24582 #define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_NUM(len) (((len)-0)/32)
24586 #define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_OFST 0
24597 #define MC_CMD_SET_DESC_ADDR_REGIONS 0x1b9
24607 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_NUM(len) (((len)-8)/8)
24612 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_OFST 0
24613 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_LEN 4
24615 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_OFST 4
24616 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_LEN 4
24625 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LEN 4
24629 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LEN 4
24637 #define MC_CMD_SET_DESC_ADDR_REGIONS_OUT_LEN 0
24651 #define MC_CMD_CLIENT_CMD 0x1ba
24657 #define MC_CMD_CLIENT_CMD_IN_LEN 4
24659 #define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_OFST 0
24660 #define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_LEN 4
24663 #define MC_CMD_CLIENT_CMD_OUT_LEN 0
24670 * unit. See also MC_CMD_CLIENT_CMD. See XN-200265-TC for background, concepts
24672 * clients". The newly-created client is a child of the client which sent this
24677 #define MC_CMD_CLIENT_ALLOC 0x1bb
24683 #define MC_CMD_CLIENT_ALLOC_IN_LEN 0
24686 #define MC_CMD_CLIENT_ALLOC_OUT_LEN 4
24688 #define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_OFST 0
24689 #define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_LEN 4
24698 #define MC_CMD_CLIENT_FREE 0x1bc
24704 #define MC_CMD_CLIENT_FREE_IN_LEN 4
24708 #define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_OFST 0
24709 #define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_LEN 4
24712 #define MC_CMD_CLIENT_FREE_OUT_LEN 0
24722 * created are then owned by the user-client. Only the VI owner can call this
24726 #define MC_CMD_SET_VI_USER 0x1be
24733 /* Function-relative VI number to modify. */
24734 #define MC_CMD_SET_VI_USER_IN_INSTANCE_OFST 0
24735 #define MC_CMD_SET_VI_USER_IN_INSTANCE_LEN 4
24740 #define MC_CMD_SET_VI_USER_IN_CLIENT_ID_OFST 4
24741 #define MC_CMD_SET_VI_USER_IN_CLIENT_ID_LEN 4
24744 #define MC_CMD_SET_VI_USER_OUT_LEN 0
24779 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES 0x1c4
24785 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_LEN 4
24790 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
24791 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
24794 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMIN 0
24797 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(num) (0+6*(num))
24798 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_NUM(len) (((len)-0)/6)
24800 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_OFST 0
24802 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MINNUM 0
24813 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES 0x1c5
24819 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMIN 4
24822 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LEN(num) (4+6*(num))
24823 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_NUM(len) (((len)-4)/6)
24825 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
24826 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
24828 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_OFST 4
24830 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MINNUM 0
24835 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT_LEN 0
24840 * Retrieve physical build-level board attributes as configured at
24841 * manufacturing stage. Fields originate from EEPROM and per-platform constants
24850 #define MC_CMD_GET_BOARD_ATTR 0x1c6
24856 #define MC_CMD_GET_BOARD_ATTR_IN_LEN 0
24861 * response-message.
24863 #define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_OFST 0
24864 #define MC_CMD_GET_BOARD_ATTR_OUT_FLAGS_LEN 4
24865 #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_OFST 0
24866 #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_FAN_LBN 0
24868 #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_SOC_OFST 0
24871 #define MC_CMD_GET_BOARD_ATTR_OUT_HAS_AUX_POWER_OFST 0
24874 #define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_OFST 4
24875 #define MC_CMD_GET_BOARD_ATTR_OUT_ATTRIBUTES_LEN 4
24876 #define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_OFST 4
24877 #define MC_CMD_GET_BOARD_ATTR_OUT_SOC_EE_LBN 0
24879 #define MC_CMD_GET_BOARD_ATTR_OUT_SUC_EE_OFST 4
24882 #define MC_CMD_GET_BOARD_ATTR_OUT_FPGA_VOLTAGES_SUPPORTED_OFST 4
24886 #define MC_CMD_FPGA_VOLTAGE_LOW 0x0
24888 #define MC_CMD_FPGA_VOLTAGE_REG 0x1
24890 #define MC_CMD_FPGA_VOLTAGE_HIGH 0x2
24891 #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_COUNT_OFST 4
24899 #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_UNKNOWN 0x0
24901 #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_SFP 0x1
24903 #define MC_CMD_GET_BOARD_ATTR_OUT_CAGE_TYPE_QSFP 0x2
24908 * Retrieve current state of the System-on-Chip. This command is valid when
24911 #define MC_CMD_GET_SOC_STATE 0x1c7
24917 #define MC_CMD_GET_SOC_STATE_IN_LEN 0
24922 #define MC_CMD_GET_SOC_STATE_OUT_FLAGS_OFST 0
24923 #define MC_CMD_GET_SOC_STATE_OUT_FLAGS_LEN 4
24924 #define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_OFST 0
24925 #define MC_CMD_GET_SOC_STATE_OUT_SHOULD_THROTTLE_LBN 0
24927 #define MC_CMD_GET_SOC_STATE_OUT_OS_RECOVERY_REQUIRED_OFST 0
24930 #define MC_CMD_GET_SOC_STATE_OUT_WDT_FIRED_OFST 0
24934 #define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_OFST 4
24935 #define MC_CMD_GET_SOC_STATE_OUT_ATTRIBUTES_LEN 4
24936 #define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_OFST 4
24937 #define MC_CMD_GET_SOC_STATE_OUT_RUN_STATE_LBN 0
24940 #define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOT 0x0
24942 #define MC_CMD_GET_SOC_STATE_OUT_SOC_BOOTLOADER 0x1
24944 #define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_START 0x2
24946 #define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_RUNNING 0x3
24948 #define MC_CMD_GET_SOC_STATE_OUT_SOC_OS_MAINTENANCE 0x4
24951 #define MC_CMD_GET_SOC_STATE_OUT_RESET_COUNT_LEN 4
24962 #define MC_CMD_CHECK_SCHEDULER_CREDITS 0x1c8
24970 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_OFST 0
24971 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_LEN 4
24972 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_OFST 0
24973 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_LBN 0
24976 * into pages. This field specifies which (0-indexed) page to request. A
24977 * request with PAGE=0 will snapshot the results, and subsequent requests with
24978 * PAGE>0 will return data from the most recent snapshot. The GENERATION field
24982 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_OFST 4
24983 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_LEN 4
24990 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_NUM(len) (((len)-16)/16)
24992 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_OFST 0
24993 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_LEN 4
24995 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_OFST 4
24996 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_LEN 4
24999 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_LEN 4
25000 /* Result generation count. Incremented any time a request is made with PAGE=0.
25003 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_LEN 4
25007 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MINNUM 0
25014 * Query per-TXQ statistics.
25016 #define MC_CMD_TXQ_STATS 0x1d5
25024 #define MC_CMD_TXQ_STATS_IN_INSTANCE_OFST 0
25025 #define MC_CMD_TXQ_STATS_IN_INSTANCE_LEN 4
25027 #define MC_CMD_TXQ_STATS_IN_FLAGS_OFST 4
25028 #define MC_CMD_TXQ_STATS_IN_FLAGS_LEN 4
25029 #define MC_CMD_TXQ_STATS_IN_CLEAR_OFST 4
25030 #define MC_CMD_TXQ_STATS_IN_CLEAR_LBN 0
25034 #define MC_CMD_TXQ_STATS_OUT_LENMIN 0
25037 #define MC_CMD_TXQ_STATS_OUT_LEN(num) (0+8*(num))
25038 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_NUM(len) (((len)-0)/8)
25039 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_OFST 0
25041 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_OFST 0
25042 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_LEN 4
25043 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_LO_LBN 0
25045 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_HI_OFST 4
25046 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_HI_LEN 4
25049 #define MC_CMD_TXQ_STATS_OUT_STATISTICS_MINNUM 0
25052 #define MC_CMD_TXQ_STATS_CTPIO_MAX_FILL 0x0 /* enum */
25055 * defined in SF-120734-TC with more information in SF-122717-TC.
25057 #define FUNCTION_PERSONALITY_LEN 4
25058 #define FUNCTION_PERSONALITY_ID_OFST 0
25059 #define FUNCTION_PERSONALITY_ID_LEN 4
25061 #define FUNCTION_PERSONALITY_NULL 0x0
25062 /* enum: Function has an EF100-style function control window and VI windows
25065 #define FUNCTION_PERSONALITY_EF100 0x1
25069 #define FUNCTION_PERSONALITY_VIRTIO_NET 0x2
25073 #define FUNCTION_PERSONALITY_VIRTIO_BLK 0x3
25074 /* enum: Function is a Xilinx acceleration device - management function */
25075 #define FUNCTION_PERSONALITY_ACCEL_MGMT 0x4
25076 /* enum: Function is a Xilinx acceleration device - user function */
25077 #define FUNCTION_PERSONALITY_ACCEL_USR 0x5
25078 #define FUNCTION_PERSONALITY_ID_LBN 0
25086 #define MC_CMD_VIRTIO_GET_FEATURES 0x168
25092 #define MC_CMD_VIRTIO_GET_FEATURES_IN_LEN 4
25096 #define MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_OFST 0
25097 #define MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_LEN 4
25099 #define MC_CMD_VIRTIO_GET_FEATURES_IN_RESERVED 0x0
25101 #define MC_CMD_VIRTIO_GET_FEATURES_IN_NET 0x1
25103 #define MC_CMD_VIRTIO_GET_FEATURES_IN_BLOCK 0x2
25109 * specification ( https://docs.oasis-
25110 * open.org/virtio/virtio/v1.1/csprd01/virtio-v1.1-csprd01.pdf )
25112 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_OFST 0
25114 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_OFST 0
25115 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LEN 4
25116 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LBN 0
25118 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_OFST 4
25119 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LEN 4
25130 #define MC_CMD_VIRTIO_TEST_FEATURES 0x169
25140 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_OFST 0
25141 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_LEN 4
25144 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_OFST 4
25145 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_LEN 4
25152 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LEN 4
25156 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LEN 4
25161 #define MC_CMD_VIRTIO_TEST_FEATURES_OUT_LEN 0
25170 * allowed on multi-queue devices is returned. Response is expected to be
25173 #define MC_CMD_VIRTIO_GET_CAPABILITIES 0x1d3
25179 #define MC_CMD_VIRTIO_GET_CAPABILITIES_IN_LEN 4
25183 #define MC_CMD_VIRTIO_GET_CAPABILITIES_IN_DEVICE_ID_OFST 0
25184 #define MC_CMD_VIRTIO_GET_CAPABILITIES_IN_DEVICE_ID_LEN 4
25189 #define MC_CMD_VIRTIO_GET_CAPABILITIES_OUT_LEN 4
25191 #define MC_CMD_VIRTIO_GET_CAPABILITIES_OUT_MAX_QUEUES_OFST 0
25192 #define MC_CMD_VIRTIO_GET_CAPABILITIES_OUT_MAX_QUEUES_LEN 4
25202 #define MC_CMD_VIRTIO_INIT_QUEUE 0x16a
25212 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_OFST 0
25215 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_RXQ 0x0
25217 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_TXQ 0x1
25219 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_BLOCK 0x2
25228 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_VF_NULL 0xffff
25229 /* Desired instance. This is the function-local index of the associated VI, not
25232 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_OFST 4
25233 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_LEN 4
25236 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_LEN 4
25239 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_LEN 4
25241 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_LBN 0
25247 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LEN 4
25251 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LEN 4
25258 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LEN 4
25262 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LEN 4
25269 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LEN 4
25273 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LEN 4
25280 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_LEN 4
25287 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NO_VECTOR 0xffff
25292 * the features returned from MC_CMD_VIRTIO_GET_FEATURES. Features are per-
25299 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LEN 4
25303 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LEN 4
25315 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_AVAIL_IDX_LEN 4
25318 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_LEN 4
25326 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_USED_IDX_LEN 4
25329 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_LEN 4
25335 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_LEN 4
25338 #define MC_CMD_VIRTIO_INIT_QUEUE_RESP_LEN 0
25345 #define MC_CMD_VIRTIO_FINI_QUEUE 0x16b
25353 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_OFST 0
25365 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_VF_NULL 0xffff
25367 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_OFST 4
25368 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_LEN 4
25373 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_AVAIL_IDX_OFST 0
25374 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_AVAIL_IDX_LEN 4
25376 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_OFST 0
25377 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_LEN 4
25379 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_USED_IDX_OFST 4
25380 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_USED_IDX_LEN 4
25382 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_OFST 4
25383 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_LEN 4
25391 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET 0x16c
25401 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_OFST 0
25413 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_VF_NULL 0xffff
25415 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_OFST 4
25416 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_LEN 4
25421 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_OFST 0
25422 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_LEN 4
25424 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_OFST 4
25425 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_LEN 4
25428 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_LEN 4
25430 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_OFST 0
25431 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_LEN 4
25438 #define PCIE_FUNCTION_PF_OFST 0
25443 #define PCIE_FUNCTION_PF_ANY 0xfffe
25445 #define PCIE_FUNCTION_PF_NULL 0xffff
25446 #define PCIE_FUNCTION_PF_LBN 0
25454 #define PCIE_FUNCTION_VF_ANY 0xfffe
25458 #define PCIE_FUNCTION_VF_NULL 0xffff
25464 #define PCIE_FUNCTION_INTF_OFST 4
25465 #define PCIE_FUNCTION_INTF_LEN 4
25469 #define PCIE_FUNCTION_INTF_HOST 0x0
25473 #define PCIE_FUNCTION_INTF_AP 0x1
25483 #define QUEUE_ID_LEN 4
25485 #define QUEUE_ID_ABS_VI_OFST 0
25487 #define QUEUE_ID_ABS_VI_LBN 0
25501 * embedded Application Processor), via EF100 descriptor proxy, memory-to-
25502 * memory and descriptor-to-completion mechanisms. Primary user is Virtio-blk
25503 * subsystem, see SF-122927-TC. This function allocates a new descriptor proxy
25504 * function on the host and assigns a user-defined label. The actual function
25509 #define MC_CMD_DESC_PROXY_FUNC_CREATE 0x172
25520 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_OFST 0
25522 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_OFST 0
25523 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LEN 4
25524 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_LO_LBN 0
25526 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_OFST 4
25527 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_HI_LEN 4
25530 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_PF_OFST 0
25534 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_OFST 4
25535 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_FUNC_INTF_LEN 4
25537 * SF-120734-TC with more information in SF-122717-TC. At present, we only
25541 #define MC_CMD_DESC_PROXY_FUNC_CREATE_IN_PERSONALITY_LEN 4
25544 /* User-defined label (zero-terminated ASCII string) to uniquely identify the
25553 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_OFST 0
25554 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_HANDLE_LEN 4
25556 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_OFST 4
25558 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_OFST 4
25559 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_LO_LEN 4
25563 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_HI_LEN 4
25566 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_PF_OFST 4
25571 #define MC_CMD_DESC_PROXY_FUNC_CREATE_OUT_FUNC_INTF_LEN 4
25581 #define MC_CMD_DESC_PROXY_FUNC_DESTROY 0x173
25588 /* User-defined label (zero-terminated ASCII string) to uniquely identify the
25591 #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_LABEL_OFST 0
25595 #define MC_CMD_DESC_PROXY_FUNC_DESTROY_IN_STORE_LEN 4
25600 #define MC_CMD_DESC_PROXY_FUNC_DESTROY_OUT_LEN 0
25604 * bits. See Virtio specification v1.1, Section 5.2.4 (struct
25609 #define VIRTIO_BLK_CONFIG_FEATURES_OFST 0
25611 #define VIRTIO_BLK_CONFIG_FEATURES_LO_OFST 0
25612 #define VIRTIO_BLK_CONFIG_FEATURES_LO_LEN 4
25613 #define VIRTIO_BLK_CONFIG_FEATURES_LO_LBN 0
25615 #define VIRTIO_BLK_CONFIG_FEATURES_HI_OFST 4
25616 #define VIRTIO_BLK_CONFIG_FEATURES_HI_LEN 4
25619 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_OFST 0
25620 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BARRIER_LBN 0
25622 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SIZE_MAX_OFST 0
25625 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SEG_MAX_OFST 0
25628 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_OFST 0
25629 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_GEOMETRY_LBN 4
25631 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_RO_OFST 0
25634 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_BLK_SIZE_OFST 0
25637 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_SCSI_OFST 0
25640 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_FLUSH_OFST 0
25643 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_TOPOLOGY_OFST 0
25646 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_CONFIG_WCE_OFST 0
25649 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_MQ_OFST 0
25652 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_DISCARD_OFST 0
25655 #define VIRTIO_BLK_CONFIG_VIRTIO_BLK_F_WRITE_ZEROES_OFST 0
25658 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_INDIRECT_DESC_OFST 0
25661 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_EVENT_IDX_OFST 0
25664 #define VIRTIO_BLK_CONFIG_VIRTIO_F_VERSION_1_OFST 0
25667 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ACCESS_PLATFORM_OFST 0
25670 #define VIRTIO_BLK_CONFIG_VIRTIO_F_RING_PACKED_OFST 0
25673 #define VIRTIO_BLK_CONFIG_VIRTIO_F_IN_ORDER_OFST 0
25676 #define VIRTIO_BLK_CONFIG_VIRTIO_F_ORDER_PLATFORM_OFST 0
25679 #define VIRTIO_BLK_CONFIG_VIRTIO_F_SR_IOV_OFST 0
25682 #define VIRTIO_BLK_CONFIG_VIRTIO_F_NOTIFICATION_DATA_OFST 0
25685 #define VIRTIO_BLK_CONFIG_FEATURES_LBN 0
25687 /* The capacity of the device (expressed in 512-byte sectors) */
25691 #define VIRTIO_BLK_CONFIG_CAPACITY_LO_LEN 4
25695 #define VIRTIO_BLK_CONFIG_CAPACITY_HI_LEN 4
25704 #define VIRTIO_BLK_CONFIG_SIZE_MAX_LEN 4
25711 #define VIRTIO_BLK_CONFIG_SEG_MAX_LEN 4
25714 /* Disk-style geometry - cylinders. Only valid when VIRTIO_BLK_F_GEOMETRY is
25721 /* Disk-style geometry - heads. Only valid when VIRTIO_BLK_F_GEOMETRY is set.
25727 /* Disk-style geometry - sectors. Only valid when VIRTIO_BLK_F_GEOMETRY is set.
25735 #define VIRTIO_BLK_CONFIG_BLK_SIZE_LEN 4
25738 /* Block topology - number of logical blocks per physical block (log2). Only
25745 /* Block topology - offset of first aligned logical block. Only valid when
25752 /* Block topology - suggested minimum I/O size in blocks. Only valid when
25759 /* Block topology - optimal (suggested maximum) I/O size in blocks. Only valid
25763 #define VIRTIO_BLK_CONFIG_OPT_IO_SIZE_LEN 4
25779 /* Maximum discard sectors size, in 512-byte units. Only valid if
25783 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SECTORS_LEN 4
25789 #define VIRTIO_BLK_CONFIG_MAX_DISCARD_SEG_LEN 4
25792 /* Discard sector alignment, in 512-byte units. Only valid if
25796 #define VIRTIO_BLK_CONFIG_DISCARD_SECTOR_ALIGNMENT_LEN 4
25799 /* Maximum write zeroes sectors size, in 512-byte units. Only valid if
25803 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SECTORS_LEN 4
25810 #define VIRTIO_BLK_CONFIG_MAX_WRITE_ZEROES_SEG_LEN 4
25833 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET 0x174
25843 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_NUM(len) (((len)-20)/1)
25847 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_OFST 0
25848 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_HANDLE_LEN 4
25850 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_RESERVED_OFST 4
25858 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_IN_CONFIG_MINNUM 0
25863 #define MC_CMD_DESC_PROXY_FUNC_CONFIG_SET_OUT_LEN 0
25868 * Commit function configuration to non-volatile or volatile store. Once
25873 #define MC_CMD_DESC_PROXY_FUNC_COMMIT 0x175
25883 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_OFST 0
25884 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_HANDLE_LEN 4
25885 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_OFST 4
25886 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_STORE_LEN 4
25887 /* enum: Store into non-volatile (dynamic) config */
25888 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_NON_VOLATILE 0x0
25890 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_IN_VOLATILE 0x1
25893 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_LEN 4
25896 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_OFST 0
25897 #define MC_CMD_DESC_PROXY_FUNC_COMMIT_OUT_CONFIG_GENERATION_LEN 4
25903 * integer handle, valid until function is deallocated, MC rebooted or power-
25906 #define MC_CMD_DESC_PROXY_FUNC_OPEN 0x176
25913 /* User-defined label (zero-terminated ASCII string) to uniquely identify the
25916 #define MC_CMD_DESC_PROXY_FUNC_OPEN_IN_LABEL_OFST 0
25924 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_NUM(len) (((len)-40)/1)
25926 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_OFST 0
25927 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_HANDLE_LEN 4
25929 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_OFST 4
25931 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_OFST 4
25932 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_LO_LEN 4
25936 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_HI_LEN 4
25939 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_PF_OFST 4
25944 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_FUNC_INTF_LEN 4
25947 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PERSONALITY_LEN 4
25952 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_STATUS_LEN 4
25954 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_LIVE 0x0
25956 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_PENDING 0x1
25960 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_UNCONFIGURED 0x2
25965 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_GENERATION_LEN 4
25974 #define MC_CMD_DESC_PROXY_FUNC_OPEN_OUT_CONFIG_MINNUM 0
25988 #define MC_CMD_DESC_PROXY_FUNC_CLOSE 0x1a1
25994 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_LEN 4
25996 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_OFST 0
25997 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_IN_HANDLE_LEN 4
26000 #define MC_CMD_DESC_PROXY_FUNC_CLOSE_OUT_LEN 0
26005 #define DESC_PROXY_FUNC_MAP_FUNC_OFST 0
26007 #define DESC_PROXY_FUNC_MAP_FUNC_LO_OFST 0
26008 #define DESC_PROXY_FUNC_MAP_FUNC_LO_LEN 4
26009 #define DESC_PROXY_FUNC_MAP_FUNC_LO_LBN 0
26011 #define DESC_PROXY_FUNC_MAP_FUNC_HI_OFST 4
26012 #define DESC_PROXY_FUNC_MAP_FUNC_HI_LEN 4
26015 #define DESC_PROXY_FUNC_MAP_FUNC_LBN 0
26017 #define DESC_PROXY_FUNC_MAP_FUNC_PF_OFST 0
26019 #define DESC_PROXY_FUNC_MAP_FUNC_PF_LBN 0
26025 #define DESC_PROXY_FUNC_MAP_FUNC_INTF_OFST 4
26026 #define DESC_PROXY_FUNC_MAP_FUNC_INTF_LEN 4
26031 #define DESC_PROXY_FUNC_MAP_PERSONALITY_LEN 4
26036 /* User-defined label (zero-terminated ASCII string) to uniquely identify the
26049 #define MC_CMD_DESC_PROXY_FUNC_ENUM 0x177
26055 #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_LEN 4
26056 /* Starting index, set to 0 on first request. See
26059 #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_OFST 0
26060 #define MC_CMD_DESC_PROXY_FUNC_ENUM_IN_START_IDX_LEN 4
26063 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LENMIN 4
26066 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_LEN(num) (4+52*(num))
26067 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_NUM(len) (((len)-4)/52)
26068 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_OFST 0
26069 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FLAGS_LEN 4
26070 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_OFST 0
26071 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_MORE_DATA_LBN 0
26074 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_OFST 4
26076 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MINNUM 0
26077 #define MC_CMD_DESC_PROXY_FUNC_ENUM_OUT_FUNC_MAP_MAXNUM 4
26090 * supports multi-queue devices and has no dependency on host driver attach.
26092 #define MC_CMD_DESC_PROXY_FUNC_ENABLE 0x178
26102 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_OFST 0
26103 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_HANDLE_LEN 4
26107 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_OFST 4
26108 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_IN_TARGET_EVQ_LEN 4
26113 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_OFST 0
26114 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_COUNT_LEN 4
26116 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_OFST 4
26117 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_OUT_VI_BASE_LEN 4
26124 * source function (0 to max_virtqueues-1). For a multi-queue device, the
26130 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE 0x1d0
26140 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_HANDLE_OFST 0
26141 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_HANDLE_LEN 4
26143 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_SOURCE_QUEUE_OFST 4
26144 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_SOURCE_QUEUE_LEN 4
26149 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_IN_TARGET_EVQ_LEN 4
26152 #define MC_CMD_DESC_PROXY_FUNC_ENABLE_QUEUE_OUT_LEN 0
26157 * Disable descriptor proxying for function. For multi-queue functions,
26160 #define MC_CMD_DESC_PROXY_FUNC_DISABLE 0x179
26166 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_LEN 4
26170 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_OFST 0
26171 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_IN_HANDLE_LEN 4
26174 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_OUT_LEN 0
26181 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE 0x1d1
26191 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_HANDLE_OFST 0
26192 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_HANDLE_LEN 4
26194 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_SOURCE_QUEUE_OFST 4
26195 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_IN_SOURCE_QUEUE_LEN 4
26198 #define MC_CMD_DESC_PROXY_FUNC_DISABLE_QUEUE_OUT_LEN 0
26210 #define MC_CMD_DESC_PROXY_GET_VI_INFO 0x1d2
26216 #define MC_CMD_DESC_PROXY_GET_VI_INFO_IN_LEN 4
26220 #define MC_CMD_DESC_PROXY_GET_VI_INFO_IN_HANDLE_OFST 0
26221 #define MC_CMD_DESC_PROXY_GET_VI_INFO_IN_HANDLE_LEN 4
26224 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_LENMIN 0
26227 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_LEN(num) (0+4*(num))
26228 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_NUM(len) (((len)-0)/4)
26230 * queues (in order from 0 to max_virtqueues-1), as array of QUEUE_ID
26233 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_OFST 0
26234 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_LEN 4
26235 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_MINNUM 0
26238 #define MC_CMD_DESC_PROXY_FUNC_GET_VI_INFO_OUT_VI_MAP_ABS_VI_OFST 0
26249 * target. See SF-120734-TC for details on ADDR_SPC_IDs and mem2mem
26252 #define MC_CMD_GET_ADDR_SPC_ID 0x1a0
26260 #define MC_CMD_GET_ADDR_SPC_ID_IN_TYPE_OFST 0
26261 #define MC_CMD_GET_ADDR_SPC_ID_IN_TYPE_LEN 4
26265 #define MC_CMD_GET_ADDR_SPC_ID_IN_SELF 0x0
26269 #define MC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC 0x1
26273 #define MC_CMD_GET_ADDR_SPC_ID_IN_PCI_FUNC_PASID 0x2
26277 #define MC_CMD_GET_ADDR_SPC_ID_IN_REL_VI 0x3
26281 #define MC_CMD_GET_ADDR_SPC_ID_IN_ABS_VI 0x4
26285 #define MC_CMD_GET_ADDR_SPC_ID_IN_DESC_PROXY_HANDLE 0x5
26287 #define MC_CMD_GET_ADDR_SPC_ID_IN_MC_MEM 0x6
26288 /* enum: Address space ID for DMA to/from other SmartNIC memory (on-chip, DDR)
26290 #define MC_CMD_GET_ADDR_SPC_ID_IN_NIC_MEM 0x7
26294 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_OFST 4
26296 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_OFST 4
26297 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_LO_LEN 4
26301 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_HI_LEN 4
26304 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_PF_OFST 4
26309 #define MC_CMD_GET_ADDR_SPC_ID_IN_FUNC_INTF_LEN 4
26312 #define MC_CMD_GET_ADDR_SPC_ID_IN_PASID_LEN 4
26315 #define MC_CMD_GET_ADDR_SPC_ID_IN_VI_LEN 4
26318 #define MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_OFST 4
26319 #define MC_CMD_GET_ADDR_SPC_ID_IN_HANDLE_LEN 4
26326 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_OFST 0
26328 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_OFST 0
26329 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LEN 4
26330 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_LO_LBN 0
26332 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_OFST 4
26333 #define MC_CMD_GET_ADDR_SPC_ID_OUT_ADDR_SPC_ID_HI_LEN 4
26345 #define MC_CMD_GET_CLIENT_HANDLE 0x1c3
26353 #define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_OFST 0
26354 #define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_LEN 4
26355 /* enum: Obtain a client handle for a PCIe function-type client. */
26356 #define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_FUNC 0x0
26357 /* PCIe Function ID (as struct PCIE_FUNCTION). Valid when TYPE==FUNC. Use: -
26358 * INTF=CALLER, PF=PF_NULL, VF=VF_NULL to refer to the calling function -
26360 * a sibling VF of the calling VF. - INTF=CALLER, PF=..., VF=VF_NULL to refer
26361 * to a PF on the calling interface - INTF=CALLER, PF=..., VF=... to refer to a
26362 * VF on the calling interface - INTF=..., PF=..., VF=VF_NULL to refer to a PF
26363 * on a named interface - INTF=..., PF=..., VF=... to refer to a VF on a named
26369 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_OFST 4
26371 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_OFST 4
26372 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LEN 4
26376 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LEN 4
26382 #define MC_CMD_GET_CLIENT_HANDLE_IN_PCIE_FUNCTION_INTF_NULL 0xffffffff
26383 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_OFST 4
26388 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_LEN 4
26391 #define MC_CMD_GET_CLIENT_HANDLE_OUT_LEN 4
26392 #define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_OFST 0
26393 #define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_LEN 4
26396 #define MAE_FIELD_FLAGS_LEN 4
26397 #define MAE_FIELD_FLAGS_FLAT_OFST 0
26398 #define MAE_FIELD_FLAGS_FLAT_LEN 4
26399 #define MAE_FIELD_FLAGS_SUPPORT_STATUS_OFST 0
26400 #define MAE_FIELD_FLAGS_SUPPORT_STATUS_LBN 0
26402 #define MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS_OFST 0
26405 #define MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS_OFST 0
26408 #define MAE_FIELD_FLAGS_FLAT_LBN 0
26421 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_OFST 0
26422 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_LEN 4
26423 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_LBN 0
26425 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_OFST 4
26426 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LEN 4
26486 #define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_LEN 4
26490 #define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_LEN 4
26502 #define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_LEN 4
26506 #define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_LEN 4
26545 #define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_LBN 0
26564 #define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_LBN 0
26580 #define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LEN 4
26584 #define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_LEN 4
26608 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_OFST 0
26609 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_LEN 4
26610 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_LBN 0
26612 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_OFST 4
26613 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LEN 4
26617 #define MAE_FIELD_MASK_VALUE_PAIRS_MARK_LEN 4
26621 #define MAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_LEN 4
26681 #define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_LEN 4
26685 #define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_LEN 4
26697 #define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_LEN 4
26701 #define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_LEN 4
26741 #define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_LEN 4
26745 #define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_LEN 4
26773 #define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_LEN 4
26777 #define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_LEN 4
26781 #define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_LEN 4
26785 #define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_LEN 4
26845 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_LEN 4
26849 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_LEN 4
26861 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_LEN 4
26865 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_LEN 4
26901 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_LEN 4
26905 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_LEN 4
26925 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_LEN 4
26929 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_LEN 4
26935 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_OFST 0
26936 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_LEN 4
26937 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_LBN 0
26939 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_OFST 4
26940 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_LEN 4
26944 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_LEN 4
26948 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_LEN 4
27008 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_LEN 4
27012 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_LEN 4
27024 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_LEN 4
27028 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_LEN 4
27068 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_LEN 4
27072 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_LEN 4
27100 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_LEN 4
27104 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_LEN 4
27108 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_LEN 4
27112 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_LEN 4
27172 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_LEN 4
27176 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_LEN 4
27188 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_LEN 4
27192 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_LEN 4
27228 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_LEN 4
27232 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_LEN 4
27252 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_LEN 4
27256 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_LEN 4
27260 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_LEN 4
27262 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_IP_FRAG_LBN 0
27274 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_LBN 4
27294 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_LEN 4
27306 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_LEN 4
27310 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_LEN 4
27352 * 32-bits or within any NIC interface field that needs store the value
27354 * refer to m-ports.
27356 #define MAE_MPORT_SELECTOR_LEN 4
27357 /* Used to force the tools to output bitfield-style defines for this structure.
27359 #define MAE_MPORT_SELECTOR_FLAT_OFST 0
27360 #define MAE_MPORT_SELECTOR_FLAT_LEN 4
27361 /* enum: An m-port selector value that is guaranteed never to represent a real
27364 #define MAE_MPORT_SELECTOR_NULL 0x0
27365 /* enum: The m-port assigned to the calling client. */
27366 #define MAE_MPORT_SELECTOR_ASSIGNED 0x1000000
27367 #define MAE_MPORT_SELECTOR_TYPE_OFST 0
27371 #define MAE_MPORT_SELECTOR_TYPE_PPORT 0x2
27375 #define MAE_MPORT_SELECTOR_TYPE_FUNC 0x3
27377 #define MAE_MPORT_SELECTOR_TYPE_MPORT_ID 0x4
27378 /* enum: The MPORT assigned to a given PCIe function (see also FWRIVERHD-1108)
27380 #define MAE_MPORT_SELECTOR_TYPE_MH_FUNC 0x5
27382 #define MAE_MPORT_SELECTOR_TYPE_INVALID 0xff
27383 #define MAE_MPORT_SELECTOR_MPORT_ID_OFST 0
27384 #define MAE_MPORT_SELECTOR_MPORT_ID_LBN 0
27386 #define MAE_MPORT_SELECTOR_PPORT_ID_OFST 0
27387 #define MAE_MPORT_SELECTOR_PPORT_ID_LBN 0
27388 #define MAE_MPORT_SELECTOR_PPORT_ID_WIDTH 4
27389 #define MAE_MPORT_SELECTOR_FUNC_INTF_ID_OFST 0
27391 #define MAE_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
27392 #define MAE_MPORT_SELECTOR_HOST_PRIMARY 0x1 /* enum */
27393 #define MAE_MPORT_SELECTOR_NIC_EMBEDDED 0x2 /* enum */
27395 #define MAE_MPORT_SELECTOR_CALLER 0xf
27396 #define MAE_MPORT_SELECTOR_CALLER_INTF 0xf /* enum */
27397 #define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_OFST 0
27399 #define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
27400 #define MAE_MPORT_SELECTOR_FUNC_PF_ID_OFST 0
27403 #define MAE_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
27404 #define MAE_MPORT_SELECTOR_FUNC_VF_ID_LBN 0
27407 #define MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL 0xffff
27409 * client. - When used by a PF with VF_ID == VF_ID_NULL, the mport selector
27411 * clients use ASSIGNED to achieve this behaviour). - When used by a PF with
27413 * function. - When used by a VF with VF_ID == VF_ID_NULL, the mport selector
27414 * relates to the PF owning the calling function. - When used by a VF with
27416 * calling function. - Not meaningful used by a client that is not a PCIe
27419 #define MAE_MPORT_SELECTOR_FUNC_PF_ID_CALLER 0xff
27423 #define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_CALLER 0xf
27424 #define MAE_MPORT_SELECTOR_FLAT_LBN 0
27432 #define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_OFST 0
27433 #define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LEN 4
27434 #define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LBN 0
27437 #define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_OFST 4
27438 #define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_LEN 4
27444 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_OFST 0
27446 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_OFST 0
27447 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LEN 4
27448 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LBN 0
27450 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_OFST 4
27451 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LEN 4
27454 /* enum: Set FLAT to this value to obtain backward-compatible behaviour in
27459 #define MAE_LINK_ENDPOINT_SELECTOR_MAE_LINK_ENDPOINT_COMPAT 0x0
27460 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LBN 0
27466 * Describes capabilities of the MAE (Match-Action Engine)
27468 #define MC_CMD_MAE_GET_CAPS 0x140
27474 #define MC_CMD_MAE_GET_CAPS_IN_LEN 0
27482 #define MC_CMD_MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT_OFST 0
27483 #define MC_CMD_MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT_LEN 4
27484 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
27485 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
27486 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_OFST 4
27487 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_LBN 0
27489 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_OFST 4
27492 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_OFST 4
27495 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_OFST 4
27500 #define MC_CMD_MAE_GET_CAPS_OUT_COUNTERS_LEN 4
27503 #define MC_CMD_MAE_GET_CAPS_OUT_AR_COUNTERS_LEN 4
27509 #define MC_CMD_MAE_GET_CAPS_OUT_COUNTER_LISTS_LEN 4
27512 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_HEADER_LIMIT_LEN 4
27515 #define MC_CMD_MAE_GET_CAPS_OUT_RSVD_LEN 4
27518 #define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SETS_LEN 4
27521 #define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SET_LISTS_LEN 4
27524 #define MC_CMD_MAE_GET_CAPS_OUT_OUTER_RULES_LEN 4
27527 #define MC_CMD_MAE_GET_CAPS_OUT_ACTION_RULES_LEN 4
27532 #define MC_CMD_MAE_GET_CAPS_OUT_ACTION_PRIOS_LEN 4
27537 #define MC_CMD_MAE_GET_CAPS_OUT_OUTER_PRIOS_LEN 4
27544 #define MC_CMD_MAE_GET_CAPS_OUT_API_VER_LEN 4
27552 #define MC_CMD_MAE_GET_CAPS_V2_OUT_MATCH_FIELD_COUNT_OFST 0
27553 #define MC_CMD_MAE_GET_CAPS_V2_OUT_MATCH_FIELD_COUNT_LEN 4
27554 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
27555 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
27556 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_VXLAN_OFST 4
27557 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_VXLAN_LBN 0
27559 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_NVGRE_OFST 4
27562 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_GENEVE_OFST 4
27565 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_L2GRE_OFST 4
27570 #define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTERS_LEN 4
27573 #define MC_CMD_MAE_GET_CAPS_V2_OUT_AR_COUNTERS_LEN 4
27579 #define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_LISTS_LEN 4
27582 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_HEADER_LIMIT_LEN 4
27585 #define MC_CMD_MAE_GET_CAPS_V2_OUT_RSVD_LEN 4
27588 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SETS_LEN 4
27591 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SET_LISTS_LEN 4
27594 #define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_RULES_LEN 4
27597 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_RULES_LEN 4
27602 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_PRIOS_LEN 4
27607 #define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_PRIOS_LEN 4
27614 #define MC_CMD_MAE_GET_CAPS_V2_OUT_API_VER_LEN 4
27618 * COUNTER_TYPES_SUPPORTED==0x1). See also
27622 #define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_TYPES_SUPPORTED_LEN 4
27625 #define MC_CMD_MAE_GET_CAPS_V2_OUT_CT_COUNTERS_LEN 4
27633 #define MC_CMD_MAE_GET_CAPS_V3_OUT_MATCH_FIELD_COUNT_OFST 0
27634 #define MC_CMD_MAE_GET_CAPS_V3_OUT_MATCH_FIELD_COUNT_LEN 4
27635 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
27636 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
27637 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_VXLAN_OFST 4
27638 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_VXLAN_LBN 0
27640 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_NVGRE_OFST 4
27643 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_GENEVE_OFST 4
27646 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_L2GRE_OFST 4
27651 #define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTERS_LEN 4
27654 #define MC_CMD_MAE_GET_CAPS_V3_OUT_AR_COUNTERS_LEN 4
27660 #define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_LISTS_LEN 4
27663 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_HEADER_LIMIT_LEN 4
27666 #define MC_CMD_MAE_GET_CAPS_V3_OUT_RSVD_LEN 4
27669 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SETS_LEN 4
27672 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SET_LISTS_LEN 4
27675 #define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_RULES_LEN 4
27678 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_RULES_LEN 4
27683 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_PRIOS_LEN 4
27688 #define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_PRIOS_LEN 4
27695 #define MC_CMD_MAE_GET_CAPS_V3_OUT_API_VER_LEN 4
27699 * COUNTER_TYPES_SUPPORTED==0x1). See also
27703 #define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_TYPES_SUPPORTED_LEN 4
27706 #define MC_CMD_MAE_GET_CAPS_V3_OUT_CT_COUNTERS_LEN 4
27709 #define MC_CMD_MAE_GET_CAPS_V3_OUT_OR_COUNTERS_LEN 4
27714 * Get a level of support for match fields when used in match-action rules
27716 #define MC_CMD_MAE_GET_AR_CAPS 0x141
27722 #define MC_CMD_MAE_GET_AR_CAPS_IN_LEN 0
27725 #define MC_CMD_MAE_GET_AR_CAPS_OUT_LENMIN 4
27728 #define MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(num) (4+4*(num))
27729 #define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_NUM(len) (((len)-4)/4)
27731 #define MC_CMD_MAE_GET_AR_CAPS_OUT_COUNT_OFST 0
27732 #define MC_CMD_MAE_GET_AR_CAPS_OUT_COUNT_LEN 4
27737 #define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_OFST 4
27738 #define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_LEN 4
27739 #define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_MINNUM 0
27748 #define MC_CMD_MAE_GET_OR_CAPS 0x142
27754 #define MC_CMD_MAE_GET_OR_CAPS_IN_LEN 0
27757 #define MC_CMD_MAE_GET_OR_CAPS_OUT_LENMIN 4
27760 #define MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(num) (4+4*(num))
27761 #define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_NUM(len) (((len)-4)/4)
27763 #define MC_CMD_MAE_GET_OR_CAPS_OUT_COUNT_OFST 0
27764 #define MC_CMD_MAE_GET_OR_CAPS_OUT_COUNT_LEN 4
27766 #define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_OFST 4
27767 #define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_LEN 4
27768 #define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_MINNUM 0
27775 * Allocate match-action-engine counters, which can be referenced in various
27778 #define MC_CMD_MAE_COUNTER_ALLOC 0x143
27786 #define MC_CMD_MAE_COUNTER_ALLOC_IN_LEN 4
27788 #define MC_CMD_MAE_COUNTER_ALLOC_IN_REQUESTED_COUNT_OFST 0
27789 #define MC_CMD_MAE_COUNTER_ALLOC_IN_REQUESTED_COUNT_LEN 4
27794 #define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_REQUESTED_COUNT_OFST 0
27795 #define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_REQUESTED_COUNT_LEN 4
27797 #define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_COUNTER_TYPE_OFST 4
27798 #define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_COUNTER_TYPE_LEN 4
27806 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_LEN(num) (8+4*(num))
27807 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NUM(len) (((len)-8)/4)
27812 * counts wrap from 0xffffffff to 1.
27814 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_OFST 0
27815 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_LEN 4
27816 /* enum: Generation counter 0 is reserved and unused. */
27817 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_INVALID 0x0
27822 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_COUNT_OFST 4
27823 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_COUNT_LEN 4
27826 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4
27831 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NULL 0xffffffff
27836 * Free match-action-engine counters
27838 #define MC_CMD_MAE_COUNTER_FREE 0x144
27849 #define MC_CMD_MAE_COUNTER_FREE_IN_LEN(num) (4+4*(num))
27850 #define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_NUM(len) (((len)-4)/4)
27852 #define MC_CMD_MAE_COUNTER_FREE_IN_COUNTER_ID_COUNT_OFST 0
27853 #define MC_CMD_MAE_COUNTER_FREE_IN_COUNTER_ID_COUNT_LEN 4
27855 #define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_OFST 4
27856 #define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_LEN 4
27864 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_ID_COUNT_OFST 0
27865 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_ID_COUNT_LEN 4
27867 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_OFST 4
27868 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_LEN 4
27874 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_TYPE_LEN 4
27882 #define MC_CMD_MAE_COUNTER_FREE_OUT_LEN(num) (8+4*(num))
27883 #define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_NUM(len) (((len)-8)/4)
27895 #define MC_CMD_MAE_COUNTER_FREE_OUT_GENERATION_COUNT_OFST 0
27896 #define MC_CMD_MAE_COUNTER_FREE_OUT_GENERATION_COUNT_LEN 4
27902 #define MC_CMD_MAE_COUNTER_FREE_OUT_COUNTER_ID_COUNT_OFST 4
27903 #define MC_CMD_MAE_COUNTER_FREE_OUT_COUNTER_ID_COUNT_LEN 4
27911 #define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_LEN 4
27927 #define MC_CMD_MAE_COUNTERS_STREAM_START 0x151
27933 * with COUNTER_TYPES_MASK=0x1 (i.e. AR counters only).
27937 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_QID_OFST 0
27943 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_FLAGS_OFST 4
27944 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_FLAGS_LEN 4
27945 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_OFST 4
27946 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_LBN 0
27948 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_OFST 4
27955 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_QID_OFST 0
27961 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_FLAGS_OFST 4
27962 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_FLAGS_LEN 4
27963 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_ZERO_SQUASH_DISABLE_OFST 4
27964 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_ZERO_SQUASH_DISABLE_LBN 0
27966 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_STALL_EN_OFST 4
27971 * 0x3 requests both AR and CT counters. A value of zero is invalid. Counter
27979 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_TYPES_MASK_LEN 4
27982 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_LEN 4
27983 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_FLAGS_OFST 0
27984 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_FLAGS_LEN 4
27985 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_OFST 0
27986 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_LBN 0
27994 #define MC_CMD_MAE_COUNTERS_STREAM_STOP 0x152
28002 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_IN_QID_OFST 0
28006 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_LEN 4
28013 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_GENERATION_COUNT_OFST 0
28014 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_GENERATION_COUNT_LEN 4
28017 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LENMIN 4
28020 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LEN(num) (0+4*(num))
28021 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_NUM(len) (((len)-0)/4)
28023 * MAE_COUNTER_TYPE_AR==0, this response is backwards-compatible with V1. The
28029 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_OFST 0
28030 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_LEN 4
28043 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS 0x153
28049 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_LEN 4
28051 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_NUM_CREDITS_OFST 0
28052 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_NUM_CREDITS_LEN 4
28055 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_OUT_LEN 0
28061 * header must be constructed as a valid packet with 0-length payload.
28067 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC 0x148
28073 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMIN 4
28076 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LEN(num) (4+1*(num))
28077 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_NUM(len) (((len)-4)/1)
28078 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_ENCAP_TYPE_OFST 0
28079 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_ENCAP_TYPE_LEN 4
28080 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_OFST 4
28082 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MINNUM 0
28087 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_LEN 4
28088 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_OFST 0
28089 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_LEN 4
28093 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_NULL 0xffffffff
28100 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE 0x149
28110 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_NUM(len) (((len)-8)/1)
28111 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_EH_ID_OFST 0
28112 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_EH_ID_LEN 4
28113 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_ENCAP_TYPE_OFST 4
28114 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_ENCAP_TYPE_LEN 4
28117 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_MINNUM 0
28122 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_OUT_LEN 0
28129 #define MC_CMD_MAE_ENCAP_HEADER_FREE 0x14a
28135 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMIN 4
28138 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LEN(num) (0+4*(num))
28139 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_NUM(len) (((len)-0)/4)
28141 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_OFST 0
28142 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_LEN 4
28148 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LENMIN 4
28151 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LEN(num) (0+4*(num))
28152 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_NUM(len) (((len)-0)/4)
28154 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_OFST 0
28155 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_LEN 4
28169 #define MC_CMD_MAE_MAC_ADDR_ALLOC 0x15e
28177 #define MC_CMD_MAE_MAC_ADDR_ALLOC_IN_MAC_ADDR_OFST 0
28181 #define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_LEN 4
28182 #define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_OFST 0
28183 #define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_LEN 4
28187 #define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL 0xffffffff
28194 #define MC_CMD_MAE_MAC_ADDR_FREE 0x15f
28200 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_LENMIN 4
28203 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_LEN(num) (0+4*(num))
28204 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_NUM(len) (((len)-0)/4)
28206 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_OFST 0
28207 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_LEN 4
28213 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LENMIN 4
28216 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LEN(num) (0+4*(num))
28217 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_NUM(len) (((len)-0)/4)
28219 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_OFST 0
28220 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_LEN 4
28233 #define MC_CMD_MAE_ACTION_SET_ALLOC 0x14d
28240 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAGS_OFST 0
28241 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAGS_LEN 4
28242 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_OFST 0
28243 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_LBN 0
28245 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_OFST 0
28246 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_LBN 4
28248 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DECAP_OFST 0
28251 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_OFST 0
28254 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAG_OFST 0
28257 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_OFST 0
28260 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_OFST 0
28263 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_OFST 0
28266 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_OFST 0
28270 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_OFST 4
28281 /* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
28283 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_RSVD_LEN 4
28286 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID_LEN 4
28287 /* An m-port selector identifying the m-port that the modified packet should be
28292 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DELIVER_LEN 4
28297 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID_LEN 4
28299 * it can supply a COUNTER_ID instead of allocating a single-element counter
28302 * not valid to supply a non-NULL value for both COUNTER_LIST_ID and
28306 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_ID_LEN 4
28308 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_VALUE_LEN 4
28311 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID_LEN 4
28314 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_LEN 4
28321 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_OFST 0
28322 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_LEN 4
28323 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_OFST 0
28324 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_LBN 0
28326 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_OFST 0
28327 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_LBN 4
28329 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_OFST 0
28332 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_OFST 0
28335 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_OFST 0
28338 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_OFST 0
28341 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_OFST 0
28344 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_OFST 0
28347 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_OFST 0
28351 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_OFST 4
28362 /* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
28364 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_LEN 4
28367 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_LEN 4
28368 /* An m-port selector identifying the m-port that the modified packet should be
28373 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_LEN 4
28378 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_LEN 4
28380 * it can supply a COUNTER_ID instead of allocating a single-element counter
28383 * not valid to supply a non-NULL value for both COUNTER_LIST_ID and
28387 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_LEN 4
28389 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_LEN 4
28392 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_LEN 4
28395 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_LEN 4
28396 /* Source m-port ID to be reported for DO_SET_SRC_MPORT action. */
28398 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_LEN 4
28399 /* Actions for modifying the Differentiated Services Code-Point (DSCP) bits
28405 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_LBN 0
28422 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_LBN 0
28441 #define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN 4
28446 #define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_OFST 0
28447 #define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_LEN 4
28450 #define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_ACTION_SET_ID_NULL 0xffffffff
28456 #define MC_CMD_MAE_ACTION_SET_FREE 0x14e
28462 #define MC_CMD_MAE_ACTION_SET_FREE_IN_LENMIN 4
28465 #define MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(num) (0+4*(num))
28466 #define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_NUM(len) (((len)-0)/4)
28468 #define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_OFST 0
28469 #define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_LEN 4
28475 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_LENMIN 4
28478 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(num) (0+4*(num))
28479 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_NUM(len) (((len)-0)/4)
28481 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_OFST 0
28482 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_LEN 4
28496 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC 0x14f
28505 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LEN(num) (4+4*(num))
28506 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_NUM(len) (((len)-4)/4)
28508 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_COUNT_OFST 0
28509 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_COUNT_LEN 4
28519 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_OFST 4
28520 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_LEN 4
28526 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_LEN 4
28530 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_OFST 0
28531 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_LEN 4
28535 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ACTION_SET_LIST_ID_NULL 0xffffffff
28540 * Free match-action-engine redirect_lists
28542 #define MC_CMD_MAE_ACTION_SET_LIST_FREE 0x150
28548 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMIN 4
28551 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LEN(num) (0+4*(num))
28552 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_NUM(len) (((len)-0)/4)
28554 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_OFST 0
28555 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_LEN 4
28561 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LENMIN 4
28564 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LEN(num) (0+4*(num))
28565 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_NUM(len) (((len)-0)/4)
28567 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_OFST 0
28568 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_LEN 4
28580 #define MC_CMD_MAE_OUTER_RULE_INSERT 0x15a
28590 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_NUM(len) (((len)-16)/1)
28592 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE_OFST 0
28593 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE_LEN 4
28600 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_PRIO_OFST 4
28601 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_PRIO_LEN 4
28604 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LOOKUP_CONTROL_LEN 4
28606 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_CT_LBN 0
28617 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_TCP_FLAGS_INHIBIT_LBN 4
28627 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ACTION_CONTROL_LEN 4
28632 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_COUNTER_ID_LEN 4
28636 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_MINNUM 0
28641 #define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN 4
28642 #define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_OFST 0
28643 #define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN 4
28646 #define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL 0xffffffff
28652 #define MC_CMD_MAE_OUTER_RULE_REMOVE 0x15b
28658 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMIN 4
28661 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(num) (0+4*(num))
28662 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_NUM(len) (((len)-0)/4)
28664 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_OFST 0
28665 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_LEN 4
28671 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LENMIN 4
28674 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(num) (0+4*(num))
28675 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_NUM(len) (((len)-0)/4)
28677 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_OFST 0
28678 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_LEN 4
28688 #define MC_CMD_MAE_OUTER_RULE_UPDATE 0x17d
28696 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_OR_ID_OFST 0
28697 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_OR_ID_LEN 4
28699 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ENCAP_TYPE_OFST 4
28700 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ENCAP_TYPE_LEN 4
28705 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_ACTION_CONTROL_LEN 4
28707 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_DO_CT_LBN 0
28718 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_CT_TCP_FLAGS_INHIBIT_LBN 4
28730 #define MC_CMD_MAE_OUTER_RULE_UPDATE_IN_COUNTER_ID_LEN 4
28733 #define MC_CMD_MAE_OUTER_RULE_UPDATE_OUT_LEN 0
28737 #define MAE_ACTION_RULE_RESPONSE_ASL_ID_OFST 0
28738 #define MAE_ACTION_RULE_RESPONSE_ASL_ID_LEN 4
28739 #define MAE_ACTION_RULE_RESPONSE_ASL_ID_LBN 0
28741 /* Only one of ASL_ID or AS_ID may have a non-NULL value. */
28742 #define MAE_ACTION_RULE_RESPONSE_AS_ID_OFST 4
28743 #define MAE_ACTION_RULE_RESPONSE_AS_ID_LEN 4
28746 /* Controls lookup flow when this rule is hit. See sub-fields for details. More
28747 * info on the lookup sequence can be found in SF-122976-TC. It is an error to
28751 #define MAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_LEN 4
28753 #define MAE_ACTION_RULE_RESPONSE_DO_CT_LBN 0
28776 #define MAE_ACTION_RULE_RESPONSE_COUNTER_ID_LEN 4
28788 #define MC_CMD_MAE_ACTION_RULE_INSERT 0x15c
28798 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_NUM(len) (((len)-28)/1)
28800 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_PRIO_OFST 0
28801 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_PRIO_LEN 4
28803 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST 4
28807 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RSVD_LEN 4
28811 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_MINNUM 0
28816 #define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN 4
28817 #define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_OFST 0
28818 #define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN 4
28821 #define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL 0xffffffff
28829 #define MC_CMD_MAE_ACTION_RULE_UPDATE 0x15d
28837 #define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_AR_ID_OFST 0
28838 #define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_AR_ID_LEN 4
28840 #define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_RESPONSE_OFST 4
28844 #define MC_CMD_MAE_ACTION_RULE_UPDATE_OUT_LEN 0
28850 #define MC_CMD_MAE_ACTION_RULE_DELETE 0x155
28856 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMIN 4
28859 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(num) (0+4*(num))
28860 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_NUM(len) (((len)-0)/4)
28862 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_OFST 0
28863 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_LEN 4
28869 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LENMIN 4
28872 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(num) (0+4*(num))
28873 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_NUM(len) (((len)-0)/4)
28875 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_OFST 0
28876 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_LEN 4
28884 * Return the m-port corresponding to a selector.
28886 #define MC_CMD_MAE_MPORT_LOOKUP 0x160
28892 #define MC_CMD_MAE_MPORT_LOOKUP_IN_LEN 4
28893 #define MC_CMD_MAE_MPORT_LOOKUP_IN_MPORT_SELECTOR_OFST 0
28894 #define MC_CMD_MAE_MPORT_LOOKUP_IN_MPORT_SELECTOR_LEN 4
28897 #define MC_CMD_MAE_MPORT_LOOKUP_OUT_LEN 4
28898 #define MC_CMD_MAE_MPORT_LOOKUP_OUT_MPORT_ID_OFST 0
28899 #define MC_CMD_MAE_MPORT_LOOKUP_OUT_MPORT_ID_LEN 4
28904 * Allocates a m-port, which can subsequently be used in action rules as a
28907 #define MC_CMD_MAE_MPORT_ALLOC 0x163
28914 /* The type of m-port to allocate. Firmware may return ENOTSUP for certain
28917 #define MC_CMD_MAE_MPORT_ALLOC_IN_TYPE_OFST 0
28918 #define MC_CMD_MAE_MPORT_ALLOC_IN_TYPE_LEN 4
28919 /* enum: Traffic can be sent to this type of m-port using an override
28920 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
28921 * nominated m-port, and will be delivered with metadata identifying the alias
28922 * m-port.
28924 #define MC_CMD_MAE_MPORT_ALLOC_IN_MPORT_TYPE_ALIAS 0x1
28925 /* enum: This type of m-port has a VNIC attached. Queues can be created on this
28926 * VNIC by specifying the created m-port as an m-port selector at queue
28929 #define MC_CMD_MAE_MPORT_ALLOC_IN_MPORT_TYPE_VNIC 0x2
28930 /* 128-bit value for use by the driver. */
28931 #define MC_CMD_MAE_MPORT_ALLOC_IN_UUID_OFST 4
28936 /* The type of m-port to allocate. Firmware may return ENOTSUP for certain
28939 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_TYPE_OFST 0
28940 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_TYPE_LEN 4
28941 /* enum: Traffic can be sent to this type of m-port using an override
28942 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
28943 * nominated m-port, and will be delivered with metadata identifying the alias
28944 * m-port.
28946 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_MPORT_TYPE_ALIAS 0x1
28947 /* enum: This type of m-port has a VNIC attached. Queues can be created on this
28948 * VNIC by specifying the created m-port as an m-port selector at queue
28951 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_MPORT_TYPE_VNIC 0x2
28952 /* 128-bit value for use by the driver. */
28953 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_UUID_OFST 4
28955 /* An m-port selector identifying the VNIC to which traffic should be
28957 * the m-port assigned to the calling client).
28960 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_DELIVER_MPORT_LEN 4
28964 /* The type of m-port to allocate. Firmware may return ENOTSUP for certain
28967 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_TYPE_OFST 0
28968 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_TYPE_LEN 4
28969 /* enum: Traffic can be sent to this type of m-port using an override
28970 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
28971 * nominated m-port, and will be delivered with metadata identifying the alias
28972 * m-port.
28974 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_MPORT_TYPE_ALIAS 0x1
28975 /* enum: This type of m-port has a VNIC attached. Queues can be created on this
28976 * VNIC by specifying the created m-port as an m-port selector at queue
28979 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_MPORT_TYPE_VNIC 0x2
28980 /* 128-bit value for use by the driver. */
28981 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_UUID_OFST 4
28985 #define MC_CMD_MAE_MPORT_ALLOC_OUT_LEN 4
28986 /* ID of newly-allocated m-port. */
28987 #define MC_CMD_MAE_MPORT_ALLOC_OUT_MPORT_ID_OFST 0
28988 #define MC_CMD_MAE_MPORT_ALLOC_OUT_MPORT_ID_LEN 4
28992 /* ID of newly-allocated m-port. */
28993 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_MPORT_ID_OFST 0
28994 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_MPORT_ID_LEN 4
28996 * using an alias type m-port. This value is guaranteed unique on the VNIC
29001 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_LABEL_LEN 4
29004 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_LEN 4
29005 /* ID of newly-allocated m-port. */
29006 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_MPORT_ID_OFST 0
29007 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_MPORT_ID_LEN 4
29012 * Free a m-port which was previously allocated by the driver.
29014 #define MC_CMD_MAE_MPORT_FREE 0x164
29020 #define MC_CMD_MAE_MPORT_FREE_IN_LEN 4
29022 #define MC_CMD_MAE_MPORT_FREE_IN_MPORT_ID_OFST 0
29023 #define MC_CMD_MAE_MPORT_FREE_IN_MPORT_ID_LEN 4
29026 #define MC_CMD_MAE_MPORT_FREE_OUT_LEN 0
29030 #define MAE_MPORT_DESC_MPORT_ID_OFST 0
29031 #define MAE_MPORT_DESC_MPORT_ID_LEN 4
29032 #define MAE_MPORT_DESC_MPORT_ID_LBN 0
29035 #define MAE_MPORT_DESC_FLAGS_OFST 4
29036 #define MAE_MPORT_DESC_FLAGS_LEN 4
29040 #define MAE_MPORT_DESC_CALLER_FLAGS_LEN 4
29042 #define MAE_MPORT_DESC_CAN_RECEIVE_ON_LBN 0
29055 /* Not the ideal name; it's really the type of thing connected to the m-port */
29057 #define MAE_MPORT_DESC_MPORT_TYPE_LEN 4
29059 #define MAE_MPORT_DESC_MPORT_TYPE_NET_PORT 0x0
29060 /* enum: Adds metadata and delivers to another m-port */
29061 #define MAE_MPORT_DESC_MPORT_TYPE_ALIAS 0x1
29063 #define MAE_MPORT_DESC_MPORT_TYPE_VNIC 0x2
29066 /* 128-bit value available to drivers for m-port identification. */
29075 #define MAE_MPORT_DESC_RESERVED_LO_LEN 4
29079 #define MAE_MPORT_DESC_RESERVED_HI_LEN 4
29086 #define MAE_MPORT_DESC_NET_PORT_IDX_LEN 4
29089 /* The m-port delivered to */
29091 #define MAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_LEN 4
29096 #define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_LEN 4
29097 #define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_FUNCTION 0x1 /* enum */
29098 #define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_PLUGIN 0x2 /* enum */
29106 #define MAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_LEN 4
29116 #define MAE_MPORT_DESC_VF_IDX_NULL 0xffff
29121 #define MAE_MPORT_DESC_VNIC_PLUGIN_TBD_LEN 4
29127 #define MAE_MPORT_DESC_V2_MPORT_ID_OFST 0
29128 #define MAE_MPORT_DESC_V2_MPORT_ID_LEN 4
29129 #define MAE_MPORT_DESC_V2_MPORT_ID_LBN 0
29132 #define MAE_MPORT_DESC_V2_FLAGS_OFST 4
29133 #define MAE_MPORT_DESC_V2_FLAGS_LEN 4
29137 #define MAE_MPORT_DESC_V2_CALLER_FLAGS_LEN 4
29139 #define MAE_MPORT_DESC_V2_CAN_RECEIVE_ON_LBN 0
29152 /* Not the ideal name; it's really the type of thing connected to the m-port */
29154 #define MAE_MPORT_DESC_V2_MPORT_TYPE_LEN 4
29156 #define MAE_MPORT_DESC_V2_MPORT_TYPE_NET_PORT 0x0
29157 /* enum: Adds metadata and delivers to another m-port */
29158 #define MAE_MPORT_DESC_V2_MPORT_TYPE_ALIAS 0x1
29160 #define MAE_MPORT_DESC_V2_MPORT_TYPE_VNIC 0x2
29163 /* 128-bit value available to drivers for m-port identification. */
29172 #define MAE_MPORT_DESC_V2_RESERVED_LO_LEN 4
29176 #define MAE_MPORT_DESC_V2_RESERVED_HI_LEN 4
29183 #define MAE_MPORT_DESC_V2_NET_PORT_IDX_LEN 4
29186 /* The m-port delivered to */
29188 #define MAE_MPORT_DESC_V2_ALIAS_DELIVER_MPORT_ID_LEN 4
29193 #define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_LEN 4
29194 #define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_FUNCTION 0x1 /* enum */
29195 #define MAE_MPORT_DESC_V2_VNIC_CLIENT_TYPE_PLUGIN 0x2 /* enum */
29203 #define MAE_MPORT_DESC_V2_VNIC_FUNCTION_INTERFACE_LEN 4
29213 #define MAE_MPORT_DESC_V2_VF_IDX_NULL 0xffff
29218 #define MAE_MPORT_DESC_V2_VNIC_PLUGIN_TBD_LEN 4
29223 #define MAE_MPORT_DESC_V2_VNIC_CLIENT_HANDLE_LEN 4
29233 #define MC_CMD_MAE_MPORT_ENUMERATE 0x17c
29239 #define MC_CMD_MAE_MPORT_ENUMERATE_IN_LEN 0
29246 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_NUM(len) (((len)-8)/1)
29247 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_COUNT_OFST 0
29248 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_COUNT_LEN 4
29249 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_SIZEOF_MPORT_DESC_OFST 4
29250 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_SIZEOF_MPORT_DESC_LEN 4
29257 #define MC_CMD_MAE_MPORT_ENUMERATE_OUT_MPORT_DESC_DATA_MINNUM 0
29264 * Firmware maintains a per-client journal of mport creations and deletions.
29265 * This journal is clear-on-read, i.e. repeated calls of this command will
29269 #define MC_CMD_MAE_MPORT_READ_JOURNAL 0x147
29275 #define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_LEN 4
29277 #define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_OFST 0
29278 #define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_LEN 4
29285 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_NUM(len) (((len)-12)/1)
29287 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_OFST 0
29288 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_LEN 4
29289 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_OFST 0
29290 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_LBN 0
29293 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_OFST 4
29294 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_LEN 4
29296 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_LEN 4
29303 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MINNUM 0
29308 * describes the location and properties of one N-bit field within a wider
29309 * M-bit key/mask/response value.
29313 #define TABLE_FIELD_DESCR_FIELD_ID_OFST 0
29317 #define TABLE_FIELD_DESCR_FIELD_ID_LBN 0
29325 #define TABLE_FIELD_DESCR_WIDTH_OFST 4
29335 #define TABLE_FIELD_DESCR_MASK_NEVER 0x0
29337 #define TABLE_FIELD_DESCR_MASK_EXACT 0x1
29339 #define TABLE_FIELD_DESCR_MASK_TERNARY 0x2
29340 /* enum: Whole field match: mask must be all 1 bits, or all 0 bits. */
29341 #define TABLE_FIELD_DESCR_MASK_WHOLE_FIELD 0x3
29342 /* enum: Longest prefix match: mask must be 1 bit(s) followed by 0 bit(s). */
29343 #define TABLE_FIELD_DESCR_MASK_LPM 0x4
29347 * currently use version 0.
29359 #define MC_CMD_TABLE_LIST 0x1c9
29365 #define MC_CMD_TABLE_LIST_IN_LEN 4
29366 /* Index of the first item to be returned in the TABLE_ID sequence. (Set to 0
29370 #define MC_CMD_TABLE_LIST_IN_FIRST_TABLE_ID_INDEX_OFST 0
29371 #define MC_CMD_TABLE_LIST_IN_FIRST_TABLE_ID_INDEX_LEN 4
29374 #define MC_CMD_TABLE_LIST_OUT_LENMIN 4
29377 #define MC_CMD_TABLE_LIST_OUT_LEN(num) (4+4*(num))
29378 #define MC_CMD_TABLE_LIST_OUT_TABLE_ID_NUM(len) (((len)-4)/4)
29380 #define MC_CMD_TABLE_LIST_OUT_N_TABLES_OFST 0
29381 #define MC_CMD_TABLE_LIST_OUT_N_TABLES_LEN 4
29383 * items can be obtained by repeating the call with a non-zero
29386 #define MC_CMD_TABLE_LIST_OUT_TABLE_ID_OFST 4
29387 #define MC_CMD_TABLE_LIST_OUT_TABLE_ID_LEN 4
29388 #define MC_CMD_TABLE_LIST_OUT_TABLE_ID_MINNUM 0
29401 #define MC_CMD_TABLE_DESCRIPTOR 0x1ca
29409 #define MC_CMD_TABLE_DESCRIPTOR_IN_TABLE_ID_OFST 0
29410 #define MC_CMD_TABLE_DESCRIPTOR_IN_TABLE_ID_LEN 4
29413 /* Index of the first item to be returned in the FIELDS sequence. (Set to 0 for
29417 #define MC_CMD_TABLE_DESCRIPTOR_IN_FIRST_FIELDS_INDEX_OFST 4
29418 #define MC_CMD_TABLE_DESCRIPTOR_IN_FIRST_FIELDS_INDEX_LEN 4
29425 #define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_NUM(len) (((len)-20)/8)
29427 #define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_ENTRIES_OFST 0
29428 #define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_ENTRIES_LEN 4
29433 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_OFST 4
29439 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_DIRECT 0x1
29441 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_BCAM 0x2
29445 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_TCAM 0x3
29446 /* enum: STCAM (semi-TCAM) table: like a TCAM but entries shared a limited
29449 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_STCAM 0x4
29462 /* Number of priorities for STCAM or TCAM; otherwise 0. The priority of a table
29464 * 0=highest to N_PRIORITIES-1=lowest.
29468 /* Maximum number of masks for STCAM; otherwise 0. */
29475 #define MC_CMD_TABLE_DESCRIPTOR_OUT_ALLOC_MASKS_LBN 0
29480 * always set to 0 indicating the original MC_CMD_TABLE_INSERT/UPDATE/DELETE
29488 * by repeating the call with a non-zero FIRST_FIELDS_INDEX.
29493 #define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_LO_LEN 4
29497 #define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_HI_LEN 4
29513 #define MC_CMD_TABLE_INSERT 0x1cd
29522 #define MC_CMD_TABLE_INSERT_IN_LEN(num) (12+4*(num))
29523 #define MC_CMD_TABLE_INSERT_IN_DATA_NUM(len) (((len)-12)/4)
29525 #define MC_CMD_TABLE_INSERT_IN_TABLE_ID_OFST 0
29526 #define MC_CMD_TABLE_INSERT_IN_TABLE_ID_LEN 4
29530 #define MC_CMD_TABLE_INSERT_IN_KEY_WIDTH_OFST 4
29532 /* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM
29539 * data is required and this must be 0).
29543 /* Mask ID for STCAM table - used instead of mask data if the table descriptor
29544 * reports ALLOC_MASKS==1. Otherwise set to 0.
29548 /* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
29551 /* (32-bit alignment padding - set to 0) */
29554 /* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0)
29555 * data values. Each of these items is logically treated as a single wide N-bit
29558 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
29560 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
29563 #define MC_CMD_TABLE_INSERT_IN_DATA_LEN 4
29569 #define MC_CMD_TABLE_INSERT_OUT_LEN 0
29580 #define MC_CMD_TABLE_UPDATE 0x1ce
29589 #define MC_CMD_TABLE_UPDATE_IN_LEN(num) (12+4*(num))
29590 #define MC_CMD_TABLE_UPDATE_IN_DATA_NUM(len) (((len)-12)/4)
29592 #define MC_CMD_TABLE_UPDATE_IN_TABLE_ID_OFST 0
29593 #define MC_CMD_TABLE_UPDATE_IN_TABLE_ID_LEN 4
29597 #define MC_CMD_TABLE_UPDATE_IN_KEY_WIDTH_OFST 4
29599 /* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM
29606 * data is required and this must be 0).
29610 /* Mask ID for STCAM table - used instead of mask data if the table descriptor
29611 * reports ALLOC_MASKS==1. Otherwise set to 0.
29615 /* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
29618 /* (32-bit alignment padding - set to 0) */
29621 /* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0)
29622 * data values. Each of these items is logically treated as a single wide N-bit
29625 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
29627 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
29630 #define MC_CMD_TABLE_UPDATE_IN_DATA_LEN 4
29636 #define MC_CMD_TABLE_UPDATE_OUT_LEN 0
29647 #define MC_CMD_TABLE_DELETE 0x1cf
29656 #define MC_CMD_TABLE_DELETE_IN_LEN(num) (12+4*(num))
29657 #define MC_CMD_TABLE_DELETE_IN_DATA_NUM(len) (((len)-12)/4)
29659 #define MC_CMD_TABLE_DELETE_IN_TABLE_ID_OFST 0
29660 #define MC_CMD_TABLE_DELETE_IN_TABLE_ID_LEN 4
29664 #define MC_CMD_TABLE_DELETE_IN_KEY_WIDTH_OFST 4
29666 /* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM
29673 * data is required and this must be 0).
29677 /* Mask ID for STCAM table - used instead of mask data if the table descriptor
29678 * reports ALLOC_MASKS==1. Otherwise set to 0.
29682 /* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
29685 /* (32-bit alignment padding - set to 0) */
29688 /* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0)
29689 * data values. Each of these items is logically treated as a single wide N-bit
29692 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
29694 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
29697 #define MC_CMD_TABLE_DELETE_IN_DATA_LEN 4
29703 #define MC_CMD_TABLE_DELETE_OUT_LEN 0