sfc/falcon/net_driver.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
4  * Copyright 2005-2006 Fen Systems Ltd.
5  * Copyright 2005-2013 Solarflare Communications Inc.
63 /* Checksum generation is a per-queue option in hardware, so each
64  * queue visible to the networking core is backed by two hardware TX
82 #define EF4_RX_USR_BUF_SIZE	(2048 - 256)
85  * of every buffer.  Otherwise, we just need to ensure 4-byte
97  * struct ef4_buffer - A general-purpose DMA buffer
112  * struct ef4_special_buffer - DMA buffer entered into buffer table
119  * table entries (and so can be physically non-contiguous, although we
132  * struct ef4_tx_buffer - buffer state for a TX descriptor
135  * @option: When @flags & %EF4_TX_BUF_OPTION, a NIC-specific option descriptor.
161  * struct ef4_tx_queue - An Efx TX queue
163  * This is a ring buffer of TX fragments.
164  * Since the TX completion path always executes on the same
176  * @core_txq: The networking core TX queue structure
179  *	%EF4_TX_CB_ORDER into %EF4_TX_CB_SIZE-sized chunks.
188  *	only get the up-to-date value of @write_count if this
190  *	avoid cache-line ping-pong between the xmit path and the
192  * @merge_events: Number of TX merged completion events
201  *	only get the up-to-date value of read_count if this
203  *	avoid cache-line ping-pong between the xmit path and the
205  * @pushes: Number of times the TX push feature has been used
207  * @cb_packets: Number of times the TX copybreak feature has been used
210  *	@read_count bitwise-added to %EF4_EMPTY_COUNT_VALID; otherwise 0.
252 #define EF4_TX_CB_SIZE	(1 << EF4_TX_CB_ORDER) - NET_IP_ALIGN
255  * struct ef4_rx_buffer - An Efx RX data buffer
280  * struct ef4_rx_page_state - Page-based rx buffer state
295  * struct ef4_rx_queue - An Efx RX queue
322  * @min_fill: RX descriptor minimum non-zero fill level.
361  * struct ef4_channel - An Efx channel
363  * A channel comprises an event queue, at least one TX queue, at least
372  * @irq: IRQ number (MSI and MSI-X only)
402  * @tx_queue: TX queues for this channel
449  * struct ef4_msi_context - Context for each MSI
464  * struct ef4_channel_type - distinguishes traffic and extra channels
498 	STRING_TABLE_LOOKUP((efx)->loopback_mode, ef4_loopback_mode)
512 #define EF4_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EF4_INT_MODE_MSI)
524 /* Pseudo bit-mask flow control field */
530  * struct ef4_link_state - Current state of the link
532  * @fd: Link is full-duplex
546 	return left->up == right->up && left->fd == right->fd &&  in ef4_link_state_equal()
547 		left->fc == right->fc && left->speed == right->speed;  in ef4_link_state_equal()
551  * struct ef4_phy_operations - Efx PHY operations table
552  * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
553  *	efx->loopback_modes.
564  * @test_name: Get the name of a PHY-specific test/result
591  * enum ef4_phy_mode - PHY operating mode flags
593  * @PHY_MODE_TX_DISABLED: on with TX disabled
612  * struct ef4_hw_stat_desc - Description of a hardware statistic
615  * @dma_width: Width in bits (0 for non-DMA statistics)
616  * @offset: Offset within stats (ignored for non-DMA statistics)
627 /* Number of (single-bit) entries in a multicast filter hash */
637  * struct ef4_nic - an Efx NIC
664  * @tx_queue: TX DMA queues
668  * @extra_channel_types: Types of extra (non-traffic) channels that
672  * @txq_stop_thresh: TX queue fill level at or above which we stop it.
673  * @txq_wake_thresh: TX queue fill level at or below which we wake it.
674  * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
680  * @n_tx_channels: Number of channels used for TX
693  *	(valid only if channel->sync_timestamps_enabled; always negative)
699  * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
704  * @selftest_work: Work item for asynchronous self-test
720  * @phy_data: PHY private data (including PHY-specific stats)
726  * @unicast_filter: Flag for Falcon-arch simple unicast filter.
728  * @multicast_hash: Multicast hash table for Falcon-arch.
731  * @fc_disable: When non-zero flow control is disabled. Typically used to
737  * @loopback_selftest: Offline self-test private state
740  * @filter_state: Architecture-dependent filter table state
744  * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
906 	return efx->net_dev->reg_state == NETREG_REGISTERED;  in ef4_dev_registered()
911 	return efx->port_num;  in ef4_port_num()
923  * struct ef4_nic_type - Efx device type definition
940  * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
956  * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
969  * @irq_disable_non_ev: Disable non-event IRQs on the NIC.  Each event
975  * @tx_probe: Allocate resources for TX queue
976  * @tx_init: Initialise TX queue on the NIC
977  * @tx_remove: Free resources for TX queue
978  * @tx_write: Write TX descriptors and doorbell
1017  * @mtd_sync: Wait for write-back to complete on MTD partition.  This
1022  * @txd_ptr_tbl_base: TX descriptor ring base address
1026  * @evq_rptr_tbl_base: Event queue read-pointer table base address
1169 	EF4_BUG_ON_PARANOID(index >= efx->n_channels);  in ef4_get_channel()
1170 	return efx->channel[index];  in ef4_get_channel()
1175 	for (_channel = (_efx)->channel[0];				\
1177 	     _channel = (_channel->channel + 1 < (_efx)->n_channels) ?	\
1178 		     (_efx)->channel[_channel->channel + 1] : NULL)
1182 	for (_channel = (_efx)->channel[(_efx)->n_channels - 1];	\
1184 	     _channel = _channel->channel ?				\
1185 		     (_efx)->channel[_channel->channel - 1] : NULL)
1190 	EF4_BUG_ON_PARANOID(index >= efx->n_tx_channels ||  in ef4_get_tx_queue()
1192 	return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type];  in ef4_get_tx_queue()
1197 	return channel->channel - channel->efx->tx_channel_offset <  in ef4_channel_has_tx_queues()
1198 		channel->efx->n_tx_channels;  in ef4_channel_has_tx_queues()
1206 	return &channel->tx_queue[type];  in ef4_channel_get_tx_queue()
1211 	return !(tx_queue->efx->net_dev->num_tc < 2 &&  in ef4_tx_queue_used()
1212 		 tx_queue->queue & EF4_TXQ_TYPE_HIGHPRI);  in ef4_tx_queue_used()
1215 /* Iterate over all TX queues belonging to a channel */
1220 		for (_tx_queue = (_channel)->tx_queue;			\
1221 		     _tx_queue < (_channel)->tx_queue + EF4_TXQ_TYPES && \
1225 /* Iterate over all possible TX queues belonging to a channel */
1230 		for (_tx_queue = (_channel)->tx_queue;			\
1231 		     _tx_queue < (_channel)->tx_queue + EF4_TXQ_TYPES;	\
1236 	return channel->rx_queue.core_index >= 0;  in ef4_channel_has_rx_queue()
1243 	return &channel->rx_queue;  in ef4_channel_get_rx_queue()
1251 		for (_rx_queue = &(_channel)->rx_queue;			\
1263 	return ef4_rx_queue_channel(rx_queue)->channel;  in ef4_rx_queue_index()
1272 	return &rx_queue->buffer[index];  in ef4_rx_buffer()
1276  * EF4_MAX_FRAME_LEN - calculate maximum frame length
1284  * The 10G MAC requires 8-byte alignment on the frame
1287  * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1303 	const struct net_device *net_dev = efx->net_dev;  in ef4_supported_features()
1305 	return net_dev->features | net_dev->hw_features;  in ef4_supported_features()
1308 /* Get the current TX queue insert index. */
1312 	return tx_queue->insert_count & tx_queue->ptr_mask;  in ef4_tx_queue_get_insert_index()
1315 /* Get a TX buffer. */
1319 	return &tx_queue->buffer[ef4_tx_queue_get_insert_index(tx_queue)];  in __ef4_tx_queue_get_insert_buffer()
1322 /* Get a TX buffer, checking it's not currently in use. */
1329 	EF4_BUG_ON_PARANOID(buffer->len);  in ef4_tx_queue_get_insert_buffer()
1330 	EF4_BUG_ON_PARANOID(buffer->flags);  in ef4_tx_queue_get_insert_buffer()
1331 	EF4_BUG_ON_PARANOID(buffer->unmap_len);  in ef4_tx_queue_get_insert_buffer()