Lines Matching +full:multi +full:- +full:phase

1 /* SPDX-License-Identifier: GPL-2.0 */
77 #define SEEQ_TCMD_RB1      0x20 /* Register bank one w/multi-cast low byte */
78 #define SEEQ_TCMD_RB2      0x40 /* Register bank two w/multi-cast high byte */
89 #define SEEQ_HPIO_P1BITS  0x00000001 /* cycles to stay in P1 phase for PIO */
90 #define SEEQ_HPIO_P2BITS  0x00000060 /* cycles to stay in P2 phase for PIO */
91 #define SEEQ_HPIO_P3BITS  0x00000100 /* cycles to stay in P3 phase for PIO */
92 #define SEEQ_HDMA_D1BITS  0x00000006 /* cycles to stay in D1 phase for DMA */
93 #define SEEQ_HDMA_D2BITS  0x00000020 /* cycles to stay in D2 phase for DMA */
94 #define SEEQ_HDMA_D3BITS  0x00000000 /* cycles to stay in D3 phase for DMA */
99 #define SEEQ_HCTL_IPG     0x00001000 /* Inter-packet gap */
100 #define SEEQ_HCTL_RFIX    0x00002000 /* At rxdc, clear end-of-packet */