Lines Matching +full:0 +full:x3fffc000
12 #define RTASE_HW_VER_MASK 0x7C800000
22 #define RTASE_INTERFRAMEGAP 0x03
25 #define RTASE_PCI_REGS_SIZE 0x100
38 #define RTASE_MITI_TIME_COUNT_MASK GENMASK(3, 0)
56 RTASE_MAC0 = 0x0000,
57 RTASE_MAC4 = 0x0004,
58 RTASE_MAR0 = 0x0008,
59 RTASE_MAR1 = 0x000C,
60 RTASE_DTCCR0 = 0x0010,
61 RTASE_DTCCR4 = 0x0014,
62 #define RTASE_COUNTER_RESET BIT(0)
65 RTASE_FCR = 0x0018,
68 RTASE_LBK_CTRL = 0x001A,
70 #define RTASE_LBK_CLR BIT(0)
72 RTASE_TX_DESC_ADDR0 = 0x0020,
73 RTASE_TX_DESC_ADDR4 = 0x0024,
74 RTASE_TX_DESC_COMMAND = 0x0028,
78 RTASE_BOOT_CTL = 0x6004,
79 RTASE_CLKSW_SET = 0x6018,
81 RTASE_CHIP_CMD = 0x0037,
87 RTASE_IMR0 = 0x0038,
88 RTASE_ISR0 = 0x003C,
96 #define RTASE_ROK BIT(0)
98 RTASE_IMR1 = 0x0800,
99 RTASE_ISR1 = 0x0802,
102 #define RTASE_Q_ROK BIT(0)
104 RTASE_EPHY_ISR = 0x6014,
105 RTASE_EPHY_IMR = 0x6016,
107 RTASE_TX_CONFIG_0 = 0x0040,
109 /* DMA burst value (0-7) is shift this many bits */
112 RTASE_RX_CONFIG_0 = 0x0044,
122 #define RTASE_ACCEPT_ALLPHYS BIT(0)
128 RTASE_RX_CONFIG_1 = 0x0046,
134 #define RTASE_PCIE_RELOAD_EN BIT(0)
136 RTASE_EEM = 0x0050,
137 #define RTASE_EEM_UNLOCK 0xC0
139 RTASE_TDFNR = 0x0057,
140 RTASE_TPPOLL = 0x0090,
141 RTASE_PDR = 0x00B0,
142 RTASE_FIFOR = 0x00D3,
146 RTASE_RMS = 0x00DA,
147 RTASE_CPLUS_CMD = 0x00E0,
152 RTASE_Q0_RX_DESC_ADDR0 = 0x00E4,
153 RTASE_Q0_RX_DESC_ADDR4 = 0x00E8,
154 RTASE_Q1_RX_DESC_ADDR0 = 0x4000,
155 RTASE_Q1_RX_DESC_ADDR4 = 0x4004,
156 RTASE_MTPS = 0x00EC,
159 RTASE_MISC = 0x00F2,
162 RTASE_TFUN_CTRL = 0x0400,
163 #define RTASE_TX_NEW_DESC_FORMAT_EN BIT(0)
165 RTASE_TX_CONFIG_1 = 0x203E,
168 RTASE_TOKSEL = 0x2046,
169 RTASE_RFIFONFULL = 0x4406,
170 RTASE_INT_MITI_TX = 0x0A00,
171 RTASE_INT_MITI_RX = 0x0A80,
173 RTASE_VLAN_ENTRY_0 = 0xAC80,
186 #define RSVD_MASK 0x3FFFC000
198 /*------ offset 0 of tx descriptor ------*/
255 #define RTASE_VLAN_TAG_MASK GENMASK(15, 0)
256 #define RTASE_RX_PKT_SIZE_MASK GENMASK(13, 0)