Lines Matching refs:tp
78 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) argument
79 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) argument
80 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) argument
81 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) argument
82 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) argument
83 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) argument
684 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
713 static inline struct device *tp_to_dev(struct rtl8169_private *tp) in tp_to_dev() argument
715 return &tp->pci_dev->dev; in tp_to_dev()
718 static void rtl_lock_config_regs(struct rtl8169_private *tp) in rtl_lock_config_regs() argument
722 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); in rtl_lock_config_regs()
723 if (!--tp->cfg9346_usage_count) in rtl_lock_config_regs()
724 RTL_W8(tp, Cfg9346, Cfg9346_Lock); in rtl_lock_config_regs()
725 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); in rtl_lock_config_regs()
728 static void rtl_unlock_config_regs(struct rtl8169_private *tp) in rtl_unlock_config_regs() argument
732 raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags); in rtl_unlock_config_regs()
733 if (!tp->cfg9346_usage_count++) in rtl_unlock_config_regs()
734 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); in rtl_unlock_config_regs()
735 raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags); in rtl_unlock_config_regs()
738 static void rtl_pci_commit(struct rtl8169_private *tp) in rtl_pci_commit() argument
741 RTL_R8(tp, ChipCmd); in rtl_pci_commit()
744 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set) in rtl_mod_config2() argument
749 raw_spin_lock_irqsave(&tp->config25_lock, flags); in rtl_mod_config2()
750 val = RTL_R8(tp, Config2); in rtl_mod_config2()
751 RTL_W8(tp, Config2, (val & ~clear) | set); in rtl_mod_config2()
752 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); in rtl_mod_config2()
755 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set) in rtl_mod_config5() argument
760 raw_spin_lock_irqsave(&tp->config25_lock, flags); in rtl_mod_config5()
761 val = RTL_R8(tp, Config5); in rtl_mod_config5()
762 RTL_W8(tp, Config5, (val & ~clear) | set); in rtl_mod_config5()
763 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); in rtl_mod_config5()
766 static bool rtl_is_8125(struct rtl8169_private *tp) in rtl_is_8125() argument
768 return tp->mac_version >= RTL_GIGA_MAC_VER_61; in rtl_is_8125()
771 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) in rtl_is_8168evl_up() argument
773 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && in rtl_is_8168evl_up()
774 tp->mac_version != RTL_GIGA_MAC_VER_39 && in rtl_is_8168evl_up()
775 tp->mac_version <= RTL_GIGA_MAC_VER_53; in rtl_is_8168evl_up()
778 static bool rtl_supports_eee(struct rtl8169_private *tp) in rtl_supports_eee() argument
780 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && in rtl_supports_eee()
781 tp->mac_version != RTL_GIGA_MAC_VER_37 && in rtl_supports_eee()
782 tp->mac_version != RTL_GIGA_MAC_VER_39; in rtl_supports_eee()
785 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) in rtl_read_mac_from_reg() argument
790 mac[i] = RTL_R8(tp, reg + i); in rtl_read_mac_from_reg()
798 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, in rtl_loop_wait() argument
804 if (c->check(tp) == high) in rtl_loop_wait()
810 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", in rtl_loop_wait()
815 static bool rtl_loop_wait_high(struct rtl8169_private *tp, in rtl_loop_wait_high() argument
819 return rtl_loop_wait(tp, c, d, n, true); in rtl_loop_wait_high()
822 static bool rtl_loop_wait_low(struct rtl8169_private *tp, in rtl_loop_wait_low() argument
826 return rtl_loop_wait(tp, c, d, n, false); in rtl_loop_wait_low()
837 static bool name ## _check(struct rtl8169_private *tp)
839 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val) in rtl8168_led_mod_ctrl() argument
841 struct device *dev = tp_to_dev(tp); in rtl8168_led_mod_ctrl()
848 mutex_lock(&tp->led_lock); in rtl8168_led_mod_ctrl()
849 RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val); in rtl8168_led_mod_ctrl()
850 mutex_unlock(&tp->led_lock); in rtl8168_led_mod_ctrl()
857 int rtl8168_get_led_mode(struct rtl8169_private *tp) in rtl8168_get_led_mode() argument
859 struct device *dev = tp_to_dev(tp); in rtl8168_get_led_mode()
866 ret = RTL_R16(tp, LED_CTRL); in rtl8168_get_led_mode()
880 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode) in rtl8125_set_led_mode() argument
883 struct device *dev = tp_to_dev(tp); in rtl8125_set_led_mode()
891 mutex_lock(&tp->led_lock); in rtl8125_set_led_mode()
892 val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125; in rtl8125_set_led_mode()
893 RTL_W16(tp, reg, val | mode); in rtl8125_set_led_mode()
894 mutex_unlock(&tp->led_lock); in rtl8125_set_led_mode()
901 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index) in rtl8125_get_led_mode() argument
904 struct device *dev = tp_to_dev(tp); in rtl8125_get_led_mode()
911 ret = RTL_R16(tp, reg); in rtl8125_get_led_mode()
918 void r8169_get_led_name(struct rtl8169_private *tp, int idx, in r8169_get_led_name() argument
921 struct pci_dev *pdev = tp->pci_dev; in r8169_get_led_name()
940 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) in r8168fp_adjust_ocp_cmd() argument
944 (tp->mac_version == RTL_GIGA_MAC_VER_52 || in r8168fp_adjust_ocp_cmd()
945 tp->mac_version == RTL_GIGA_MAC_VER_53)) in r8168fp_adjust_ocp_cmd()
951 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; in DECLARE_RTL_COND()
954 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, in _rtl_eri_write() argument
962 RTL_W32(tp, ERIDR, val); in _rtl_eri_write()
963 r8168fp_adjust_ocp_cmd(tp, &cmd, type); in _rtl_eri_write()
964 RTL_W32(tp, ERIAR, cmd); in _rtl_eri_write()
966 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); in _rtl_eri_write()
969 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, in rtl_eri_write() argument
972 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); in rtl_eri_write()
975 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) in _rtl_eri_read() argument
979 r8168fp_adjust_ocp_cmd(tp, &cmd, type); in _rtl_eri_read()
980 RTL_W32(tp, ERIAR, cmd); in _rtl_eri_read()
982 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? in _rtl_eri_read()
983 RTL_R32(tp, ERIDR) : ~0; in _rtl_eri_read()
986 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) in rtl_eri_read() argument
988 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); in rtl_eri_read()
991 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) in rtl_w0w1_eri() argument
993 u32 val = rtl_eri_read(tp, addr); in rtl_w0w1_eri()
995 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); in rtl_w0w1_eri()
998 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) in rtl_eri_set_bits() argument
1000 rtl_w0w1_eri(tp, addr, p, 0); in rtl_eri_set_bits()
1003 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) in rtl_eri_clear_bits() argument
1005 rtl_w0w1_eri(tp, addr, 0, m); in rtl_eri_clear_bits()
1015 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; in DECLARE_RTL_COND()
1018 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) in r8168_phy_ocp_write() argument
1023 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); in r8168_phy_ocp_write()
1025 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); in r8168_phy_ocp_write()
1028 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) in r8168_phy_ocp_read() argument
1033 RTL_W32(tp, GPHY_OCP, reg << 15); in r8168_phy_ocp_read()
1035 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? in r8168_phy_ocp_read()
1036 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; in r8168_phy_ocp_read()
1039 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) in __r8168_mac_ocp_write() argument
1044 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); in __r8168_mac_ocp_write()
1047 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) in r8168_mac_ocp_write() argument
1051 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); in r8168_mac_ocp_write()
1052 __r8168_mac_ocp_write(tp, reg, data); in r8168_mac_ocp_write()
1053 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); in r8168_mac_ocp_write()
1056 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) in __r8168_mac_ocp_read() argument
1061 RTL_W32(tp, OCPDR, reg << 15); in __r8168_mac_ocp_read()
1063 return RTL_R32(tp, OCPDR); in __r8168_mac_ocp_read()
1066 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) in r8168_mac_ocp_read() argument
1071 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); in r8168_mac_ocp_read()
1072 val = __r8168_mac_ocp_read(tp, reg); in r8168_mac_ocp_read()
1073 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); in r8168_mac_ocp_read()
1078 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, in r8168_mac_ocp_modify() argument
1084 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); in r8168_mac_ocp_modify()
1085 data = __r8168_mac_ocp_read(tp, reg); in r8168_mac_ocp_modify()
1086 __r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); in r8168_mac_ocp_modify()
1087 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); in r8168_mac_ocp_modify()
1093 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value) in rtl8168g_phy_suspend_quirk() argument
1095 switch (tp->mac_version) { in rtl8168g_phy_suspend_quirk()
1098 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); in rtl8168g_phy_suspend_quirk()
1100 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); in rtl8168g_phy_suspend_quirk()
1107 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) in r8168g_mdio_write() argument
1110 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; in r8168g_mdio_write()
1114 if (tp->ocp_base != OCP_STD_PHY_BASE) in r8168g_mdio_write()
1117 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR) in r8168g_mdio_write()
1118 rtl8168g_phy_suspend_quirk(tp, value); in r8168g_mdio_write()
1120 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); in r8168g_mdio_write()
1123 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) in r8168g_mdio_read() argument
1126 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; in r8168g_mdio_read()
1128 if (tp->ocp_base != OCP_STD_PHY_BASE) in r8168g_mdio_read()
1131 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); in r8168g_mdio_read()
1134 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) in mac_mcu_write() argument
1137 tp->ocp_base = value << 4; in mac_mcu_write()
1141 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); in mac_mcu_write()
1144 static int mac_mcu_read(struct rtl8169_private *tp, int reg) in mac_mcu_read() argument
1146 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); in mac_mcu_read()
1151 return RTL_R32(tp, PHYAR) & 0x80000000; in DECLARE_RTL_COND()
1154 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) in r8169_mdio_write() argument
1156 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); in r8169_mdio_write()
1158 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); in r8169_mdio_write()
1166 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) in r8169_mdio_read() argument
1170 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); in r8169_mdio_read()
1172 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? in r8169_mdio_read()
1173 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; in r8169_mdio_read()
1186 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; in DECLARE_RTL_COND()
1191 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) in r8168dp_2_mdio_start() argument
1193 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_start()
1196 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) in r8168dp_2_mdio_stop() argument
1198 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_stop()
1201 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) in r8168dp_2_mdio_write() argument
1203 r8168dp_2_mdio_start(tp); in r8168dp_2_mdio_write()
1205 r8169_mdio_write(tp, reg, value); in r8168dp_2_mdio_write()
1207 r8168dp_2_mdio_stop(tp); in r8168dp_2_mdio_write()
1210 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) in r8168dp_2_mdio_read() argument
1218 r8168dp_2_mdio_start(tp); in r8168dp_2_mdio_read()
1220 value = r8169_mdio_read(tp, reg); in r8168dp_2_mdio_read()
1222 r8168dp_2_mdio_stop(tp); in r8168dp_2_mdio_read()
1227 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) in rtl_writephy() argument
1229 switch (tp->mac_version) { in rtl_writephy()
1232 r8168dp_2_mdio_write(tp, location, val); in rtl_writephy()
1235 r8168g_mdio_write(tp, location, val); in rtl_writephy()
1238 r8169_mdio_write(tp, location, val); in rtl_writephy()
1243 static int rtl_readphy(struct rtl8169_private *tp, int location) in rtl_readphy() argument
1245 switch (tp->mac_version) { in rtl_readphy()
1248 return r8168dp_2_mdio_read(tp, location); in rtl_readphy()
1250 return r8168g_mdio_read(tp, location); in rtl_readphy()
1252 return r8169_mdio_read(tp, location); in rtl_readphy()
1258 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; in DECLARE_RTL_COND()
1261 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) in rtl_ephy_write() argument
1263 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | in rtl_ephy_write()
1266 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); in rtl_ephy_write()
1271 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) in rtl_ephy_read() argument
1273 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); in rtl_ephy_read()
1275 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? in rtl_ephy_read()
1276 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; in rtl_ephy_read()
1279 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) in r8168dp_ocp_read() argument
1281 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); in r8168dp_ocp_read()
1282 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? in r8168dp_ocp_read()
1283 RTL_R32(tp, OCPDR) : ~0; in r8168dp_ocp_read()
1286 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) in r8168ep_ocp_read() argument
1288 return _rtl_eri_read(tp, reg, ERIAR_OOB); in r8168ep_ocp_read()
1291 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, in r8168dp_ocp_write() argument
1294 RTL_W32(tp, OCPDR, data); in r8168dp_ocp_write()
1295 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); in r8168dp_ocp_write()
1296 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); in r8168dp_ocp_write()
1299 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, in r8168ep_ocp_write() argument
1302 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, in r8168ep_ocp_write()
1306 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) in r8168dp_oob_notify() argument
1308 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); in r8168dp_oob_notify()
1310 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); in r8168dp_oob_notify()
1317 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) in rtl8168_get_ocp_reg() argument
1319 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; in rtl8168_get_ocp_reg()
1326 reg = rtl8168_get_ocp_reg(tp); in DECLARE_RTL_COND()
1328 return r8168dp_ocp_read(tp, reg) & 0x00000800; in DECLARE_RTL_COND()
1333 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; in DECLARE_RTL_COND()
1338 return RTL_R8(tp, IBISR0) & 0x20; in DECLARE_RTL_COND()
1341 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) in rtl8168ep_stop_cmac() argument
1343 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); in rtl8168ep_stop_cmac()
1344 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); in rtl8168ep_stop_cmac()
1345 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); in rtl8168ep_stop_cmac()
1346 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); in rtl8168ep_stop_cmac()
1349 static void rtl_dash_loop_wait(struct rtl8169_private *tp, in rtl_dash_loop_wait() argument
1353 if (!tp->dash_enabled) in rtl_dash_loop_wait()
1355 rtl_loop_wait(tp, c, usecs, n, high); in rtl_dash_loop_wait()
1358 static void rtl_dash_loop_wait_high(struct rtl8169_private *tp, in rtl_dash_loop_wait_high() argument
1362 rtl_dash_loop_wait(tp, c, d, n, true); in rtl_dash_loop_wait_high()
1365 static void rtl_dash_loop_wait_low(struct rtl8169_private *tp, in rtl_dash_loop_wait_low() argument
1369 rtl_dash_loop_wait(tp, c, d, n, false); in rtl_dash_loop_wait_low()
1372 static void rtl8168dp_driver_start(struct rtl8169_private *tp) in rtl8168dp_driver_start() argument
1374 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); in rtl8168dp_driver_start()
1375 rtl_dash_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); in rtl8168dp_driver_start()
1378 static void rtl8168ep_driver_start(struct rtl8169_private *tp) in rtl8168ep_driver_start() argument
1380 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); in rtl8168ep_driver_start()
1381 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); in rtl8168ep_driver_start()
1382 rtl_dash_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30); in rtl8168ep_driver_start()
1385 static void rtl8168_driver_start(struct rtl8169_private *tp) in rtl8168_driver_start() argument
1387 if (tp->dash_type == RTL_DASH_DP) in rtl8168_driver_start()
1388 rtl8168dp_driver_start(tp); in rtl8168_driver_start()
1390 rtl8168ep_driver_start(tp); in rtl8168_driver_start()
1393 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) in rtl8168dp_driver_stop() argument
1395 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); in rtl8168dp_driver_stop()
1396 rtl_dash_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); in rtl8168dp_driver_stop()
1399 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) in rtl8168ep_driver_stop() argument
1401 rtl8168ep_stop_cmac(tp); in rtl8168ep_driver_stop()
1402 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); in rtl8168ep_driver_stop()
1403 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); in rtl8168ep_driver_stop()
1404 rtl_dash_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); in rtl8168ep_driver_stop()
1407 static void rtl8168_driver_stop(struct rtl8169_private *tp) in rtl8168_driver_stop() argument
1409 if (tp->dash_type == RTL_DASH_DP) in rtl8168_driver_stop()
1410 rtl8168dp_driver_stop(tp); in rtl8168_driver_stop()
1412 rtl8168ep_driver_stop(tp); in rtl8168_driver_stop()
1415 static bool r8168dp_check_dash(struct rtl8169_private *tp) in r8168dp_check_dash() argument
1417 u16 reg = rtl8168_get_ocp_reg(tp); in r8168dp_check_dash()
1419 return r8168dp_ocp_read(tp, reg) & BIT(15); in r8168dp_check_dash()
1422 static bool r8168ep_check_dash(struct rtl8169_private *tp) in r8168ep_check_dash() argument
1424 return r8168ep_ocp_read(tp, 0x128) & BIT(0); in r8168ep_check_dash()
1427 static bool rtl_dash_is_enabled(struct rtl8169_private *tp) in rtl_dash_is_enabled() argument
1429 switch (tp->dash_type) { in rtl_dash_is_enabled()
1431 return r8168dp_check_dash(tp); in rtl_dash_is_enabled()
1433 return r8168ep_check_dash(tp); in rtl_dash_is_enabled()
1439 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp) in rtl_get_dash_type() argument
1441 switch (tp->mac_version) { in rtl_get_dash_type()
1452 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable) in rtl_set_d3_pll_down() argument
1454 switch (tp->mac_version) { in rtl_set_d3_pll_down()
1460 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); in rtl_set_d3_pll_down()
1462 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); in rtl_set_d3_pll_down()
1469 static void rtl_reset_packet_filter(struct rtl8169_private *tp) in rtl_reset_packet_filter() argument
1471 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); in rtl_reset_packet_filter()
1472 rtl_eri_set_bits(tp, 0xdc, BIT(0)); in rtl_reset_packet_filter()
1477 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; in DECLARE_RTL_COND()
1480 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) in rtl8168d_efuse_read() argument
1482 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); in rtl8168d_efuse_read()
1484 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? in rtl8168d_efuse_read()
1485 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; in rtl8168d_efuse_read()
1488 static u32 rtl_get_events(struct rtl8169_private *tp) in rtl_get_events() argument
1490 if (rtl_is_8125(tp)) in rtl_get_events()
1491 return RTL_R32(tp, IntrStatus_8125); in rtl_get_events()
1493 return RTL_R16(tp, IntrStatus); in rtl_get_events()
1496 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) in rtl_ack_events() argument
1498 if (rtl_is_8125(tp)) in rtl_ack_events()
1499 RTL_W32(tp, IntrStatus_8125, bits); in rtl_ack_events()
1501 RTL_W16(tp, IntrStatus, bits); in rtl_ack_events()
1504 static void rtl_irq_disable(struct rtl8169_private *tp) in rtl_irq_disable() argument
1506 if (rtl_is_8125(tp)) in rtl_irq_disable()
1507 RTL_W32(tp, IntrMask_8125, 0); in rtl_irq_disable()
1509 RTL_W16(tp, IntrMask, 0); in rtl_irq_disable()
1512 static void rtl_irq_enable(struct rtl8169_private *tp) in rtl_irq_enable() argument
1514 if (rtl_is_8125(tp)) in rtl_irq_enable()
1515 RTL_W32(tp, IntrMask_8125, tp->irq_mask); in rtl_irq_enable()
1517 RTL_W16(tp, IntrMask, tp->irq_mask); in rtl_irq_enable()
1520 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) in rtl8169_irq_mask_and_ack() argument
1522 rtl_irq_disable(tp); in rtl8169_irq_mask_and_ack()
1523 rtl_ack_events(tp, 0xffffffff); in rtl8169_irq_mask_and_ack()
1524 rtl_pci_commit(tp); in rtl8169_irq_mask_and_ack()
1527 static void rtl_link_chg_patch(struct rtl8169_private *tp) in rtl_link_chg_patch() argument
1529 struct phy_device *phydev = tp->phydev; in rtl_link_chg_patch()
1531 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || in rtl_link_chg_patch()
1532 tp->mac_version == RTL_GIGA_MAC_VER_38) { in rtl_link_chg_patch()
1534 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); in rtl_link_chg_patch()
1535 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1537 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1538 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1540 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1541 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); in rtl_link_chg_patch()
1543 rtl_reset_packet_filter(tp); in rtl_link_chg_patch()
1544 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || in rtl_link_chg_patch()
1545 tp->mac_version == RTL_GIGA_MAC_VER_36) { in rtl_link_chg_patch()
1547 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); in rtl_link_chg_patch()
1548 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1550 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1551 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); in rtl_link_chg_patch()
1553 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { in rtl_link_chg_patch()
1555 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); in rtl_link_chg_patch()
1556 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); in rtl_link_chg_patch()
1558 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); in rtl_link_chg_patch()
1567 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_get_wol() local
1570 wol->wolopts = tp->saved_wolopts; in rtl8169_get_wol()
1573 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) in __rtl8169_set_wol() argument
1591 rtl_unlock_config_regs(tp); in __rtl8169_set_wol()
1593 if (rtl_is_8168evl_up(tp)) { in __rtl8169_set_wol()
1596 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); in __rtl8169_set_wol()
1598 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); in __rtl8169_set_wol()
1599 } else if (rtl_is_8125(tp)) { in __rtl8169_set_wol()
1602 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); in __rtl8169_set_wol()
1604 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); in __rtl8169_set_wol()
1607 raw_spin_lock_irqsave(&tp->config25_lock, flags); in __rtl8169_set_wol()
1609 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; in __rtl8169_set_wol()
1612 RTL_W8(tp, cfg[i].reg, options); in __rtl8169_set_wol()
1614 raw_spin_unlock_irqrestore(&tp->config25_lock, flags); in __rtl8169_set_wol()
1616 switch (tp->mac_version) { in __rtl8169_set_wol()
1618 options = RTL_R8(tp, Config1) & ~PMEnable; in __rtl8169_set_wol()
1621 RTL_W8(tp, Config1, options); in __rtl8169_set_wol()
1627 rtl_mod_config2(tp, 0, PME_SIGNAL); in __rtl8169_set_wol()
1629 rtl_mod_config2(tp, PME_SIGNAL, 0); in __rtl8169_set_wol()
1635 rtl_lock_config_regs(tp); in __rtl8169_set_wol()
1637 device_set_wakeup_enable(tp_to_dev(tp), wolopts); in __rtl8169_set_wol()
1639 if (!tp->dash_enabled) { in __rtl8169_set_wol()
1640 rtl_set_d3_pll_down(tp, !wolopts); in __rtl8169_set_wol()
1641 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; in __rtl8169_set_wol()
1647 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_set_wol() local
1652 tp->saved_wolopts = wol->wolopts; in rtl8169_set_wol()
1653 __rtl8169_set_wol(tp, tp->saved_wolopts); in rtl8169_set_wol()
1661 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_get_drvinfo() local
1662 struct rtl_fw *rtl_fw = tp->rtl_fw; in rtl8169_get_drvinfo()
1665 strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); in rtl8169_get_drvinfo()
1680 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_fix_features() local
1686 tp->mac_version > RTL_GIGA_MAC_VER_06) in rtl8169_fix_features()
1692 static void rtl_set_rx_config_features(struct rtl8169_private *tp, in rtl_set_rx_config_features() argument
1695 u32 rx_config = RTL_R32(tp, RxConfig); in rtl_set_rx_config_features()
1702 if (rtl_is_8125(tp)) { in rtl_set_rx_config_features()
1709 RTL_W32(tp, RxConfig, rx_config); in rtl_set_rx_config_features()
1715 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_set_features() local
1717 rtl_set_rx_config_features(tp, features); in rtl8169_set_features()
1720 tp->cp_cmd |= RxChkSum; in rtl8169_set_features()
1722 tp->cp_cmd &= ~RxChkSum; in rtl8169_set_features()
1724 if (!rtl_is_8125(tp)) { in rtl8169_set_features()
1726 tp->cp_cmd |= RxVlan; in rtl8169_set_features()
1728 tp->cp_cmd &= ~RxVlan; in rtl8169_set_features()
1731 RTL_W16(tp, CPlusCmd, tp->cp_cmd); in rtl8169_set_features()
1732 rtl_pci_commit(tp); in rtl8169_set_features()
1754 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_get_regs() local
1755 u32 __iomem *data = tp->mmio_addr; in rtl8169_get_regs()
1791 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); in DECLARE_RTL_COND()
1794 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) in rtl8169_do_counters() argument
1796 u32 cmd = lower_32_bits(tp->counters_phys_addr); in rtl8169_do_counters()
1798 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr)); in rtl8169_do_counters()
1799 rtl_pci_commit(tp); in rtl8169_do_counters()
1800 RTL_W32(tp, CounterAddrLow, cmd); in rtl8169_do_counters()
1801 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); in rtl8169_do_counters()
1803 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); in rtl8169_do_counters()
1806 static void rtl8169_update_counters(struct rtl8169_private *tp) in rtl8169_update_counters() argument
1808 u8 val = RTL_R8(tp, ChipCmd); in rtl8169_update_counters()
1815 rtl8169_do_counters(tp, CounterDump); in rtl8169_update_counters()
1818 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) in rtl8169_init_counter_offsets() argument
1820 struct rtl8169_counters *counters = tp->counters; in rtl8169_init_counter_offsets()
1837 if (tp->tc_offset.inited) in rtl8169_init_counter_offsets()
1840 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) { in rtl8169_init_counter_offsets()
1841 rtl8169_do_counters(tp, CounterReset); in rtl8169_init_counter_offsets()
1843 rtl8169_update_counters(tp); in rtl8169_init_counter_offsets()
1844 tp->tc_offset.tx_errors = counters->tx_errors; in rtl8169_init_counter_offsets()
1845 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; in rtl8169_init_counter_offsets()
1846 tp->tc_offset.tx_aborted = counters->tx_aborted; in rtl8169_init_counter_offsets()
1847 tp->tc_offset.rx_missed = counters->rx_missed; in rtl8169_init_counter_offsets()
1850 tp->tc_offset.inited = true; in rtl8169_init_counter_offsets()
1856 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_get_ethtool_stats() local
1859 counters = tp->counters; in rtl8169_get_ethtool_stats()
1860 rtl8169_update_counters(tp); in rtl8169_get_ethtool_stats()
1940 rtl_coalesce_info(struct rtl8169_private *tp) in rtl_coalesce_info() argument
1944 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) in rtl_coalesce_info()
1950 if (tp->phydev->speed == SPEED_UNKNOWN) in rtl_coalesce_info()
1954 if (tp->phydev->speed == ci->speed) in rtl_coalesce_info()
1966 struct rtl8169_private *tp = netdev_priv(dev); in rtl_get_coalesce() local
1971 if (rtl_is_8125(tp)) in rtl_get_coalesce()
1977 ci = rtl_coalesce_info(tp); in rtl_get_coalesce()
1981 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; in rtl_get_coalesce()
1983 intrmit = RTL_R16(tp, IntrMitigate); in rtl_get_coalesce()
2002 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, in rtl_coalesce_choose_scale() argument
2008 ci = rtl_coalesce_info(tp); in rtl_coalesce_choose_scale()
2027 struct rtl8169_private *tp = netdev_priv(dev); in rtl_set_coalesce() local
2034 if (rtl_is_8125(tp)) in rtl_set_coalesce()
2041 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); in rtl_set_coalesce()
2073 RTL_W16(tp, IntrMitigate, w); in rtl_set_coalesce()
2076 if (rtl_is_8168evl_up(tp)) { in rtl_set_coalesce()
2079 tp->cp_cmd |= PktCntrDisable; in rtl_set_coalesce()
2081 tp->cp_cmd &= ~PktCntrDisable; in rtl_set_coalesce()
2084 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; in rtl_set_coalesce()
2085 RTL_W16(tp, CPlusCmd, tp->cp_cmd); in rtl_set_coalesce()
2086 rtl_pci_commit(tp); in rtl_set_coalesce()
2091 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp) in rtl_set_eee_txidle_timer() argument
2093 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; in rtl_set_eee_txidle_timer()
2095 switch (tp->mac_version) { in rtl_set_eee_txidle_timer()
2098 tp->tx_lpi_timer = timer_val; in rtl_set_eee_txidle_timer()
2099 r8168_mac_ocp_write(tp, 0xe048, timer_val); in rtl_set_eee_txidle_timer()
2105 tp->tx_lpi_timer = timer_val; in rtl_set_eee_txidle_timer()
2106 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val); in rtl_set_eee_txidle_timer()
2113 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp) in r8169_get_tx_lpi_timer_us() argument
2115 unsigned int speed = tp->phydev->speed; in r8169_get_tx_lpi_timer_us()
2116 unsigned int timer = tp->tx_lpi_timer; in r8169_get_tx_lpi_timer_us()
2127 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_get_eee() local
2130 if (!rtl_supports_eee(tp)) in rtl8169_get_eee()
2133 ret = phy_ethtool_get_eee(tp->phydev, data); in rtl8169_get_eee()
2137 data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp); in rtl8169_get_eee()
2144 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_set_eee() local
2146 if (!rtl_supports_eee(tp)) in rtl8169_set_eee()
2149 return phy_ethtool_set_eee(tp->phydev, data); in rtl8169_set_eee()
2166 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_get_pauseparam() local
2169 phy_get_pause(tp->phydev, &tx_pause, &rx_pause); in rtl8169_get_pauseparam()
2171 data->autoneg = tp->phydev->autoneg; in rtl8169_get_pauseparam()
2179 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_set_pauseparam() local
2184 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause); in rtl8169_set_pauseparam()
2354 static void rtl_release_firmware(struct rtl8169_private *tp) in rtl_release_firmware() argument
2356 if (tp->rtl_fw) { in rtl_release_firmware()
2357 rtl_fw_release_firmware(tp->rtl_fw); in rtl_release_firmware()
2358 kfree(tp->rtl_fw); in rtl_release_firmware()
2359 tp->rtl_fw = NULL; in rtl_release_firmware()
2363 void r8169_apply_firmware(struct rtl8169_private *tp) in r8169_apply_firmware() argument
2368 if (tp->rtl_fw) { in r8169_apply_firmware()
2369 rtl_fw_write_firmware(tp, tp->rtl_fw); in r8169_apply_firmware()
2371 tp->ocp_base = OCP_STD_PHY_BASE; in r8169_apply_firmware()
2374 phy_read_poll_timeout(tp->phydev, MII_BMCR, val, in r8169_apply_firmware()
2380 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) in rtl8168_config_eee_mac() argument
2383 if (tp->mac_version != RTL_GIGA_MAC_VER_38) in rtl8168_config_eee_mac()
2384 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); in rtl8168_config_eee_mac()
2386 rtl_eri_set_bits(tp, 0x1b0, 0x0003); in rtl8168_config_eee_mac()
2389 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp) in rtl8125a_config_eee_mac() argument
2391 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); in rtl8125a_config_eee_mac()
2392 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); in rtl8125a_config_eee_mac()
2395 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp) in rtl8125b_config_eee_mac() argument
2397 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); in rtl8125b_config_eee_mac()
2400 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr) in rtl_rar_exgmac_set() argument
2402 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); in rtl_rar_exgmac_set()
2403 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); in rtl_rar_exgmac_set()
2404 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); in rtl_rar_exgmac_set()
2405 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); in rtl_rar_exgmac_set()
2408 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) in rtl8168h_2_get_adc_bias_ioffset() argument
2412 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); in rtl8168h_2_get_adc_bias_ioffset()
2413 data1 = r8168_mac_ocp_read(tp, 0xdd02); in rtl8168h_2_get_adc_bias_ioffset()
2414 data2 = r8168_mac_ocp_read(tp, 0xdd00); in rtl8168h_2_get_adc_bias_ioffset()
2424 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) in rtl_schedule_task() argument
2426 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) in rtl_schedule_task()
2429 set_bit(flag, tp->wk.flags); in rtl_schedule_task()
2430 schedule_work(&tp->wk.work); in rtl_schedule_task()
2433 static void rtl8169_init_phy(struct rtl8169_private *tp) in rtl8169_init_phy() argument
2435 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); in rtl8169_init_phy()
2437 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { in rtl8169_init_phy()
2438 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); in rtl8169_init_phy()
2439 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); in rtl8169_init_phy()
2441 RTL_W8(tp, 0x82, 0x01); in rtl8169_init_phy()
2444 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && in rtl8169_init_phy()
2445 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && in rtl8169_init_phy()
2446 tp->pci_dev->subsystem_device == 0xe000) in rtl8169_init_phy()
2447 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); in rtl8169_init_phy()
2450 phy_speed_up(tp->phydev); in rtl8169_init_phy()
2452 genphy_soft_reset(tp->phydev); in rtl8169_init_phy()
2455 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr) in rtl_rar_set() argument
2457 rtl_unlock_config_regs(tp); in rtl_rar_set()
2459 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4)); in rtl_rar_set()
2460 rtl_pci_commit(tp); in rtl_rar_set()
2462 RTL_W32(tp, MAC0, get_unaligned_le32(addr)); in rtl_rar_set()
2463 rtl_pci_commit(tp); in rtl_rar_set()
2465 if (tp->mac_version == RTL_GIGA_MAC_VER_34) in rtl_rar_set()
2466 rtl_rar_exgmac_set(tp, addr); in rtl_rar_set()
2468 rtl_lock_config_regs(tp); in rtl_rar_set()
2473 struct rtl8169_private *tp = netdev_priv(dev); in rtl_set_mac_address() local
2480 rtl_rar_set(tp, dev->dev_addr); in rtl_set_mac_address()
2485 static void rtl_init_rxcfg(struct rtl8169_private *tp) in rtl_init_rxcfg() argument
2487 switch (tp->mac_version) { in rtl_init_rxcfg()
2490 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); in rtl_init_rxcfg()
2495 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); in rtl_init_rxcfg()
2498 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); in rtl_init_rxcfg()
2501 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); in rtl_init_rxcfg()
2506 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST | in rtl_init_rxcfg()
2510 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); in rtl_init_rxcfg()
2515 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) in rtl8169_init_ring_indexes() argument
2517 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; in rtl8169_init_ring_indexes()
2520 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) in r8168c_hw_jumbo_enable() argument
2522 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); in r8168c_hw_jumbo_enable()
2523 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); in r8168c_hw_jumbo_enable()
2526 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) in r8168c_hw_jumbo_disable() argument
2528 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); in r8168c_hw_jumbo_disable()
2529 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); in r8168c_hw_jumbo_disable()
2532 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) in r8168dp_hw_jumbo_enable() argument
2534 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); in r8168dp_hw_jumbo_enable()
2537 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) in r8168dp_hw_jumbo_disable() argument
2539 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); in r8168dp_hw_jumbo_disable()
2542 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) in r8168e_hw_jumbo_enable() argument
2544 RTL_W8(tp, MaxTxPacketSize, 0x24); in r8168e_hw_jumbo_enable()
2545 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); in r8168e_hw_jumbo_enable()
2546 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); in r8168e_hw_jumbo_enable()
2549 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) in r8168e_hw_jumbo_disable() argument
2551 RTL_W8(tp, MaxTxPacketSize, 0x3f); in r8168e_hw_jumbo_disable()
2552 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); in r8168e_hw_jumbo_disable()
2553 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); in r8168e_hw_jumbo_disable()
2556 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) in r8168b_1_hw_jumbo_enable() argument
2558 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); in r8168b_1_hw_jumbo_enable()
2561 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) in r8168b_1_hw_jumbo_disable() argument
2563 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); in r8168b_1_hw_jumbo_disable()
2566 static void rtl_jumbo_config(struct rtl8169_private *tp) in rtl_jumbo_config() argument
2568 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; in rtl_jumbo_config()
2571 rtl_unlock_config_regs(tp); in rtl_jumbo_config()
2572 switch (tp->mac_version) { in rtl_jumbo_config()
2576 r8168b_1_hw_jumbo_enable(tp); in rtl_jumbo_config()
2578 r8168b_1_hw_jumbo_disable(tp); in rtl_jumbo_config()
2584 r8168c_hw_jumbo_enable(tp); in rtl_jumbo_config()
2586 r8168c_hw_jumbo_disable(tp); in rtl_jumbo_config()
2591 r8168dp_hw_jumbo_enable(tp); in rtl_jumbo_config()
2593 r8168dp_hw_jumbo_disable(tp); in rtl_jumbo_config()
2597 r8168e_hw_jumbo_enable(tp); in rtl_jumbo_config()
2599 r8168e_hw_jumbo_disable(tp); in rtl_jumbo_config()
2604 rtl_lock_config_regs(tp); in rtl_jumbo_config()
2606 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) in rtl_jumbo_config()
2607 pcie_set_readrq(tp->pci_dev, readrq); in rtl_jumbo_config()
2612 tp->phydev->advertising); in rtl_jumbo_config()
2614 tp->phydev->advertising); in rtl_jumbo_config()
2615 phy_start_aneg(tp->phydev); in rtl_jumbo_config()
2621 return RTL_R8(tp, ChipCmd) & CmdReset; in DECLARE_RTL_COND()
2624 static void rtl_hw_reset(struct rtl8169_private *tp) in rtl_hw_reset() argument
2626 RTL_W8(tp, ChipCmd, CmdReset); in rtl_hw_reset()
2628 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); in rtl_hw_reset()
2631 static void rtl_request_firmware(struct rtl8169_private *tp) in rtl_request_firmware() argument
2636 if (tp->rtl_fw || !tp->fw_name) in rtl_request_firmware()
2647 rtl_fw->fw_name = tp->fw_name; in rtl_request_firmware()
2648 rtl_fw->dev = tp_to_dev(tp); in rtl_request_firmware()
2653 tp->rtl_fw = rtl_fw; in rtl_request_firmware()
2656 static void rtl_rx_close(struct rtl8169_private *tp) in rtl_rx_close() argument
2658 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); in rtl_rx_close()
2663 return RTL_R8(tp, TxPoll) & NPQ; in DECLARE_RTL_COND()
2668 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; in DECLARE_RTL_COND()
2673 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; in DECLARE_RTL_COND()
2679 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; in DECLARE_RTL_COND()
2682 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) in rtl_wait_txrx_fifo_empty() argument
2684 switch (tp->mac_version) { in rtl_wait_txrx_fifo_empty()
2686 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); in rtl_wait_txrx_fifo_empty()
2687 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); in rtl_wait_txrx_fifo_empty()
2690 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); in rtl_wait_txrx_fifo_empty()
2693 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); in rtl_wait_txrx_fifo_empty()
2694 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); in rtl_wait_txrx_fifo_empty()
2695 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42); in rtl_wait_txrx_fifo_empty()
2702 static void rtl_disable_rxdvgate(struct rtl8169_private *tp) in rtl_disable_rxdvgate() argument
2704 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); in rtl_disable_rxdvgate()
2707 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) in rtl_enable_rxdvgate() argument
2709 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); in rtl_enable_rxdvgate()
2711 rtl_wait_txrx_fifo_empty(tp); in rtl_enable_rxdvgate()
2714 static void rtl_wol_enable_rx(struct rtl8169_private *tp) in rtl_wol_enable_rx() argument
2716 if (tp->mac_version >= RTL_GIGA_MAC_VER_25) in rtl_wol_enable_rx()
2717 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | in rtl_wol_enable_rx()
2720 if (tp->mac_version >= RTL_GIGA_MAC_VER_40) in rtl_wol_enable_rx()
2721 rtl_disable_rxdvgate(tp); in rtl_wol_enable_rx()
2724 static void rtl_prepare_power_down(struct rtl8169_private *tp) in rtl_prepare_power_down() argument
2726 if (tp->dash_enabled) in rtl_prepare_power_down()
2729 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || in rtl_prepare_power_down()
2730 tp->mac_version == RTL_GIGA_MAC_VER_33) in rtl_prepare_power_down()
2731 rtl_ephy_write(tp, 0x19, 0xff64); in rtl_prepare_power_down()
2733 if (device_may_wakeup(tp_to_dev(tp))) { in rtl_prepare_power_down()
2734 phy_speed_down(tp->phydev, false); in rtl_prepare_power_down()
2735 rtl_wol_enable_rx(tp); in rtl_prepare_power_down()
2739 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) in rtl_set_tx_config_registers() argument
2744 if (rtl_is_8168evl_up(tp)) in rtl_set_tx_config_registers()
2747 RTL_W32(tp, TxConfig, val); in rtl_set_tx_config_registers()
2750 static void rtl_set_rx_max_size(struct rtl8169_private *tp) in rtl_set_rx_max_size() argument
2753 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); in rtl_set_rx_max_size()
2756 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) in rtl_set_rx_tx_desc_registers() argument
2763 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); in rtl_set_rx_tx_desc_registers()
2764 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); in rtl_set_rx_tx_desc_registers()
2765 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); in rtl_set_rx_tx_desc_registers()
2766 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); in rtl_set_rx_tx_desc_registers()
2769 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) in rtl8169_set_magic_reg() argument
2773 if (tp->mac_version == RTL_GIGA_MAC_VER_05) in rtl8169_set_magic_reg()
2775 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) in rtl8169_set_magic_reg()
2780 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) in rtl8169_set_magic_reg()
2783 RTL_W32(tp, 0x7c, val); in rtl8169_set_magic_reg()
2791 struct rtl8169_private *tp = netdev_priv(dev); in rtl_set_rx_mode() local
2799 tp->mac_version == RTL_GIGA_MAC_VER_35) { in rtl_set_rx_mode()
2812 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { in rtl_set_rx_mode()
2819 RTL_W32(tp, MAR0 + 4, mc_filter[1]); in rtl_set_rx_mode()
2820 RTL_W32(tp, MAR0 + 0, mc_filter[0]); in rtl_set_rx_mode()
2822 tmp = RTL_R32(tp, RxConfig); in rtl_set_rx_mode()
2823 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); in rtl_set_rx_mode()
2828 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; in DECLARE_RTL_COND()
2831 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) in rtl_csi_write() argument
2833 u32 func = PCI_FUNC(tp->pci_dev->devfn); in rtl_csi_write()
2835 RTL_W32(tp, CSIDR, value); in rtl_csi_write()
2836 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | in rtl_csi_write()
2839 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); in rtl_csi_write()
2842 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) in rtl_csi_read() argument
2844 u32 func = PCI_FUNC(tp->pci_dev->devfn); in rtl_csi_read()
2846 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | in rtl_csi_read()
2849 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? in rtl_csi_read()
2850 RTL_R32(tp, CSIDR) : ~0; in rtl_csi_read()
2853 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val) in rtl_set_aspm_entry_latency() argument
2855 struct pci_dev *pdev = tp->pci_dev; in rtl_set_aspm_entry_latency()
2868 netdev_notice_once(tp->dev, in rtl_set_aspm_entry_latency()
2870 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; in rtl_set_aspm_entry_latency()
2871 rtl_csi_write(tp, 0x070c, csi | val << 24); in rtl_set_aspm_entry_latency()
2874 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) in rtl_set_def_aspm_entry_latency() argument
2877 rtl_set_aspm_entry_latency(tp, 0x27); in rtl_set_def_aspm_entry_latency()
2886 static void __rtl_ephy_init(struct rtl8169_private *tp, in __rtl_ephy_init() argument
2892 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; in __rtl_ephy_init()
2893 rtl_ephy_write(tp, e->offset, w); in __rtl_ephy_init()
2898 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) argument
2900 static void rtl_disable_clock_request(struct rtl8169_private *tp) in rtl_disable_clock_request() argument
2902 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, in rtl_disable_clock_request()
2906 static void rtl_enable_clock_request(struct rtl8169_private *tp) in rtl_enable_clock_request() argument
2908 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, in rtl_enable_clock_request()
2912 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) in rtl_pcie_state_l2l3_disable() argument
2915 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); in rtl_pcie_state_l2l3_disable()
2918 static void rtl_enable_exit_l1(struct rtl8169_private *tp) in rtl_enable_exit_l1() argument
2928 switch (tp->mac_version) { in rtl_enable_exit_l1()
2930 rtl_eri_set_bits(tp, 0xd4, 0x1f00); in rtl_enable_exit_l1()
2933 rtl_eri_set_bits(tp, 0xd4, 0x0c00); in rtl_enable_exit_l1()
2936 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); in rtl_enable_exit_l1()
2943 static void rtl_disable_exit_l1(struct rtl8169_private *tp) in rtl_disable_exit_l1() argument
2945 switch (tp->mac_version) { in rtl_disable_exit_l1()
2947 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); in rtl_disable_exit_l1()
2950 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); in rtl_disable_exit_l1()
2957 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) in rtl_hw_aspm_clkreq_enable() argument
2961 if (tp->mac_version < RTL_GIGA_MAC_VER_32) in rtl_hw_aspm_clkreq_enable()
2965 if (enable && tp->aspm_manageable) { in rtl_hw_aspm_clkreq_enable()
2969 if (tp->mac_version == RTL_GIGA_MAC_VER_42 || in rtl_hw_aspm_clkreq_enable()
2970 tp->mac_version == RTL_GIGA_MAC_VER_43) in rtl_hw_aspm_clkreq_enable()
2973 rtl_mod_config5(tp, 0, ASPM_en); in rtl_hw_aspm_clkreq_enable()
2974 switch (tp->mac_version) { in rtl_hw_aspm_clkreq_enable()
2977 val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN; in rtl_hw_aspm_clkreq_enable()
2978 RTL_W8(tp, INT_CFG0_8125, val8); in rtl_hw_aspm_clkreq_enable()
2981 rtl_mod_config2(tp, 0, ClkReqEn); in rtl_hw_aspm_clkreq_enable()
2985 switch (tp->mac_version) { in rtl_hw_aspm_clkreq_enable()
2989 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); in rtl_hw_aspm_clkreq_enable()
2991 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); in rtl_hw_aspm_clkreq_enable()
2997 switch (tp->mac_version) { in rtl_hw_aspm_clkreq_enable()
3000 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); in rtl_hw_aspm_clkreq_enable()
3006 switch (tp->mac_version) { in rtl_hw_aspm_clkreq_enable()
3009 val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN; in rtl_hw_aspm_clkreq_enable()
3010 RTL_W8(tp, INT_CFG0_8125, val8); in rtl_hw_aspm_clkreq_enable()
3013 rtl_mod_config2(tp, ClkReqEn, 0); in rtl_hw_aspm_clkreq_enable()
3016 rtl_mod_config5(tp, ASPM_en, 0); in rtl_hw_aspm_clkreq_enable()
3020 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, in rtl_set_fifo_size() argument
3026 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); in rtl_set_fifo_size()
3027 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); in rtl_set_fifo_size()
3030 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, in rtl8168g_set_pause_thresholds() argument
3034 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); in rtl8168g_set_pause_thresholds()
3035 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); in rtl8168g_set_pause_thresholds()
3038 static void rtl_hw_start_8168b(struct rtl8169_private *tp) in rtl_hw_start_8168b() argument
3040 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8168b()
3043 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) in __rtl_hw_start_8168cp() argument
3045 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); in __rtl_hw_start_8168cp()
3047 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in __rtl_hw_start_8168cp()
3049 rtl_disable_clock_request(tp); in __rtl_hw_start_8168cp()
3052 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) in rtl_hw_start_8168cp_1() argument
3062 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168cp_1()
3064 rtl_ephy_init(tp, e_info_8168cp); in rtl_hw_start_8168cp_1()
3066 __rtl_hw_start_8168cp(tp); in rtl_hw_start_8168cp_1()
3069 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) in rtl_hw_start_8168cp_2() argument
3071 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168cp_2()
3073 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8168cp_2()
3076 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) in rtl_hw_start_8168cp_3() argument
3078 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168cp_3()
3080 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8168cp_3()
3083 RTL_W8(tp, DBG_REG, 0x20); in rtl_hw_start_8168cp_3()
3086 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) in rtl_hw_start_8168c_1() argument
3094 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168c_1()
3096 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); in rtl_hw_start_8168c_1()
3098 rtl_ephy_init(tp, e_info_8168c_1); in rtl_hw_start_8168c_1()
3100 __rtl_hw_start_8168cp(tp); in rtl_hw_start_8168c_1()
3103 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) in rtl_hw_start_8168c_2() argument
3110 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168c_2()
3112 rtl_ephy_init(tp, e_info_8168c_2); in rtl_hw_start_8168c_2()
3114 __rtl_hw_start_8168cp(tp); in rtl_hw_start_8168c_2()
3117 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) in rtl_hw_start_8168c_4() argument
3119 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168c_4()
3121 __rtl_hw_start_8168cp(tp); in rtl_hw_start_8168c_4()
3124 static void rtl_hw_start_8168d(struct rtl8169_private *tp) in rtl_hw_start_8168d() argument
3126 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168d()
3128 rtl_disable_clock_request(tp); in rtl_hw_start_8168d()
3131 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) in rtl_hw_start_8168d_4() argument
3140 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168d_4()
3142 rtl_ephy_init(tp, e_info_8168d_4); in rtl_hw_start_8168d_4()
3144 rtl_enable_clock_request(tp); in rtl_hw_start_8168d_4()
3147 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) in rtl_hw_start_8168e_1() argument
3165 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168e_1()
3167 rtl_ephy_init(tp, e_info_8168e_1); in rtl_hw_start_8168e_1()
3169 rtl_disable_clock_request(tp); in rtl_hw_start_8168e_1()
3172 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); in rtl_hw_start_8168e_1()
3173 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); in rtl_hw_start_8168e_1()
3175 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168e_1()
3178 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) in rtl_hw_start_8168e_2() argument
3187 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168e_2()
3189 rtl_ephy_init(tp, e_info_8168e_2); in rtl_hw_start_8168e_2()
3191 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168e_2()
3192 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); in rtl_hw_start_8168e_2()
3193 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); in rtl_hw_start_8168e_2()
3194 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); in rtl_hw_start_8168e_2()
3195 rtl_reset_packet_filter(tp); in rtl_hw_start_8168e_2()
3196 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); in rtl_hw_start_8168e_2()
3197 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); in rtl_hw_start_8168e_2()
3198 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); in rtl_hw_start_8168e_2()
3200 rtl_disable_clock_request(tp); in rtl_hw_start_8168e_2()
3202 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_start_8168e_2()
3204 rtl8168_config_eee_mac(tp); in rtl_hw_start_8168e_2()
3206 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); in rtl_hw_start_8168e_2()
3207 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); in rtl_hw_start_8168e_2()
3208 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168e_2()
3211 static void rtl_hw_start_8168f(struct rtl8169_private *tp) in rtl_hw_start_8168f() argument
3213 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168f()
3215 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168f()
3216 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); in rtl_hw_start_8168f()
3217 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); in rtl_hw_start_8168f()
3218 rtl_reset_packet_filter(tp); in rtl_hw_start_8168f()
3219 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); in rtl_hw_start_8168f()
3220 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); in rtl_hw_start_8168f()
3221 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); in rtl_hw_start_8168f()
3222 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); in rtl_hw_start_8168f()
3224 rtl_disable_clock_request(tp); in rtl_hw_start_8168f()
3226 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_start_8168f()
3227 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); in rtl_hw_start_8168f()
3228 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); in rtl_hw_start_8168f()
3229 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168f()
3231 rtl8168_config_eee_mac(tp); in rtl_hw_start_8168f()
3234 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) in rtl_hw_start_8168f_1() argument
3245 rtl_hw_start_8168f(tp); in rtl_hw_start_8168f_1()
3247 rtl_ephy_init(tp, e_info_8168f_1); in rtl_hw_start_8168f_1()
3250 static void rtl_hw_start_8411(struct rtl8169_private *tp) in rtl_hw_start_8411() argument
3260 rtl_hw_start_8168f(tp); in rtl_hw_start_8411()
3261 rtl_pcie_state_l2l3_disable(tp); in rtl_hw_start_8411()
3263 rtl_ephy_init(tp, e_info_8168f_1); in rtl_hw_start_8411()
3266 static void rtl_hw_start_8168g(struct rtl8169_private *tp) in rtl_hw_start_8168g() argument
3268 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168g()
3269 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); in rtl_hw_start_8168g()
3271 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168g()
3273 rtl_reset_packet_filter(tp); in rtl_hw_start_8168g()
3274 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); in rtl_hw_start_8168g()
3276 rtl_disable_rxdvgate(tp); in rtl_hw_start_8168g()
3278 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168g()
3279 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168g()
3281 rtl8168_config_eee_mac(tp); in rtl_hw_start_8168g()
3283 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); in rtl_hw_start_8168g()
3284 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8168g()
3286 rtl_pcie_state_l2l3_disable(tp); in rtl_hw_start_8168g()
3289 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) in rtl_hw_start_8168g_1() argument
3298 rtl_hw_start_8168g(tp); in rtl_hw_start_8168g_1()
3299 rtl_ephy_init(tp, e_info_8168g_1); in rtl_hw_start_8168g_1()
3302 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) in rtl_hw_start_8168g_2() argument
3316 rtl_hw_start_8168g(tp); in rtl_hw_start_8168g_2()
3317 rtl_ephy_init(tp, e_info_8168g_2); in rtl_hw_start_8168g_2()
3320 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp) in rtl8411b_fix_phy_down() argument
3341 raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags); in rtl8411b_fix_phy_down()
3343 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); in rtl8411b_fix_phy_down()
3344 raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags); in rtl8411b_fix_phy_down()
3347 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) in rtl_hw_start_8411_2() argument
3362 rtl_hw_start_8168g(tp); in rtl_hw_start_8411_2()
3364 rtl_ephy_init(tp, e_info_8411_2); in rtl_hw_start_8411_2()
3369 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); in rtl_hw_start_8411_2()
3370 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); in rtl_hw_start_8411_2()
3371 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); in rtl_hw_start_8411_2()
3372 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); in rtl_hw_start_8411_2()
3373 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); in rtl_hw_start_8411_2()
3374 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); in rtl_hw_start_8411_2()
3375 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); in rtl_hw_start_8411_2()
3376 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); in rtl_hw_start_8411_2()
3378 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); in rtl_hw_start_8411_2()
3380 rtl8411b_fix_phy_down(tp); in rtl_hw_start_8411_2()
3382 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); in rtl_hw_start_8411_2()
3384 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); in rtl_hw_start_8411_2()
3385 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); in rtl_hw_start_8411_2()
3386 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); in rtl_hw_start_8411_2()
3387 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); in rtl_hw_start_8411_2()
3388 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); in rtl_hw_start_8411_2()
3389 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); in rtl_hw_start_8411_2()
3390 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); in rtl_hw_start_8411_2()
3393 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) in rtl_hw_start_8168h_1() argument
3405 rtl_ephy_init(tp, e_info_8168h_1); in rtl_hw_start_8168h_1()
3407 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168h_1()
3408 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); in rtl_hw_start_8168h_1()
3410 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168h_1()
3412 rtl_reset_packet_filter(tp); in rtl_hw_start_8168h_1()
3414 rtl_eri_set_bits(tp, 0xdc, 0x001c); in rtl_hw_start_8168h_1()
3416 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8168h_1()
3418 rtl_disable_rxdvgate(tp); in rtl_hw_start_8168h_1()
3420 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168h_1()
3421 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168h_1()
3423 rtl8168_config_eee_mac(tp); in rtl_hw_start_8168h_1()
3425 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); in rtl_hw_start_8168h_1()
3426 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); in rtl_hw_start_8168h_1()
3428 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); in rtl_hw_start_8168h_1()
3430 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8168h_1()
3432 rtl_pcie_state_l2l3_disable(tp); in rtl_hw_start_8168h_1()
3434 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; in rtl_hw_start_8168h_1()
3440 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); in rtl_hw_start_8168h_1()
3443 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); in rtl_hw_start_8168h_1()
3444 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); in rtl_hw_start_8168h_1()
3445 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); in rtl_hw_start_8168h_1()
3446 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); in rtl_hw_start_8168h_1()
3448 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); in rtl_hw_start_8168h_1()
3449 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); in rtl_hw_start_8168h_1()
3450 r8168_mac_ocp_write(tp, 0xc094, 0x0000); in rtl_hw_start_8168h_1()
3451 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); in rtl_hw_start_8168h_1()
3454 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) in rtl_hw_start_8168ep() argument
3456 rtl8168ep_stop_cmac(tp); in rtl_hw_start_8168ep()
3458 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168ep()
3459 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); in rtl_hw_start_8168ep()
3461 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8168ep()
3463 rtl_reset_packet_filter(tp); in rtl_hw_start_8168ep()
3465 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8168ep()
3467 rtl_disable_rxdvgate(tp); in rtl_hw_start_8168ep()
3469 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168ep()
3470 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168ep()
3472 rtl8168_config_eee_mac(tp); in rtl_hw_start_8168ep()
3474 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); in rtl_hw_start_8168ep()
3476 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); in rtl_hw_start_8168ep()
3478 rtl_pcie_state_l2l3_disable(tp); in rtl_hw_start_8168ep()
3481 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) in rtl_hw_start_8168ep_3() argument
3490 rtl_ephy_init(tp, e_info_8168ep_3); in rtl_hw_start_8168ep_3()
3492 rtl_hw_start_8168ep(tp); in rtl_hw_start_8168ep_3()
3494 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); in rtl_hw_start_8168ep_3()
3495 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); in rtl_hw_start_8168ep_3()
3497 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); in rtl_hw_start_8168ep_3()
3498 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); in rtl_hw_start_8168ep_3()
3499 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); in rtl_hw_start_8168ep_3()
3502 static void rtl_hw_start_8117(struct rtl8169_private *tp) in rtl_hw_start_8117() argument
3510 rtl8168ep_stop_cmac(tp); in rtl_hw_start_8117()
3511 rtl_ephy_init(tp, e_info_8117); in rtl_hw_start_8117()
3513 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8117()
3514 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); in rtl_hw_start_8117()
3516 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8117()
3518 rtl_reset_packet_filter(tp); in rtl_hw_start_8117()
3520 rtl_eri_set_bits(tp, 0xd4, 0x0010); in rtl_hw_start_8117()
3522 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8117()
3524 rtl_disable_rxdvgate(tp); in rtl_hw_start_8117()
3526 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8117()
3527 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8117()
3529 rtl8168_config_eee_mac(tp); in rtl_hw_start_8117()
3531 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); in rtl_hw_start_8117()
3532 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); in rtl_hw_start_8117()
3534 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); in rtl_hw_start_8117()
3536 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8117()
3538 rtl_pcie_state_l2l3_disable(tp); in rtl_hw_start_8117()
3540 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; in rtl_hw_start_8117()
3545 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); in rtl_hw_start_8117()
3548 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); in rtl_hw_start_8117()
3549 r8168_mac_ocp_write(tp, 0xea80, 0x0003); in rtl_hw_start_8117()
3550 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); in rtl_hw_start_8117()
3551 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); in rtl_hw_start_8117()
3553 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); in rtl_hw_start_8117()
3554 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); in rtl_hw_start_8117()
3555 r8168_mac_ocp_write(tp, 0xc094, 0x0000); in rtl_hw_start_8117()
3556 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); in rtl_hw_start_8117()
3559 r8169_apply_firmware(tp); in rtl_hw_start_8117()
3562 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) in rtl_hw_start_8102e_1() argument
3576 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8102e_1()
3578 RTL_W8(tp, DBG_REG, FIX_NAK_1); in rtl_hw_start_8102e_1()
3580 RTL_W8(tp, Config1, in rtl_hw_start_8102e_1()
3582 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8102e_1()
3584 cfg1 = RTL_R8(tp, Config1); in rtl_hw_start_8102e_1()
3586 RTL_W8(tp, Config1, cfg1 & ~LEDS0); in rtl_hw_start_8102e_1()
3588 rtl_ephy_init(tp, e_info_8102e_1); in rtl_hw_start_8102e_1()
3591 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) in rtl_hw_start_8102e_2() argument
3593 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8102e_2()
3595 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); in rtl_hw_start_8102e_2()
3596 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8102e_2()
3599 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) in rtl_hw_start_8102e_3() argument
3601 rtl_hw_start_8102e_2(tp); in rtl_hw_start_8102e_3()
3603 rtl_ephy_write(tp, 0x03, 0xc2f9); in rtl_hw_start_8102e_3()
3606 static void rtl_hw_start_8401(struct rtl8169_private *tp) in rtl_hw_start_8401() argument
3615 rtl_ephy_init(tp, e_info_8401); in rtl_hw_start_8401()
3616 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8401()
3619 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) in rtl_hw_start_8105e_1() argument
3633 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8105e_1()
3636 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); in rtl_hw_start_8105e_1()
3638 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); in rtl_hw_start_8105e_1()
3639 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); in rtl_hw_start_8105e_1()
3641 rtl_ephy_init(tp, e_info_8105e_1); in rtl_hw_start_8105e_1()
3643 rtl_pcie_state_l2l3_disable(tp); in rtl_hw_start_8105e_1()
3646 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) in rtl_hw_start_8105e_2() argument
3648 rtl_hw_start_8105e_1(tp); in rtl_hw_start_8105e_2()
3649 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); in rtl_hw_start_8105e_2()
3652 static void rtl_hw_start_8402(struct rtl8169_private *tp) in rtl_hw_start_8402() argument
3659 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8402()
3662 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8402()
3664 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_start_8402()
3666 rtl_ephy_init(tp, e_info_8402); in rtl_hw_start_8402()
3668 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); in rtl_hw_start_8402()
3669 rtl_reset_packet_filter(tp); in rtl_hw_start_8402()
3670 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3671 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3672 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); in rtl_hw_start_8402()
3675 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3677 rtl_pcie_state_l2l3_disable(tp); in rtl_hw_start_8402()
3680 static void rtl_hw_start_8106(struct rtl8169_private *tp) in rtl_hw_start_8106() argument
3683 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8106()
3685 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); in rtl_hw_start_8106()
3686 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); in rtl_hw_start_8106()
3687 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); in rtl_hw_start_8106()
3690 rtl_set_aspm_entry_latency(tp, 0x2f); in rtl_hw_start_8106()
3692 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8106()
3695 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8106()
3697 rtl_pcie_state_l2l3_disable(tp); in rtl_hw_start_8106()
3702 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); in DECLARE_RTL_COND()
3705 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) in rtl_hw_start_8125_common() argument
3707 rtl_pcie_state_l2l3_disable(tp); in rtl_hw_start_8125_common()
3709 RTL_W16(tp, 0x382, 0x221b); in rtl_hw_start_8125_common()
3710 RTL_W8(tp, 0x4500, 0); in rtl_hw_start_8125_common()
3711 RTL_W16(tp, 0x4800, 0); in rtl_hw_start_8125_common()
3714 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); in rtl_hw_start_8125_common()
3716 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); in rtl_hw_start_8125_common()
3718 r8168_mac_ocp_write(tp, 0xc140, 0xffff); in rtl_hw_start_8125_common()
3719 r8168_mac_ocp_write(tp, 0xc142, 0xffff); in rtl_hw_start_8125_common()
3721 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); in rtl_hw_start_8125_common()
3722 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); in rtl_hw_start_8125_common()
3723 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); in rtl_hw_start_8125_common()
3726 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); in rtl_hw_start_8125_common()
3728 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || in rtl_hw_start_8125_common()
3729 tp->mac_version == RTL_GIGA_MAC_VER_66) in rtl_hw_start_8125_common()
3730 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); in rtl_hw_start_8125_common()
3732 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || in rtl_hw_start_8125_common()
3733 tp->mac_version == RTL_GIGA_MAC_VER_66) in rtl_hw_start_8125_common()
3734 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); in rtl_hw_start_8125_common()
3735 else if (tp->mac_version == RTL_GIGA_MAC_VER_63) in rtl_hw_start_8125_common()
3736 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); in rtl_hw_start_8125_common()
3738 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); in rtl_hw_start_8125_common()
3740 if (tp->mac_version == RTL_GIGA_MAC_VER_63) in rtl_hw_start_8125_common()
3741 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); in rtl_hw_start_8125_common()
3743 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); in rtl_hw_start_8125_common()
3745 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); in rtl_hw_start_8125_common()
3746 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); in rtl_hw_start_8125_common()
3747 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); in rtl_hw_start_8125_common()
3748 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); in rtl_hw_start_8125_common()
3749 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); in rtl_hw_start_8125_common()
3750 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); in rtl_hw_start_8125_common()
3751 if (tp->mac_version == RTL_GIGA_MAC_VER_65 || in rtl_hw_start_8125_common()
3752 tp->mac_version == RTL_GIGA_MAC_VER_66) in rtl_hw_start_8125_common()
3753 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); in rtl_hw_start_8125_common()
3755 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); in rtl_hw_start_8125_common()
3756 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); in rtl_hw_start_8125_common()
3757 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); in rtl_hw_start_8125_common()
3758 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); in rtl_hw_start_8125_common()
3760 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); in rtl_hw_start_8125_common()
3761 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); in rtl_hw_start_8125_common()
3763 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); in rtl_hw_start_8125_common()
3764 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); in rtl_hw_start_8125_common()
3766 r8168_mac_ocp_write(tp, 0xe098, 0xc302); in rtl_hw_start_8125_common()
3768 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); in rtl_hw_start_8125_common()
3770 if (tp->mac_version == RTL_GIGA_MAC_VER_61) in rtl_hw_start_8125_common()
3771 rtl8125a_config_eee_mac(tp); in rtl_hw_start_8125_common()
3773 rtl8125b_config_eee_mac(tp); in rtl_hw_start_8125_common()
3775 rtl_disable_rxdvgate(tp); in rtl_hw_start_8125_common()
3778 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp) in rtl_hw_start_8125a_2() argument
3796 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8125a_2()
3797 rtl_ephy_init(tp, e_info_8125a_2); in rtl_hw_start_8125a_2()
3798 rtl_hw_start_8125_common(tp); in rtl_hw_start_8125a_2()
3801 static void rtl_hw_start_8125b(struct rtl8169_private *tp) in rtl_hw_start_8125b() argument
3812 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8125b()
3813 rtl_ephy_init(tp, e_info_8125b); in rtl_hw_start_8125b()
3814 rtl_hw_start_8125_common(tp); in rtl_hw_start_8125b()
3817 static void rtl_hw_start_8126a(struct rtl8169_private *tp) in rtl_hw_start_8126a() argument
3819 rtl_set_def_aspm_entry_latency(tp); in rtl_hw_start_8126a()
3820 rtl_hw_start_8125_common(tp); in rtl_hw_start_8126a()
3823 static void rtl_hw_config(struct rtl8169_private *tp) in rtl_hw_config() argument
3869 if (hw_configs[tp->mac_version]) in rtl_hw_config()
3870 hw_configs[tp->mac_version](tp); in rtl_hw_config()
3873 static void rtl_hw_start_8125(struct rtl8169_private *tp) in rtl_hw_start_8125() argument
3877 RTL_W8(tp, INT_CFG0_8125, 0x00); in rtl_hw_start_8125()
3880 switch (tp->mac_version) { in rtl_hw_start_8125()
3883 RTL_W32(tp, i, 0); in rtl_hw_start_8125()
3889 RTL_W32(tp, i, 0); in rtl_hw_start_8125()
3890 RTL_W16(tp, INT_CFG1_8125, 0x0000); in rtl_hw_start_8125()
3896 rtl_hw_config(tp); in rtl_hw_start_8125()
3899 static void rtl_hw_start_8168(struct rtl8169_private *tp) in rtl_hw_start_8168() argument
3901 if (rtl_is_8168evl_up(tp)) in rtl_hw_start_8168()
3902 RTL_W8(tp, MaxTxPacketSize, EarlySize); in rtl_hw_start_8168()
3904 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); in rtl_hw_start_8168()
3906 rtl_hw_config(tp); in rtl_hw_start_8168()
3909 RTL_W16(tp, IntrMitigate, 0x0000); in rtl_hw_start_8168()
3912 static void rtl_hw_start_8169(struct rtl8169_private *tp) in rtl_hw_start_8169() argument
3914 RTL_W8(tp, EarlyTxThres, NoEarlyTx); in rtl_hw_start_8169()
3916 tp->cp_cmd |= PCIMulRW; in rtl_hw_start_8169()
3918 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || in rtl_hw_start_8169()
3919 tp->mac_version == RTL_GIGA_MAC_VER_03) in rtl_hw_start_8169()
3920 tp->cp_cmd |= EnAnaPLL; in rtl_hw_start_8169()
3922 RTL_W16(tp, CPlusCmd, tp->cp_cmd); in rtl_hw_start_8169()
3924 rtl8169_set_magic_reg(tp); in rtl_hw_start_8169()
3927 RTL_W16(tp, IntrMitigate, 0x0000); in rtl_hw_start_8169()
3930 static void rtl_hw_start(struct rtl8169_private *tp) in rtl_hw_start() argument
3932 rtl_unlock_config_regs(tp); in rtl_hw_start()
3934 rtl_hw_aspm_clkreq_enable(tp, false); in rtl_hw_start()
3935 RTL_W16(tp, CPlusCmd, tp->cp_cmd); in rtl_hw_start()
3937 rtl_set_eee_txidle_timer(tp); in rtl_hw_start()
3939 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) in rtl_hw_start()
3940 rtl_hw_start_8169(tp); in rtl_hw_start()
3941 else if (rtl_is_8125(tp)) in rtl_hw_start()
3942 rtl_hw_start_8125(tp); in rtl_hw_start()
3944 rtl_hw_start_8168(tp); in rtl_hw_start()
3946 rtl_enable_exit_l1(tp); in rtl_hw_start()
3947 rtl_hw_aspm_clkreq_enable(tp, true); in rtl_hw_start()
3948 rtl_set_rx_max_size(tp); in rtl_hw_start()
3949 rtl_set_rx_tx_desc_registers(tp); in rtl_hw_start()
3950 rtl_lock_config_regs(tp); in rtl_hw_start()
3952 rtl_jumbo_config(tp); in rtl_hw_start()
3955 rtl_pci_commit(tp); in rtl_hw_start()
3957 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); in rtl_hw_start()
3958 rtl_init_rxcfg(tp); in rtl_hw_start()
3959 rtl_set_tx_config_registers(tp); in rtl_hw_start()
3960 rtl_set_rx_config_features(tp, tp->dev->features); in rtl_hw_start()
3961 rtl_set_rx_mode(tp->dev); in rtl_hw_start()
3962 rtl_irq_enable(tp); in rtl_hw_start()
3967 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_change_mtu() local
3971 rtl_jumbo_config(tp); in rtl8169_change_mtu()
3972 rtl_set_eee_txidle_timer(tp); in rtl8169_change_mtu()
3987 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, in rtl8169_alloc_rx_data() argument
3990 struct device *d = tp_to_dev(tp); in rtl8169_alloc_rx_data()
4001 netdev_err(tp->dev, "Failed to map RX DMA!\n"); in rtl8169_alloc_rx_data()
4012 static void rtl8169_rx_clear(struct rtl8169_private *tp) in rtl8169_rx_clear() argument
4016 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { in rtl8169_rx_clear()
4017 dma_unmap_page(tp_to_dev(tp), in rtl8169_rx_clear()
4018 le64_to_cpu(tp->RxDescArray[i].addr), in rtl8169_rx_clear()
4020 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); in rtl8169_rx_clear()
4021 tp->Rx_databuff[i] = NULL; in rtl8169_rx_clear()
4022 tp->RxDescArray[i].addr = 0; in rtl8169_rx_clear()
4023 tp->RxDescArray[i].opts1 = 0; in rtl8169_rx_clear()
4027 static int rtl8169_rx_fill(struct rtl8169_private *tp) in rtl8169_rx_fill() argument
4034 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); in rtl8169_rx_fill()
4036 rtl8169_rx_clear(tp); in rtl8169_rx_fill()
4039 tp->Rx_databuff[i] = data; in rtl8169_rx_fill()
4043 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); in rtl8169_rx_fill()
4048 static int rtl8169_init_ring(struct rtl8169_private *tp) in rtl8169_init_ring() argument
4050 rtl8169_init_ring_indexes(tp); in rtl8169_init_ring()
4052 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); in rtl8169_init_ring()
4053 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); in rtl8169_init_ring()
4055 return rtl8169_rx_fill(tp); in rtl8169_init_ring()
4058 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) in rtl8169_unmap_tx_skb() argument
4060 struct ring_info *tx_skb = tp->tx_skb + entry; in rtl8169_unmap_tx_skb()
4061 struct TxDesc *desc = tp->TxDescArray + entry; in rtl8169_unmap_tx_skb()
4063 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, in rtl8169_unmap_tx_skb()
4069 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, in rtl8169_tx_clear_range() argument
4076 struct ring_info *tx_skb = tp->tx_skb + entry; in rtl8169_tx_clear_range()
4082 rtl8169_unmap_tx_skb(tp, entry); in rtl8169_tx_clear_range()
4089 static void rtl8169_tx_clear(struct rtl8169_private *tp) in rtl8169_tx_clear() argument
4091 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); in rtl8169_tx_clear()
4092 netdev_reset_queue(tp->dev); in rtl8169_tx_clear()
4095 static void rtl8169_cleanup(struct rtl8169_private *tp) in rtl8169_cleanup() argument
4097 napi_disable(&tp->napi); in rtl8169_cleanup()
4103 rtl8169_irq_mask_and_ack(tp); in rtl8169_cleanup()
4105 rtl_rx_close(tp); in rtl8169_cleanup()
4107 switch (tp->mac_version) { in rtl8169_cleanup()
4110 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); in rtl8169_cleanup()
4113 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); in rtl8169_cleanup()
4114 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); in rtl8169_cleanup()
4117 rtl_enable_rxdvgate(tp); in rtl8169_cleanup()
4121 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); in rtl8169_cleanup()
4126 rtl_hw_reset(tp); in rtl8169_cleanup()
4128 rtl8169_tx_clear(tp); in rtl8169_cleanup()
4129 rtl8169_init_ring_indexes(tp); in rtl8169_cleanup()
4132 static void rtl_reset_work(struct rtl8169_private *tp) in rtl_reset_work() argument
4136 netif_stop_queue(tp->dev); in rtl_reset_work()
4138 rtl8169_cleanup(tp); in rtl_reset_work()
4141 rtl8169_mark_to_asic(tp->RxDescArray + i); in rtl_reset_work()
4143 napi_enable(&tp->napi); in rtl_reset_work()
4144 rtl_hw_start(tp); in rtl_reset_work()
4149 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_tx_timeout() local
4151 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT); in rtl8169_tx_timeout()
4154 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, in rtl8169_tx_map() argument
4157 struct TxDesc *txd = tp->TxDescArray + entry; in rtl8169_tx_map()
4158 struct device *d = tp_to_dev(tp); in rtl8169_tx_map()
4167 netdev_err(tp->dev, "Failed to map TX data!\n"); in rtl8169_tx_map()
4181 tp->tx_skb[entry].len = len; in rtl8169_tx_map()
4186 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, in rtl8169_xmit_frags() argument
4199 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) in rtl8169_xmit_frags()
4206 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); in rtl8169_xmit_frags()
4231 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp, in rtl8125_quirk_udp_padto() argument
4236 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN && in rtl8125_quirk_udp_padto()
4258 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp, in rtl_quirk_packet_padto() argument
4263 padto = rtl8125_quirk_udp_padto(tp, skb); in rtl_quirk_packet_padto()
4265 switch (tp->mac_version) { in rtl_quirk_packet_padto()
4296 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, in rtl8169_tso_csum_v2() argument
4345 unsigned int padto = rtl_quirk_packet_padto(tp, skb); in rtl8169_tso_csum_v2()
4354 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp) in rtl_tx_slots_avail() argument
4356 return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx); in rtl_tx_slots_avail()
4360 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) in rtl_chip_supports_csum_v2() argument
4362 switch (tp->mac_version) { in rtl_chip_supports_csum_v2()
4371 static void rtl8169_doorbell(struct rtl8169_private *tp) in rtl8169_doorbell() argument
4373 if (rtl_is_8125(tp)) in rtl8169_doorbell()
4374 RTL_W16(tp, TxPoll_8125, BIT(0)); in rtl8169_doorbell()
4376 RTL_W8(tp, TxPoll, NPQ); in rtl8169_doorbell()
4382 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_start_xmit() local
4383 unsigned int entry = tp->cur_tx % NUM_TX_DESC; in rtl8169_start_xmit()
4389 if (unlikely(!rtl_tx_slots_avail(tp))) { in rtl8169_start_xmit()
4399 if (!rtl_chip_supports_csum_v2(tp)) in rtl8169_start_xmit()
4401 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) in rtl8169_start_xmit()
4404 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, in rtl8169_start_xmit()
4408 txd_first = tp->TxDescArray + entry; in rtl8169_start_xmit()
4412 if (rtl8169_xmit_frags(tp, skb, opts, entry)) in rtl8169_start_xmit()
4417 txd_last = tp->TxDescArray + entry; in rtl8169_start_xmit()
4419 tp->tx_skb[entry].skb = skb; in rtl8169_start_xmit()
4433 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1); in rtl8169_start_xmit()
4435 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), in rtl8169_start_xmit()
4439 rtl8169_doorbell(tp); in rtl8169_start_xmit()
4444 rtl8169_unmap_tx_skb(tp, entry); in rtl8169_start_xmit()
4486 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_features_check() local
4489 if (tp->mac_version == RTL_GIGA_MAC_VER_34) in rtl8169_features_check()
4493 rtl_chip_supports_csum_v2(tp)) in rtl8169_features_check()
4500 if (rtl_quirk_packet_padto(tp, skb)) in rtl8169_features_check()
4504 rtl_chip_supports_csum_v2(tp)) in rtl8169_features_check()
4513 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_pcierr_interrupt() local
4514 struct pci_dev *pdev = tp->pci_dev; in rtl8169_pcierr_interrupt()
4526 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); in rtl8169_pcierr_interrupt()
4529 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, in rtl_tx() argument
4535 dirty_tx = tp->dirty_tx; in rtl_tx()
4537 while (READ_ONCE(tp->cur_tx) != dirty_tx) { in rtl_tx()
4541 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); in rtl_tx()
4545 skb = tp->tx_skb[entry].skb; in rtl_tx()
4546 rtl8169_unmap_tx_skb(tp, entry); in rtl_tx()
4556 if (tp->dirty_tx != dirty_tx) { in rtl_tx()
4558 WRITE_ONCE(tp->dirty_tx, dirty_tx); in rtl_tx()
4561 rtl_tx_slots_avail(tp), in rtl_tx()
4571 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) in rtl_tx()
4572 rtl8169_doorbell(tp); in rtl_tx()
4591 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget) in rtl_rx() argument
4593 struct device *d = tp_to_dev(tp); in rtl_rx()
4596 for (count = 0; count < budget; count++, tp->cur_rx++) { in rtl_rx()
4597 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC; in rtl_rx()
4598 struct RxDesc *desc = tp->RxDescArray + entry; in rtl_rx()
4643 skb = napi_alloc_skb(&tp->napi, pkt_size); in rtl_rx()
4650 rx_buf = page_address(tp->Rx_databuff[entry]); in rtl_rx()
4667 napi_gro_receive(&tp->napi, skb); in rtl_rx()
4679 struct rtl8169_private *tp = dev_instance; in rtl8169_interrupt() local
4680 u32 status = rtl_get_events(tp); in rtl8169_interrupt()
4682 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) in rtl8169_interrupt()
4687 tp->mac_version <= RTL_GIGA_MAC_VER_06)) { in rtl8169_interrupt()
4688 rtl8169_pcierr_interrupt(tp->dev); in rtl8169_interrupt()
4693 phy_mac_interrupt(tp->phydev); in rtl8169_interrupt()
4696 tp->mac_version == RTL_GIGA_MAC_VER_11)) { in rtl8169_interrupt()
4697 netif_stop_queue(tp->dev); in rtl8169_interrupt()
4698 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); in rtl8169_interrupt()
4701 rtl_irq_disable(tp); in rtl8169_interrupt()
4702 napi_schedule(&tp->napi); in rtl8169_interrupt()
4704 rtl_ack_events(tp, status); in rtl8169_interrupt()
4711 struct rtl8169_private *tp = in rtl_task() local
4717 if (!test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) in rtl_task()
4720 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) { in rtl_task()
4722 if (RTL_R32(tp, TxConfig) == ~0) { in rtl_task()
4723 ret = pci_reset_bus(tp->pci_dev); in rtl_task()
4725 netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n"); in rtl_task()
4726 netif_device_detach(tp->dev); in rtl_task()
4732 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 | in rtl_task()
4735 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n"); in rtl_task()
4739 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) { in rtl_task()
4741 rtl_reset_work(tp); in rtl_task()
4742 netif_wake_queue(tp->dev); in rtl_task()
4743 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) { in rtl_task()
4744 rtl_reset_work(tp); in rtl_task()
4752 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); in rtl8169_poll() local
4753 struct net_device *dev = tp->dev; in rtl8169_poll()
4756 rtl_tx(dev, tp, budget); in rtl8169_poll()
4758 work_done = rtl_rx(dev, tp, budget); in rtl8169_poll()
4761 rtl_irq_enable(tp); in rtl8169_poll()
4768 struct rtl8169_private *tp = netdev_priv(ndev); in r8169_phylink_handler() local
4769 struct device *d = tp_to_dev(tp); in r8169_phylink_handler()
4772 rtl_link_chg_patch(tp); in r8169_phylink_handler()
4774 netif_wake_queue(tp->dev); in r8169_phylink_handler()
4777 if (rtl_is_8125(tp)) in r8169_phylink_handler()
4778 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE); in r8169_phylink_handler()
4782 phy_print_status(tp->phydev); in r8169_phylink_handler()
4785 static int r8169_phy_connect(struct rtl8169_private *tp) in r8169_phy_connect() argument
4787 struct phy_device *phydev = tp->phydev; in r8169_phy_connect()
4791 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : in r8169_phy_connect()
4794 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, in r8169_phy_connect()
4799 if (!tp->supports_gmii) in r8169_phy_connect()
4807 static void rtl8169_down(struct rtl8169_private *tp) in rtl8169_down() argument
4810 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); in rtl8169_down()
4812 phy_stop(tp->phydev); in rtl8169_down()
4814 rtl8169_update_counters(tp); in rtl8169_down()
4816 pci_clear_master(tp->pci_dev); in rtl8169_down()
4817 rtl_pci_commit(tp); in rtl8169_down()
4819 rtl8169_cleanup(tp); in rtl8169_down()
4820 rtl_disable_exit_l1(tp); in rtl8169_down()
4821 rtl_prepare_power_down(tp); in rtl8169_down()
4823 if (tp->dash_type != RTL_DASH_NONE) in rtl8169_down()
4824 rtl8168_driver_stop(tp); in rtl8169_down()
4827 static void rtl8169_up(struct rtl8169_private *tp) in rtl8169_up() argument
4829 if (tp->dash_type != RTL_DASH_NONE) in rtl8169_up()
4830 rtl8168_driver_start(tp); in rtl8169_up()
4832 pci_set_master(tp->pci_dev); in rtl8169_up()
4833 phy_init_hw(tp->phydev); in rtl8169_up()
4834 phy_resume(tp->phydev); in rtl8169_up()
4835 rtl8169_init_phy(tp); in rtl8169_up()
4836 napi_enable(&tp->napi); in rtl8169_up()
4837 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); in rtl8169_up()
4838 rtl_reset_work(tp); in rtl8169_up()
4840 phy_start(tp->phydev); in rtl8169_up()
4845 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_close() local
4846 struct pci_dev *pdev = tp->pci_dev; in rtl8169_close()
4851 rtl8169_down(tp); in rtl8169_close()
4852 rtl8169_rx_clear(tp); in rtl8169_close()
4854 cancel_work(&tp->wk.work); in rtl8169_close()
4856 free_irq(tp->irq, tp); in rtl8169_close()
4858 phy_disconnect(tp->phydev); in rtl8169_close()
4860 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, in rtl8169_close()
4861 tp->RxPhyAddr); in rtl8169_close()
4862 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, in rtl8169_close()
4863 tp->TxPhyAddr); in rtl8169_close()
4864 tp->TxDescArray = NULL; in rtl8169_close()
4865 tp->RxDescArray = NULL; in rtl8169_close()
4875 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_netpoll() local
4877 rtl8169_interrupt(tp->irq, tp); in rtl8169_netpoll()
4883 struct rtl8169_private *tp = netdev_priv(dev); in rtl_open() local
4884 struct pci_dev *pdev = tp->pci_dev; in rtl_open()
4894 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, in rtl_open()
4895 &tp->TxPhyAddr, GFP_KERNEL); in rtl_open()
4896 if (!tp->TxDescArray) in rtl_open()
4899 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, in rtl_open()
4900 &tp->RxPhyAddr, GFP_KERNEL); in rtl_open()
4901 if (!tp->RxDescArray) in rtl_open()
4904 retval = rtl8169_init_ring(tp); in rtl_open()
4908 rtl_request_firmware(tp); in rtl_open()
4911 retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp); in rtl_open()
4915 retval = r8169_phy_connect(tp); in rtl_open()
4919 rtl8169_up(tp); in rtl_open()
4920 rtl8169_init_counter_offsets(tp); in rtl_open()
4928 free_irq(tp->irq, tp); in rtl_open()
4930 rtl_release_firmware(tp); in rtl_open()
4931 rtl8169_rx_clear(tp); in rtl_open()
4933 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, in rtl_open()
4934 tp->RxPhyAddr); in rtl_open()
4935 tp->RxDescArray = NULL; in rtl_open()
4937 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, in rtl_open()
4938 tp->TxPhyAddr); in rtl_open()
4939 tp->TxDescArray = NULL; in rtl_open()
4946 struct rtl8169_private *tp = netdev_priv(dev); in rtl8169_get_stats64() local
4947 struct pci_dev *pdev = tp->pci_dev; in rtl8169_get_stats64()
4948 struct rtl8169_counters *counters = tp->counters; in rtl8169_get_stats64()
4960 rtl8169_update_counters(tp); in rtl8169_get_stats64()
4967 le64_to_cpu(tp->tc_offset.tx_errors); in rtl8169_get_stats64()
4969 le32_to_cpu(tp->tc_offset.tx_multi_collision); in rtl8169_get_stats64()
4971 le16_to_cpu(tp->tc_offset.tx_aborted); in rtl8169_get_stats64()
4973 le16_to_cpu(tp->tc_offset.rx_missed); in rtl8169_get_stats64()
4978 static void rtl8169_net_suspend(struct rtl8169_private *tp) in rtl8169_net_suspend() argument
4980 netif_device_detach(tp->dev); in rtl8169_net_suspend()
4982 if (netif_running(tp->dev)) in rtl8169_net_suspend()
4983 rtl8169_down(tp); in rtl8169_net_suspend()
4988 struct rtl8169_private *tp = dev_get_drvdata(dev); in rtl8169_runtime_resume() local
4990 rtl_rar_set(tp, tp->dev->dev_addr); in rtl8169_runtime_resume()
4991 __rtl8169_set_wol(tp, tp->saved_wolopts); in rtl8169_runtime_resume()
4993 if (tp->TxDescArray) in rtl8169_runtime_resume()
4994 rtl8169_up(tp); in rtl8169_runtime_resume()
4996 netif_device_attach(tp->dev); in rtl8169_runtime_resume()
5003 struct rtl8169_private *tp = dev_get_drvdata(device); in rtl8169_suspend() local
5006 rtl8169_net_suspend(tp); in rtl8169_suspend()
5007 if (!device_may_wakeup(tp_to_dev(tp))) in rtl8169_suspend()
5008 clk_disable_unprepare(tp->clk); in rtl8169_suspend()
5016 struct rtl8169_private *tp = dev_get_drvdata(device); in rtl8169_resume() local
5018 if (!device_may_wakeup(tp_to_dev(tp))) in rtl8169_resume()
5019 clk_prepare_enable(tp->clk); in rtl8169_resume()
5022 if (tp->mac_version == RTL_GIGA_MAC_VER_37) in rtl8169_resume()
5023 rtl_init_rxcfg(tp); in rtl8169_resume()
5030 struct rtl8169_private *tp = dev_get_drvdata(device); in rtl8169_runtime_suspend() local
5032 if (!tp->TxDescArray) { in rtl8169_runtime_suspend()
5033 netif_device_detach(tp->dev); in rtl8169_runtime_suspend()
5038 __rtl8169_set_wol(tp, WAKE_PHY); in rtl8169_runtime_suspend()
5039 rtl8169_net_suspend(tp); in rtl8169_runtime_suspend()
5047 struct rtl8169_private *tp = dev_get_drvdata(device); in rtl8169_runtime_idle() local
5049 if (tp->dash_enabled) in rtl8169_runtime_idle()
5052 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) in rtl8169_runtime_idle()
5066 struct rtl8169_private *tp = pci_get_drvdata(pdev); in rtl_shutdown() local
5069 rtl8169_net_suspend(tp); in rtl_shutdown()
5073 rtl_rar_set(tp, tp->dev->perm_addr); in rtl_shutdown()
5075 if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) { in rtl_shutdown()
5076 pci_wake_from_d3(pdev, tp->saved_wolopts); in rtl_shutdown()
5083 struct rtl8169_private *tp = pci_get_drvdata(pdev); in rtl_remove_one() local
5088 cancel_work_sync(&tp->wk.work); in rtl_remove_one()
5091 r8169_remove_leds(tp->leds); in rtl_remove_one()
5093 unregister_netdev(tp->dev); in rtl_remove_one()
5095 if (tp->dash_type != RTL_DASH_NONE) in rtl_remove_one()
5096 rtl8168_driver_stop(tp); in rtl_remove_one()
5098 rtl_release_firmware(tp); in rtl_remove_one()
5101 rtl_rar_set(tp, tp->dev->perm_addr); in rtl_remove_one()
5124 static void rtl_set_irq_mask(struct rtl8169_private *tp) in rtl_set_irq_mask() argument
5126 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; in rtl_set_irq_mask()
5128 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) in rtl_set_irq_mask()
5129 tp->irq_mask |= SYSErr | RxFIFOOver; in rtl_set_irq_mask()
5130 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) in rtl_set_irq_mask()
5132 tp->irq_mask |= RxFIFOOver; in rtl_set_irq_mask()
5135 static int rtl_alloc_irq(struct rtl8169_private *tp) in rtl_alloc_irq() argument
5139 switch (tp->mac_version) { in rtl_alloc_irq()
5141 rtl_unlock_config_regs(tp); in rtl_alloc_irq()
5142 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); in rtl_alloc_irq()
5143 rtl_lock_config_regs(tp); in rtl_alloc_irq()
5153 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); in rtl_alloc_irq()
5156 static void rtl_read_mac_address(struct rtl8169_private *tp, in rtl_read_mac_address() argument
5160 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { in rtl_read_mac_address()
5163 value = rtl_eri_read(tp, 0xe0); in rtl_read_mac_address()
5165 value = rtl_eri_read(tp, 0xe4); in rtl_read_mac_address()
5167 } else if (rtl_is_8125(tp)) { in rtl_read_mac_address()
5168 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); in rtl_read_mac_address()
5174 return RTL_R8(tp, MCU) & LINK_LIST_RDY; in DECLARE_RTL_COND()
5177 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) in r8168g_wait_ll_share_fifo_ready() argument
5179 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); in r8168g_wait_ll_share_fifo_ready()
5184 struct rtl8169_private *tp = mii_bus->priv; in r8169_mdio_read_reg() local
5189 return rtl_readphy(tp, phyreg); in r8169_mdio_read_reg()
5195 struct rtl8169_private *tp = mii_bus->priv; in r8169_mdio_write_reg() local
5200 rtl_writephy(tp, phyreg, val); in r8169_mdio_write_reg()
5205 static int r8169_mdio_register(struct rtl8169_private *tp) in r8169_mdio_register() argument
5207 struct pci_dev *pdev = tp->pci_dev; in r8169_mdio_register()
5216 if (tp->mac_version == RTL_GIGA_MAC_VER_25 || in r8169_mdio_register()
5217 tp->mac_version == RTL_GIGA_MAC_VER_26) in r8169_mdio_register()
5218 r8169_mdio_write(tp, 0x1f, 0); in r8169_mdio_register()
5225 new_bus->priv = tp; in r8169_mdio_register()
5238 tp->phydev = mdiobus_get_phy(new_bus, 0); in r8169_mdio_register()
5239 if (!tp->phydev) { in r8169_mdio_register()
5241 } else if (!tp->phydev->drv) { in r8169_mdio_register()
5246 tp->phydev->phy_id); in r8169_mdio_register()
5250 tp->phydev->mac_managed_pm = true; in r8169_mdio_register()
5251 if (rtl_supports_eee(tp)) in r8169_mdio_register()
5252 phy_support_eee(tp->phydev); in r8169_mdio_register()
5253 phy_support_asym_pause(tp->phydev); in r8169_mdio_register()
5256 phy_suspend(tp->phydev); in r8169_mdio_register()
5261 static void rtl_hw_init_8168g(struct rtl8169_private *tp) in rtl_hw_init_8168g() argument
5263 rtl_enable_rxdvgate(tp); in rtl_hw_init_8168g()
5265 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); in rtl_hw_init_8168g()
5267 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_init_8168g()
5269 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); in rtl_hw_init_8168g()
5270 r8168g_wait_ll_share_fifo_ready(tp); in rtl_hw_init_8168g()
5272 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); in rtl_hw_init_8168g()
5273 r8168g_wait_ll_share_fifo_ready(tp); in rtl_hw_init_8168g()
5276 static void rtl_hw_init_8125(struct rtl8169_private *tp) in rtl_hw_init_8125() argument
5278 rtl_enable_rxdvgate(tp); in rtl_hw_init_8125()
5280 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); in rtl_hw_init_8125()
5282 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_init_8125()
5284 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); in rtl_hw_init_8125()
5285 r8168g_wait_ll_share_fifo_ready(tp); in rtl_hw_init_8125()
5287 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); in rtl_hw_init_8125()
5288 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); in rtl_hw_init_8125()
5289 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); in rtl_hw_init_8125()
5290 r8168g_wait_ll_share_fifo_ready(tp); in rtl_hw_init_8125()
5293 static void rtl_hw_initialize(struct rtl8169_private *tp) in rtl_hw_initialize() argument
5295 switch (tp->mac_version) { in rtl_hw_initialize()
5297 rtl8168ep_stop_cmac(tp); in rtl_hw_initialize()
5300 rtl_hw_init_8168g(tp); in rtl_hw_initialize()
5303 rtl_hw_init_8125(tp); in rtl_hw_initialize()
5310 static int rtl_jumbo_max(struct rtl8169_private *tp) in rtl_jumbo_max() argument
5313 if (!tp->supports_gmii) in rtl_jumbo_max()
5316 switch (tp->mac_version) { in rtl_jumbo_max()
5332 static void rtl_init_mac_address(struct rtl8169_private *tp) in rtl_init_mac_address() argument
5335 struct net_device *dev = tp->dev; in rtl_init_mac_address()
5338 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); in rtl_init_mac_address()
5342 rtl_read_mac_address(tp, mac_addr); in rtl_init_mac_address()
5346 rtl_read_mac_from_reg(tp, mac_addr, MAC0); in rtl_init_mac_address()
5352 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); in rtl_init_mac_address()
5355 rtl_rar_set(tp, mac_addr); in rtl_init_mac_address()
5359 static bool rtl_aspm_is_safe(struct rtl8169_private *tp) in rtl_aspm_is_safe() argument
5361 if (tp->mac_version >= RTL_GIGA_MAC_VER_61 && in rtl_aspm_is_safe()
5362 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) in rtl_aspm_is_safe()
5370 struct rtl8169_private *tp; in rtl_init_one() local
5377 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); in rtl_init_one()
5383 tp = netdev_priv(dev); in rtl_init_one()
5384 tp->dev = dev; in rtl_init_one()
5385 tp->pci_dev = pdev; in rtl_init_one()
5386 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; in rtl_init_one()
5387 tp->ocp_base = OCP_STD_PHY_BASE; in rtl_init_one()
5389 raw_spin_lock_init(&tp->cfg9346_usage_lock); in rtl_init_one()
5390 raw_spin_lock_init(&tp->config25_lock); in rtl_init_one()
5391 raw_spin_lock_init(&tp->mac_ocp_lock); in rtl_init_one()
5392 mutex_init(&tp->led_lock); in rtl_init_one()
5395 tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk"); in rtl_init_one()
5396 if (IS_ERR(tp->clk)) in rtl_init_one()
5397 return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n"); in rtl_init_one()
5416 tp->mmio_addr = pcim_iomap_table(pdev)[region]; in rtl_init_one()
5418 txconfig = RTL_R32(tp, TxConfig); in rtl_init_one()
5425 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); in rtl_init_one()
5430 tp->mac_version = chipset; in rtl_init_one()
5435 if (rtl_aspm_is_safe(tp)) in rtl_init_one()
5439 tp->aspm_manageable = !rc; in rtl_init_one()
5441 tp->dash_type = rtl_get_dash_type(tp); in rtl_init_one()
5442 tp->dash_enabled = rtl_dash_is_enabled(tp); in rtl_init_one()
5444 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; in rtl_init_one()
5446 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && in rtl_init_one()
5450 rtl_init_rxcfg(tp); in rtl_init_one()
5452 rtl8169_irq_mask_and_ack(tp); in rtl_init_one()
5454 rtl_hw_initialize(tp); in rtl_init_one()
5456 rtl_hw_reset(tp); in rtl_init_one()
5458 rc = rtl_alloc_irq(tp); in rtl_init_one()
5462 tp->irq = pci_irq_vector(pdev, 0); in rtl_init_one()
5464 INIT_WORK(&tp->wk.work, rtl_task); in rtl_init_one()
5466 rtl_init_mac_address(tp); in rtl_init_one()
5470 netif_napi_add(dev, &tp->napi, rtl8169_poll); in rtl_init_one()
5481 if (tp->mac_version == RTL_GIGA_MAC_VER_05) in rtl_init_one()
5485 if (rtl_chip_supports_csum_v2(tp)) in rtl_init_one()
5495 if (rtl_chip_supports_csum_v2(tp)) { in rtl_init_one()
5515 if (!tp->dash_enabled) { in rtl_init_one()
5516 rtl_set_d3_pll_down(tp, true); in rtl_init_one()
5518 rtl_set_d3_pll_down(tp, false); in rtl_init_one()
5522 jumbo_max = rtl_jumbo_max(tp); in rtl_init_one()
5526 rtl_set_irq_mask(tp); in rtl_init_one()
5528 tp->fw_name = rtl_chip_infos[chipset].fw_name; in rtl_init_one()
5530 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), in rtl_init_one()
5531 &tp->counters_phys_addr, in rtl_init_one()
5533 if (!tp->counters) in rtl_init_one()
5536 pci_set_drvdata(pdev, tp); in rtl_init_one()
5538 rc = r8169_mdio_register(tp); in rtl_init_one()
5547 if (rtl_is_8125(tp)) in rtl_init_one()
5548 tp->leds = rtl8125_init_leds(dev); in rtl_init_one()
5549 else if (tp->mac_version > RTL_GIGA_MAC_VER_06) in rtl_init_one()
5550 tp->leds = rtl8168_init_leds(dev); in rtl_init_one()
5554 rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq); in rtl_init_one()
5558 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? in rtl_init_one()
5561 if (tp->dash_type != RTL_DASH_NONE) { in rtl_init_one()
5563 tp->dash_enabled ? "enabled" : "disabled"); in rtl_init_one()
5564 rtl8168_driver_start(tp); in rtl_init_one()