16 #define PAR_DATA	0
20 #define Ctrl_LNibRead	0x08	/* LP_PSELECP */
21 #define Ctrl_HNibRead	0
22 #define Ctrl_LNibWrite	0x08	/* LP_PSELECP */
23 #define Ctrl_HNibWrite	0
24 #define Ctrl_SelData	0x04	/* LP_PINITP */
25 #define Ctrl_IRQEN	0x10	/* LP_PINTEN */
27 #define EOW	0xE0
28 #define EOC	0xE0
29 #define WrAddr	0x40	/* Set address of EPLC read, write register. */
30 #define RdAddr	0xC0
31 #define HNib	0x10
37 	PAR0 = 0, PAR1 = 1, PAR2 = 2, PAR3 = 3, PAR4 = 4, PAR5 = 5,
45 	CMR2_h = 0x1d,
53 #define ISR_TxOK	0x01
54 #define ISR_RxOK	0x04
55 #define ISR_TxErr	0x02
56 #define ISRh_RxErr	0x11	/* ISR, high nibble */
58 #define CMR1h_MUX	0x08	/* Select printer multiplexor on 8012. */
59 #define CMR1h_RESET	0x04	/* Reset. */
60 #define CMR1h_RxENABLE	0x02	/* Rx unit enable.  */
61 #define CMR1h_TxENABLE	0x01	/* Tx unit enable.  */
62 #define CMR1h_TxRxOFF	0x00
63 #define CMR1_ReXmit	0x08	/* Trigger a retransmit. */
64 #define CMR1_Xmit	0x04	/* Trigger a transmit. */
65 #define	CMR1_IRQ	0x02	/* Interrupt active. */
66 #define	CMR1_BufEnb	0x01	/* Enable the buffer(?). */
67 #define	CMR1_NextPkt	0x01	/* Enable the buffer(?). */
74 #define CMR2h_OFF	0	/* No accept mode. */
107 /* Get a byte using read mode 0, reading data from the control lines. */
114 	low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;  in read_byte_mode0()
118 	return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);  in read_byte_mode0()
128 	low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;  in read_byte_mode2()
131 	return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);  in read_byte_mode2()
140 	low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;  in read_byte_mode4()
142 	return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);  in read_byte_mode4()
152 	low_nib = (inbyte(ioaddr + PAR_STATUS) >> 3) & 0x0f;  in read_byte_mode6()
155 	return low_nib | ((inbyte(ioaddr + PAR_STATUS) << 1) & 0xf0);  in read_byte_mode6()
168 	outval &= 0xf0;  in write_reg()
171 	outval &= 0x1f;  in write_reg()
184 	outval &= WrAddr | HNib | 0x0f;  in write_reg_high()
190 	outval &= HNib | 0x0f;		/* HNib | value */  in write_reg_high()
208 	outb((outval & 0xf0) | (value & 0x0f), port + PAR_DATA);  in write_reg_byte()
209 	outb(value & 0x0f, port + PAR_DATA);  in write_reg_byte()
212 	outb(0x10 | value, port + PAR_DATA);  in write_reg_byte()
213 	outb(0x10 | value, port + PAR_DATA);  in write_reg_byte()
219  * The first, faster method uses only the dataport (data modes 0, 2 & 4).
226 	outb(value & 0x0f, ioaddr + PAR_DATA);  in write_byte_mode0()
227 	outb((value>>4) | 0x10, ioaddr + PAR_DATA);  in write_byte_mode0()
232 	outb(value & 0x0f, ioaddr + PAR_DATA);  in write_byte_mode1()
234 	outb((value>>4) | 0x10, ioaddr + PAR_DATA);  in write_byte_mode1()
241 	outb(value & 0x0f, ioaddr + PAR_DATA);  in write_word_mode0()
243 	outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);  in write_word_mode0()
245 	outb(value & 0x0f, ioaddr + PAR_DATA);  in write_word_mode0()
247 	outb((value & 0x0f) | 0x10, ioaddr + PAR_DATA);  in write_word_mode0()
251 #define EE_SHIFT_CLK	0x04	/* EEPROM shift clock. */
252 #define EE_CS		0x02	/* EEPROM chip select. */
253 #define EE_CLK_HIGH	0x12
254 #define EE_CLK_LOW	0x16
255 #define EE_DATA_WRITE	0x01	/* EEPROM chip data in. */
256 #define EE_DATA_READ	0x08	/* EEPROM chip data out. */