Lines Matching +full:0 +full:x1b00
17 #define EMAC_DMA_MAS_CTRL 0x1400
18 #define EMAC_IRQ_MOD_TIM_INIT 0x1408
19 #define EMAC_BLK_IDLE_STS 0x140c
20 #define EMAC_PHY_LINK_DELAY 0x141c
21 #define EMAC_SYS_ALIV_CTRL 0x1434
22 #define EMAC_MAC_CTRL 0x1480
23 #define EMAC_MAC_IPGIFG_CTRL 0x1484
24 #define EMAC_MAC_STA_ADDR0 0x1488
25 #define EMAC_MAC_STA_ADDR1 0x148c
26 #define EMAC_HASH_TAB_REG0 0x1490
27 #define EMAC_HASH_TAB_REG1 0x1494
28 #define EMAC_MAC_HALF_DPLX_CTRL 0x1498
29 #define EMAC_MAX_FRAM_LEN_CTRL 0x149c
30 #define EMAC_WOL_CTRL0 0x14a0
31 #define EMAC_RSS_KEY0 0x14b0
32 #define EMAC_H1TPD_BASE_ADDR_LO 0x14e0
33 #define EMAC_H2TPD_BASE_ADDR_LO 0x14e4
34 #define EMAC_H3TPD_BASE_ADDR_LO 0x14e8
35 #define EMAC_INTER_SRAM_PART9 0x1534
36 #define EMAC_DESC_CTRL_0 0x1540
37 #define EMAC_DESC_CTRL_1 0x1544
38 #define EMAC_DESC_CTRL_2 0x1550
39 #define EMAC_DESC_CTRL_10 0x1554
40 #define EMAC_DESC_CTRL_12 0x1558
41 #define EMAC_DESC_CTRL_13 0x155c
42 #define EMAC_DESC_CTRL_3 0x1560
43 #define EMAC_DESC_CTRL_4 0x1564
44 #define EMAC_DESC_CTRL_5 0x1568
45 #define EMAC_DESC_CTRL_14 0x156c
46 #define EMAC_DESC_CTRL_15 0x1570
47 #define EMAC_DESC_CTRL_16 0x1574
48 #define EMAC_DESC_CTRL_6 0x1578
49 #define EMAC_DESC_CTRL_8 0x1580
50 #define EMAC_DESC_CTRL_9 0x1584
51 #define EMAC_DESC_CTRL_11 0x1588
52 #define EMAC_TXQ_CTRL_0 0x1590
53 #define EMAC_TXQ_CTRL_1 0x1594
54 #define EMAC_TXQ_CTRL_2 0x1598
55 #define EMAC_RXQ_CTRL_0 0x15a0
56 #define EMAC_RXQ_CTRL_1 0x15a4
57 #define EMAC_RXQ_CTRL_2 0x15a8
58 #define EMAC_RXQ_CTRL_3 0x15ac
59 #define EMAC_BASE_CPU_NUMBER 0x15b8
60 #define EMAC_DMA_CTRL 0x15c0
61 #define EMAC_MAILBOX_0 0x15e0
62 #define EMAC_MAILBOX_5 0x15e4
63 #define EMAC_MAILBOX_6 0x15e8
64 #define EMAC_MAILBOX_13 0x15ec
65 #define EMAC_MAILBOX_2 0x15f4
66 #define EMAC_MAILBOX_3 0x15f8
67 #define EMAC_INT_STATUS 0x1600
68 #define EMAC_INT_MASK 0x1604
69 #define EMAC_MAILBOX_11 0x160c
70 #define EMAC_AXI_MAST_CTRL 0x1610
71 #define EMAC_MAILBOX_12 0x1614
72 #define EMAC_MAILBOX_9 0x1618
73 #define EMAC_MAILBOX_10 0x161c
74 #define EMAC_ATHR_HEADER_CTRL 0x1620
75 #define EMAC_RXMAC_STATC_REG0 0x1700
76 #define EMAC_RXMAC_STATC_REG22 0x1758
77 #define EMAC_TXMAC_STATC_REG0 0x1760
78 #define EMAC_TXMAC_STATC_REG24 0x17c0
79 #define EMAC_CLK_GATE_CTRL 0x1814
80 #define EMAC_CORE_HW_VERSION 0x1974
81 #define EMAC_MISC_CTRL 0x1990
82 #define EMAC_MAILBOX_7 0x19e0
83 #define EMAC_MAILBOX_8 0x19e4
84 #define EMAC_IDT_TABLE0 0x1b00
85 #define EMAC_RXMAC_STATC_REG23 0x1bc8
86 #define EMAC_RXMAC_STATC_REG24 0x1bcc
87 #define EMAC_TXMAC_STATC_REG25 0x1bd0
88 #define EMAC_MAILBOX_15 0x1bd4
89 #define EMAC_MAILBOX_16 0x1bd8
90 #define EMAC_INT1_MASK 0x1bf0
91 #define EMAC_INT1_STATUS 0x1bf4
92 #define EMAC_INT2_MASK 0x1bf8
93 #define EMAC_INT2_STATUS 0x1bfc
94 #define EMAC_INT3_MASK 0x1c00
95 #define EMAC_INT3_STATUS 0x1c04
98 #define DEV_ID_NUM_BMSK 0x7f000000
100 #define DEV_REV_NUM_BMSK 0xff0000
102 #define INT_RD_CLR_EN 0x4000
103 #define IRQ_MODERATOR2_EN 0x800
104 #define IRQ_MODERATOR_EN 0x400
105 #define LPW_CLK_SEL 0x80
106 #define LPW_STATE 0x20
107 #define LPW_MODE 0x10
108 #define SOFT_RST 0x1
111 #define IRQ_MODERATOR2_INIT_BMSK 0xffff0000
113 #define IRQ_MODERATOR_INIT_BMSK 0xffff
114 #define IRQ_MODERATOR_INIT_SHFT 0
143 #define RFD2_PROC_IDX_BMSK 0xfff0000
145 #define RFD2_PROD_IDX_BMSK 0xfff
146 #define RFD2_PROD_IDX_SHFT 0
149 #define MAJOR_BMSK 0xf0000000
151 #define MINOR_BMSK 0xfff0000
153 #define STEP_BMSK 0xffff
154 #define STEP_SHFT 0
167 #define HDRIVE_BMSK 0x3000
172 #define PHY_RESET BIT(0)
174 #define EMAC_DEV_ID 0x0040
177 #define SGMII_LN_RSM_START 0x029C
180 #define SGMII_PHY_CMN_CTRL 0x0408
181 #define SGMII_PHY_CMN_RESET_CTRL 0x0410
184 #define SGMII_PHY_LN_OFFSET 0x0400
185 #define SGMII_PHY_LN_LANE_STATUS 0x00DC
186 #define SGMII_PHY_LN_BIST_GEN0 0x008C
187 #define SGMII_PHY_LN_BIST_GEN1 0x0090
188 #define SGMII_PHY_LN_BIST_GEN2 0x0094
189 #define SGMII_PHY_LN_BIST_GEN3 0x0098
190 #define SGMII_PHY_LN_CDR_CTRL1 0x005C
203 #define EMAC_LINK_SPEED_UNKNOWN 0x0
204 #define EMAC_LINK_SPEED_10_HALF BIT(0)
272 #define EMAC_RSS_HSTYP_IPV4_EN 0x00000001
273 #define EMAC_RSS_HSTYP_TCP4_EN 0x00000002
274 #define EMAC_RSS_HSTYP_IPV6_EN 0x00000004
275 #define EMAC_RSS_HSTYP_TCP6_EN 0x00000008
283 (_tag = ((((_vlan) >> 8) & 0xFF) | (((_vlan) & 0xFF) << 8)))
286 (_vlan = ((((_tag) >> 8) & 0xFF) | (((_tag) & 0xFF) << 8)))