Lines Matching full:x3
147 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
188 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
190 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
359 #define CORE_TX_BD_TX_DST_MASK 0x3
469 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
471 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
473 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
475 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
478 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
480 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
482 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
484 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
487 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
489 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
491 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
493 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
496 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
498 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
500 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
502 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
505 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
507 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
509 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
511 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
514 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
516 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
518 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
639 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
710 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
713 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
715 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
717 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
719 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
722 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
724 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
726 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
728 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
731 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
733 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
806 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
808 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
810 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
813 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
815 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
817 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
819 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
1494 #define DMAE_CMD_DST_MASK 0x3
1514 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1516 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
1518 #define DMAE_CMD_PORT_ID_MASK 0x3
1528 #define DMAE_CMD_RESERVED2_MASK 0x3
1610 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1612 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1614 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1647 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1649 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1651 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1797 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1866 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3
3305 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
3307 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
3309 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3311 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3314 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
3316 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
3318 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
3320 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
3323 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
3325 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
3327 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
3329 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
3332 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
3334 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
3336 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
3338 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
3341 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
3343 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
3345 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
3347 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
3350 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
3352 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
3354 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
3475 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
3543 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
3545 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
3547 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3595 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
3598 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
3600 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3602 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3604 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
3607 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
3609 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
3611 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
3613 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
3616 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
3618 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
3691 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
3693 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
3695 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3698 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3700 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
3702 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
3704 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
4427 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
4429 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
4431 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
4433 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
4436 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
4438 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
4440 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
4442 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
4445 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
4447 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
4449 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
4451 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
4454 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
4456 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
4458 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
4460 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
4463 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
4465 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
4467 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
4469 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
4472 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
4474 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
4476 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
4597 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
4626 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4628 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4630 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4693 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
4695 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
4697 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
4699 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
4702 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
4704 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
4706 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
4708 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
4711 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
4713 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
4715 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
4717 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
4720 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
4722 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
4724 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
4726 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
4729 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
4731 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
4733 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
4735 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
4738 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
4740 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
4742 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
4863 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
4924 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
4963 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
5080 #define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5082 #define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5084 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
5136 #define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5138 #define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5140 #define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
5197 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
5200 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
5202 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
5204 #define USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK 0x3
5206 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
5301 #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK 0x3
5303 #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_MASK 0x3
5305 #define YSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5375 #define XSTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
5377 #define XSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5379 #define XSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5381 #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5384 #define XSTORM_TOE_CONN_AG_CTX_CF4_MASK 0x3
5386 #define XSTORM_TOE_CONN_AG_CTX_CF5_MASK 0x3
5388 #define XSTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
5390 #define XSTORM_TOE_CONN_AG_CTX_CF7_MASK 0x3
5393 #define XSTORM_TOE_CONN_AG_CTX_CF8_MASK 0x3
5395 #define XSTORM_TOE_CONN_AG_CTX_CF9_MASK 0x3
5397 #define XSTORM_TOE_CONN_AG_CTX_CF10_MASK 0x3
5399 #define XSTORM_TOE_CONN_AG_CTX_CF11_MASK 0x3
5402 #define XSTORM_TOE_CONN_AG_CTX_CF12_MASK 0x3
5404 #define XSTORM_TOE_CONN_AG_CTX_CF13_MASK 0x3
5406 #define XSTORM_TOE_CONN_AG_CTX_CF14_MASK 0x3
5408 #define XSTORM_TOE_CONN_AG_CTX_CF15_MASK 0x3
5411 #define XSTORM_TOE_CONN_AG_CTX_CF16_MASK 0x3
5413 #define XSTORM_TOE_CONN_AG_CTX_CF17_MASK 0x3
5415 #define XSTORM_TOE_CONN_AG_CTX_CF18_MASK 0x3
5417 #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
5420 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5422 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
5424 #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
5545 #define XSTORM_TOE_CONN_AG_CTX_CF23_MASK 0x3
5610 #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_MASK 0x3
5613 #define TSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5615 #define TSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5617 #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5619 #define TSTORM_TOE_CONN_AG_CTX_CF4_MASK 0x3
5622 #define TSTORM_TOE_CONN_AG_CTX_CF5_MASK 0x3
5624 #define TSTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
5626 #define TSTORM_TOE_CONN_AG_CTX_CF7_MASK 0x3
5628 #define TSTORM_TOE_CONN_AG_CTX_CF8_MASK 0x3
5631 #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5633 #define TSTORM_TOE_CONN_AG_CTX_CF10_MASK 0x3
5699 #define USTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
5701 #define USTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5703 #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_MASK 0x3
5706 #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5708 #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK 0x3
5710 #define USTORM_TOE_CONN_AG_CTX_DQ_CF_MASK 0x3
5712 #define USTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
6055 #define MSTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
6057 #define MSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
6059 #define MSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
6087 #define TOE_DB_DATA_DEST_MASK 0x3
6089 #define TOE_DB_DATA_AGG_CMD_MASK 0x3
6095 #define TOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
6266 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
6393 #define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6395 #define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6397 #define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6400 #define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6402 #define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
6404 #define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
6406 #define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
6409 #define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
6460 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6462 #define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6464 #define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6467 #define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
6469 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
6471 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
6473 #define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
6559 #define XSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
6561 #define XSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
6563 #define XSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
6565 #define XSTORM_ROCE_CONN_AG_CTX_CF3_MASK 0x3
6568 #define XSTORM_ROCE_CONN_AG_CTX_CF4_MASK 0x3
6570 #define XSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
6572 #define XSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
6574 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6577 #define XSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
6579 #define XSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
6581 #define XSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
6583 #define XSTORM_ROCE_CONN_AG_CTX_CF11_MASK 0x3
6586 #define XSTORM_ROCE_CONN_AG_CTX_CF12_MASK 0x3
6588 #define XSTORM_ROCE_CONN_AG_CTX_CF13_MASK 0x3
6590 #define XSTORM_ROCE_CONN_AG_CTX_CF14_MASK 0x3
6592 #define XSTORM_ROCE_CONN_AG_CTX_CF15_MASK 0x3
6595 #define XSTORM_ROCE_CONN_AG_CTX_CF16_MASK 0x3
6597 #define XSTORM_ROCE_CONN_AG_CTX_CF17_MASK 0x3
6599 #define XSTORM_ROCE_CONN_AG_CTX_CF18_MASK 0x3
6601 #define XSTORM_ROCE_CONN_AG_CTX_CF19_MASK 0x3
6604 #define XSTORM_ROCE_CONN_AG_CTX_CF20_MASK 0x3
6606 #define XSTORM_ROCE_CONN_AG_CTX_CF21_MASK 0x3
6608 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
6721 #define XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
6727 #define XSTORM_ROCE_CONN_AG_CTX_CF23_MASK 0x3
6766 #define TSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
6769 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
6771 #define TSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
6773 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
6775 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6778 #define TSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
6780 #define TSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
6782 #define TSTORM_ROCE_CONN_AG_CTX_CF7_MASK 0x3
6784 #define TSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
6787 #define TSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
6789 #define TSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
6915 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
6974 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
7488 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
7490 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
7492 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
7494 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
7497 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
7499 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
7501 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
7503 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
7506 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
7508 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
7510 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
7512 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
7515 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
7517 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
7519 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
7521 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
7524 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
7526 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
7528 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
7530 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
7533 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
7535 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
7537 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
7650 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
7656 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
7685 #define MSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
7687 #define MSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
7689 #define MSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
7722 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7724 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7726 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7759 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7761 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7763 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7804 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
7807 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7809 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
7811 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7813 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7816 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK 0x3
7818 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
7820 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
7822 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
7825 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
7827 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
7908 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7911 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7913 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
7915 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7917 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7920 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7922 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
7924 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
7926 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
7929 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
7931 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8004 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8006 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8008 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8011 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8013 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
8015 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
8017 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
8073 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8075 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8077 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8080 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8082 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
8084 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
8086 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8172 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8174 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8176 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8178 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8181 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8183 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8185 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
8187 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8190 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK 0x3
8192 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK 0x3
8194 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
8196 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
8199 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
8201 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
8203 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
8205 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
8208 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
8210 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
8212 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
8214 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
8217 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
8219 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
8221 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8334 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
8340 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
8401 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8403 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8405 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8407 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8410 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
8412 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8414 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
8416 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8419 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8421 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8423 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8425 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
8428 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
8430 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
8432 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
8434 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
8437 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
8439 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
8441 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
8443 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
8446 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
8448 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
8450 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8571 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
8602 #define YSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
8604 #define YSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
8606 #define YSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
8646 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8648 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8650 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8690 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8692 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8694 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8787 #define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
8789 #define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
8791 #define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
8793 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8796 #define XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
8798 #define XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
8800 #define XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
8802 #define XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
8805 #define XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
8807 #define XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
8809 #define XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
8811 #define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
8814 #define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
8816 #define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
8818 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8820 #define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
8823 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
8825 #define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
8827 #define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
8829 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
8832 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
8834 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
8836 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8957 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK 0x3
9022 #define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9025 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
9027 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
9029 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
9031 #define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
9034 #define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
9036 #define TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9038 #define TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
9040 #define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
9043 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
9045 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
9434 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
9436 #define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9438 #define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9471 #define USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9473 #define USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9475 #define USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9478 #define USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
9480 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
9482 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
9484 #define USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9540 #define YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9542 #define YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9544 #define YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9703 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
9790 #define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
9792 #define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
9794 #define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9796 #define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
9799 #define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9801 #define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9803 #define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9805 #define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
9808 #define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
9810 #define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
9812 #define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
9814 #define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
9817 #define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
9819 #define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
9821 #define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
9823 #define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
9826 #define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
9828 #define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
9830 #define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
9832 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
9835 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9837 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
9839 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9960 #define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
10015 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
10018 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
10020 #define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10022 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
10024 #define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10027 #define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10029 #define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10031 #define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
10033 #define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
10036 #define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
10038 #define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
10094 #define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10096 #define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10098 #define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10101 #define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
10103 #define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10105 #define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10107 #define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10173 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
10191 #define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10193 #define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10195 #define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10332 #define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10334 #define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10336 #define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10423 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10425 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10427 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10429 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10432 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10434 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10436 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10438 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10441 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10443 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
10445 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
10447 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
10450 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
10452 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
10454 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
10456 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
10459 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
10461 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
10463 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
10465 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
10468 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
10470 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
10472 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
10593 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
10658 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10661 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
10663 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
10665 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10667 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10670 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10672 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10674 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10676 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10679 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
10681 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK 0x3
10747 #define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10749 #define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10751 #define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10754 #define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
10756 #define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10758 #define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10760 #define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10821 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10823 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10825 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10896 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10898 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10900 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3