45 #define ILT_CFG_REG(cli, reg)	PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET  macro
1123 	clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);  in qed_cxt_mngr_alloc()
1124 	clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);  in qed_cxt_mngr_alloc()
1125 	clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);  in qed_cxt_mngr_alloc()
1127 	clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);  in qed_cxt_mngr_alloc()
1128 	clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);  in qed_cxt_mngr_alloc()
1129 	clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);  in qed_cxt_mngr_alloc()
1131 	clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);  in qed_cxt_mngr_alloc()
1132 	clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);  in qed_cxt_mngr_alloc()
1133 	clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);  in qed_cxt_mngr_alloc()
1135 	clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);  in qed_cxt_mngr_alloc()
1136 	clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);  in qed_cxt_mngr_alloc()
1137 	clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);  in qed_cxt_mngr_alloc()
1139 	clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);  in qed_cxt_mngr_alloc()
1140 	clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);  in qed_cxt_mngr_alloc()
1141 	clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);  in qed_cxt_mngr_alloc()
1143 	clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);  in qed_cxt_mngr_alloc()
1144 	clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);  in qed_cxt_mngr_alloc()
1145 	clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);  in qed_cxt_mngr_alloc()