3307 	u32 phyreg, txreg;  in nv_force_linkspeed()  local
3317 		phyreg = readl(base + NvRegSlotTime);  in nv_force_linkspeed()
3318 		phyreg &= ~(0x3FF00);  in nv_force_linkspeed()
3320 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_force_linkspeed()
3322 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_force_linkspeed()
3324 			phyreg |= NVREG_SLOTTIME_1000_FULL;  in nv_force_linkspeed()
3325 		writel(phyreg, base + NvRegSlotTime);  in nv_force_linkspeed()
3328 	phyreg = readl(base + NvRegPhyInterface);  in nv_force_linkspeed()
3329 	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);  in nv_force_linkspeed()
3331 		phyreg |= PHY_HALF;  in nv_force_linkspeed()
3333 		phyreg |= PHY_100;  in nv_force_linkspeed()
3336 		phyreg |= PHY_1000;  in nv_force_linkspeed()
3337 	writel(phyreg, base + NvRegPhyInterface);  in nv_force_linkspeed()
3339 	if (phyreg & PHY_RGMII) {  in nv_force_linkspeed()
3391 	u32 control_1000, status_1000, phyreg, pause_flags, txreg;  in nv_update_linkspeed()  local
3500 		phyreg = readl(base + NvRegSlotTime);  in nv_update_linkspeed()
3501 		phyreg &= ~(0x3FF00);  in nv_update_linkspeed()
3504 			phyreg |= NVREG_SLOTTIME_10_100_FULL;  in nv_update_linkspeed()
3506 			phyreg |= NVREG_SLOTTIME_1000_FULL;  in nv_update_linkspeed()
3507 		writel(phyreg, base + NvRegSlotTime);  in nv_update_linkspeed()
3510 	phyreg = readl(base + NvRegPhyInterface);  in nv_update_linkspeed()
3511 	phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);  in nv_update_linkspeed()
3513 		phyreg |= PHY_HALF;  in nv_update_linkspeed()
3515 		phyreg |= PHY_100;  in nv_update_linkspeed()
3517 		phyreg |= PHY_1000;  in nv_update_linkspeed()
3518 	writel(phyreg, base + NvRegPhyInterface);  in nv_update_linkspeed()
3521 	if (phyreg & PHY_RGMII) {  in nv_update_linkspeed()