Lines Matching +full:revision +full:- +full:id2
1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * engineered documentation written by Carl-Daniel Hailfinger
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
50 #include <linux/dma-mapping.h>
73 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
483 * - DESC_VER_1: Original
484 * - DESC_VER_2: support for jumbo frames.
485 * - DESC_VER_3: 64-bit format.
568 /* MSI/MSI-X defines */
638 u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */
659 u64 rx_packets; /* should be ifconfig->rx_packets */
665 u64 tx_packets; /* should be ifconfig->tx_packets */
666 u64 rx_bytes; /* should be ifconfig->rx_bytes + 4*rx_packets */
678 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
679 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
727 __this_cpu_inc(np->txrx_stats->member)
729 __this_cpu_add(np->txrx_stats->member, (count))
733 * All hardware access under netdev_priv(dev)->lock, except the performance
735 * - rx is (pseudo-) lockless: it relies on the single-threading provided
737 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
738 * needs netdev_priv(dev)->lock :-(
739 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
742 * - updated by nv_do_stats_poll (timer). This is meant to avoid
745 * - updated by nv_get_ethtool_stats + nv_get_stats64
797 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
818 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
842 /* msi/msi-x fields */
852 /* for different msi-x irq type */
853 char name_rx[IFNAMSIZ + 3]; /* -rx */
854 char name_tx[IFNAMSIZ + 3]; /* -tx */
855 char name_other[IFNAMSIZ + 6]; /* -other */
884 static int poll_interval = -1;
941 return ((struct fe_priv *)netdev_priv(dev))->base; in get_hwbase()
952 return le32_to_cpu(prd->flaglen) in nv_descr_getlength()
958 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2; in nv_descr_getlength_ex()
963 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) in nv_optimized()
976 delaymax -= delay; in reg_delay()
1003 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); in setup_hw_rings()
1005 …writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysA… in setup_hw_rings()
1008 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); in setup_hw_rings()
1009 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh); in setup_hw_rings()
1012 …writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPh… in setup_hw_rings()
1013 …writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingP… in setup_hw_rings()
1023 if (np->rx_ring.orig) in free_rings()
1024 dma_free_coherent(&np->pci_dev->dev, in free_rings()
1026 (np->rx_ring_size + in free_rings()
1027 np->tx_ring_size), in free_rings()
1028 np->rx_ring.orig, np->ring_addr); in free_rings()
1030 if (np->rx_ring.ex) in free_rings()
1031 dma_free_coherent(&np->pci_dev->dev, in free_rings()
1033 (np->rx_ring_size + in free_rings()
1034 np->tx_ring_size), in free_rings()
1035 np->rx_ring.ex, np->ring_addr); in free_rings()
1037 kfree(np->rx_skb); in free_rings()
1038 kfree(np->tx_skb); in free_rings()
1045 if (!(np->msi_flags & NV_MSI_X_ENABLED) || in using_multi_irqs()
1046 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)) in using_multi_irqs()
1058 if (!np->mac_in_use && in nv_txrx_gate()
1059 (np->driver_data & DEV_HAS_POWER_CNTRL)) { in nv_txrx_gate()
1074 if (np->msi_flags & NV_MSI_X_ENABLED) in nv_enable_irq()
1075 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); in nv_enable_irq()
1077 enable_irq(np->pci_dev->irq); in nv_enable_irq()
1079 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); in nv_enable_irq()
1080 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); in nv_enable_irq()
1081 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); in nv_enable_irq()
1090 if (np->msi_flags & NV_MSI_X_ENABLED) in nv_disable_irq()
1091 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); in nv_disable_irq()
1093 disable_irq(np->pci_dev->irq); in nv_disable_irq()
1095 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); in nv_disable_irq()
1096 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); in nv_disable_irq()
1097 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); in nv_disable_irq()
1114 if (np->msi_flags & NV_MSI_X_ENABLED) { in nv_disable_hw_interrupts()
1117 if (np->msi_flags & NV_MSI_ENABLED) in nv_disable_hw_interrupts()
1127 napi_enable(&np->napi); in nv_napi_enable()
1134 napi_disable(&np->napi); in nv_napi_disable()
1137 #define MII_READ (-1)
1165 retval = -1; in mii_rw()
1167 /* it was a write operation - fewer failures are detectable */ in mii_rw()
1170 retval = -1; in mii_rw()
1185 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) in phy_reset()
1186 return -1; in phy_reset()
1194 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_reset()
1197 return -1; in phy_reset()
1219 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) in init_realtek_8211b()
1241 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); in init_realtek_8211c()
1243 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) in init_realtek_8211c()
1245 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1248 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); in init_realtek_8211c()
1251 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) in init_realtek_8211c()
1254 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1265 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) { in init_realtek_8201()
1266 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201()
1269 if (mii_rw(dev, np->phyaddr, in init_realtek_8201()
1282 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1285 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1289 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1292 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1306 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); in init_cicada()
1309 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) in init_cicada()
1311 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in init_cicada()
1313 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) in init_cicada()
1316 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); in init_cicada()
1318 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) in init_cicada()
1328 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1331 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1334 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1336 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1338 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1342 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1344 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1347 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1350 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1354 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1356 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1358 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1360 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1363 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1366 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1368 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1370 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1374 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1376 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1379 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1394 if (np->phy_model == PHY_MODEL_MARVELL_E3016) { in phy_init()
1395 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in phy_init()
1397 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { in phy_init()
1399 pci_name(np->pci_dev)); in phy_init()
1403 if (np->phy_oui == PHY_OUI_REALTEK) { in phy_init()
1404 if (np->phy_model == PHY_MODEL_REALTEK_8211 && in phy_init()
1405 np->phy_rev == PHY_REV_REALTEK_8211B) { in phy_init()
1408 pci_name(np->pci_dev)); in phy_init()
1411 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 && in phy_init()
1412 np->phy_rev == PHY_REV_REALTEK_8211C) { in phy_init()
1415 pci_name(np->pci_dev)); in phy_init()
1418 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) { in phy_init()
1421 pci_name(np->pci_dev)); in phy_init()
1428 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in phy_init()
1432 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { in phy_init()
1434 pci_name(np->pci_dev)); in phy_init()
1442 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in phy_init()
1444 np->gigabit = PHY_GIGABIT; in phy_init()
1445 mii_control_1000 = mii_rw(dev, np->phyaddr, in phy_init()
1453 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { in phy_init()
1455 pci_name(np->pci_dev)); in phy_init()
1459 np->gigabit = 0; in phy_init()
1461 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1464 if (np->phy_oui == PHY_OUI_REALTEK && in phy_init()
1465 np->phy_model == PHY_MODEL_REALTEK_8211 && in phy_init()
1466 np->phy_rev == PHY_REV_REALTEK_8211C) { in phy_init()
1469 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { in phy_init()
1471 pci_name(np->pci_dev)); in phy_init()
1480 pci_name(np->pci_dev)); in phy_init()
1486 if (np->phy_oui == PHY_OUI_CICADA) { in phy_init()
1489 pci_name(np->pci_dev)); in phy_init()
1492 } else if (np->phy_oui == PHY_OUI_VITESSE) { in phy_init()
1495 pci_name(np->pci_dev)); in phy_init()
1498 } else if (np->phy_oui == PHY_OUI_REALTEK) { in phy_init()
1499 if (np->phy_model == PHY_MODEL_REALTEK_8211 && in phy_init()
1500 np->phy_rev == PHY_REV_REALTEK_8211B) { in phy_init()
1504 pci_name(np->pci_dev)); in phy_init()
1507 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) { in phy_init()
1511 pci_name(np->pci_dev)); in phy_init()
1518 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); in phy_init()
1521 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1525 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) in phy_init()
1538 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { in nv_start_rx()
1543 writel(np->linkspeed, base + NvRegLinkSpeed); in nv_start_rx()
1546 if (np->mac_in_use) in nv_start_rx()
1558 if (!np->mac_in_use) in nv_stop_rx()
1569 if (!np->mac_in_use) in nv_stop_rx()
1580 if (np->mac_in_use) in nv_start_tx()
1592 if (!np->mac_in_use) in nv_stop_tx()
1603 if (!np->mac_in_use) in nv_stop_tx()
1625 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); in nv_txrx_reset()
1628 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); in nv_txrx_reset()
1638 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); in nv_mac_reset()
1658 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); in nv_mac_reset()
1662 /* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1668 lockdep_assert_held(&np->hwstats_lock); in nv_update_stats()
1671 np->estats.tx_bytes += readl(base + NvRegTxCnt); in nv_update_stats()
1672 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); in nv_update_stats()
1673 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); in nv_update_stats()
1674 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); in nv_update_stats()
1675 np->estats.tx_late_collision += readl(base + NvRegTxLateCol); in nv_update_stats()
1676 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); in nv_update_stats()
1677 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); in nv_update_stats()
1678 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); in nv_update_stats()
1679 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); in nv_update_stats()
1680 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); in nv_update_stats()
1681 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); in nv_update_stats()
1682 np->estats.rx_late_collision += readl(base + NvRegRxLateCol); in nv_update_stats()
1683 np->estats.rx_runt += readl(base + NvRegRxRunt); in nv_update_stats()
1684 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); in nv_update_stats()
1685 np->estats.rx_over_errors += readl(base + NvRegRxOverflow); in nv_update_stats()
1686 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); in nv_update_stats()
1687 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); in nv_update_stats()
1688 np->estats.rx_length_error += readl(base + NvRegRxLenErr); in nv_update_stats()
1689 np->estats.rx_unicast += readl(base + NvRegRxUnicast); in nv_update_stats()
1690 np->estats.rx_multicast += readl(base + NvRegRxMulticast); in nv_update_stats()
1691 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); in nv_update_stats()
1692 np->estats.rx_packets = in nv_update_stats()
1693 np->estats.rx_unicast + in nv_update_stats()
1694 np->estats.rx_multicast + in nv_update_stats()
1695 np->estats.rx_broadcast; in nv_update_stats()
1696 np->estats.rx_errors_total = in nv_update_stats()
1697 np->estats.rx_crc_errors + in nv_update_stats()
1698 np->estats.rx_over_errors + in nv_update_stats()
1699 np->estats.rx_frame_error + in nv_update_stats()
1700 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) + in nv_update_stats()
1701 np->estats.rx_late_collision + in nv_update_stats()
1702 np->estats.rx_runt + in nv_update_stats()
1703 np->estats.rx_frame_too_long; in nv_update_stats()
1704 np->estats.tx_errors_total = in nv_update_stats()
1705 np->estats.tx_late_collision + in nv_update_stats()
1706 np->estats.tx_fifo_errors + in nv_update_stats()
1707 np->estats.tx_carrier_errors + in nv_update_stats()
1708 np->estats.tx_excess_deferral + in nv_update_stats()
1709 np->estats.tx_retry_error; in nv_update_stats()
1711 if (np->driver_data & DEV_HAS_STATISTICS_V2) { in nv_update_stats()
1712 np->estats.tx_deferral += readl(base + NvRegTxDef); in nv_update_stats()
1713 np->estats.tx_packets += readl(base + NvRegTxFrame); in nv_update_stats()
1714 np->estats.rx_bytes += readl(base + NvRegRxCnt); in nv_update_stats()
1715 np->estats.tx_pause += readl(base + NvRegTxPause); in nv_update_stats()
1716 np->estats.rx_pause += readl(base + NvRegRxPause); in nv_update_stats()
1717 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); in nv_update_stats()
1718 np->estats.rx_errors_total += np->estats.rx_drop_frame; in nv_update_stats()
1721 if (np->driver_data & DEV_HAS_STATISTICS_V3) { in nv_update_stats()
1722 np->estats.tx_unicast += readl(base + NvRegTxUnicast); in nv_update_stats()
1723 np->estats.tx_multicast += readl(base + NvRegTxMulticast); in nv_update_stats()
1724 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast); in nv_update_stats()
1731 struct nv_txrx_stats *src = per_cpu_ptr(np->txrx_stats, cpu); in nv_get_stats()
1737 syncp_start = u64_stats_fetch_begin(&np->swstats_rx_syncp); in nv_get_stats()
1738 rx_packets = src->stat_rx_packets; in nv_get_stats()
1739 rx_bytes = src->stat_rx_bytes; in nv_get_stats()
1740 rx_dropped = src->stat_rx_dropped; in nv_get_stats()
1741 rx_missed_errors = src->stat_rx_missed_errors; in nv_get_stats()
1742 } while (u64_stats_fetch_retry(&np->swstats_rx_syncp, syncp_start)); in nv_get_stats()
1744 storage->rx_packets += rx_packets; in nv_get_stats()
1745 storage->rx_bytes += rx_bytes; in nv_get_stats()
1746 storage->rx_dropped += rx_dropped; in nv_get_stats()
1747 storage->rx_missed_errors += rx_missed_errors; in nv_get_stats()
1750 syncp_start = u64_stats_fetch_begin(&np->swstats_tx_syncp); in nv_get_stats()
1751 tx_packets = src->stat_tx_packets; in nv_get_stats()
1752 tx_bytes = src->stat_tx_bytes; in nv_get_stats()
1753 tx_dropped = src->stat_tx_dropped; in nv_get_stats()
1754 } while (u64_stats_fetch_retry(&np->swstats_tx_syncp, syncp_start)); in nv_get_stats()
1756 storage->tx_packets += tx_packets; in nv_get_stats()
1757 storage->tx_bytes += tx_bytes; in nv_get_stats()
1758 storage->tx_dropped += tx_dropped; in nv_get_stats()
1762 * nv_get_stats64: dev->ndo_get_stats64 function
1764 * Called with rcu_read_lock() held -
1769 __acquires(&netdev_priv(dev)->hwstats_lock) in nv_get_stats64()
1770 __releases(&netdev_priv(dev)->hwstats_lock) in nv_get_stats64()
1790 if (np->driver_data & DEV_HAS_STATISTICS_V123) { in nv_get_stats64()
1791 spin_lock_bh(&np->hwstats_lock); in nv_get_stats64()
1796 storage->rx_errors = np->estats.rx_errors_total; in nv_get_stats64()
1797 storage->tx_errors = np->estats.tx_errors_total; in nv_get_stats64()
1800 storage->multicast = np->estats.rx_multicast; in nv_get_stats64()
1803 storage->rx_length_errors = np->estats.rx_length_error; in nv_get_stats64()
1804 storage->rx_over_errors = np->estats.rx_over_errors; in nv_get_stats64()
1805 storage->rx_crc_errors = np->estats.rx_crc_errors; in nv_get_stats64()
1806 storage->rx_frame_errors = np->estats.rx_frame_align_error; in nv_get_stats64()
1807 storage->rx_fifo_errors = np->estats.rx_drop_frame; in nv_get_stats64()
1810 storage->tx_carrier_errors = np->estats.tx_carrier_errors; in nv_get_stats64()
1811 storage->tx_fifo_errors = np->estats.tx_fifo_errors; in nv_get_stats64()
1813 spin_unlock_bh(&np->hwstats_lock); in nv_get_stats64()
1827 less_rx = np->get_rx.orig; in nv_alloc_rx()
1828 if (less_rx-- == np->rx_ring.orig) in nv_alloc_rx()
1829 less_rx = np->last_rx.orig; in nv_alloc_rx()
1831 while (np->put_rx.orig != less_rx) { in nv_alloc_rx()
1832 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD); in nv_alloc_rx()
1834 np->put_rx_ctx->skb = skb; in nv_alloc_rx()
1835 np->put_rx_ctx->dma = dma_map_single(&np->pci_dev->dev, in nv_alloc_rx()
1836 skb->data, in nv_alloc_rx()
1839 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_alloc_rx()
1840 np->put_rx_ctx->dma))) { in nv_alloc_rx()
1844 np->put_rx_ctx->dma_len = skb_tailroom(skb); in nv_alloc_rx()
1845 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma); in nv_alloc_rx()
1847 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); in nv_alloc_rx()
1848 if (unlikely(np->put_rx.orig++ == np->last_rx.orig)) in nv_alloc_rx()
1849 np->put_rx.orig = np->rx_ring.orig; in nv_alloc_rx()
1850 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) in nv_alloc_rx()
1851 np->put_rx_ctx = np->rx_skb; in nv_alloc_rx()
1854 u64_stats_update_begin(&np->swstats_rx_syncp); in nv_alloc_rx()
1856 u64_stats_update_end(&np->swstats_rx_syncp); in nv_alloc_rx()
1868 less_rx = np->get_rx.ex; in nv_alloc_rx_optimized()
1869 if (less_rx-- == np->rx_ring.ex) in nv_alloc_rx_optimized()
1870 less_rx = np->last_rx.ex; in nv_alloc_rx_optimized()
1872 while (np->put_rx.ex != less_rx) { in nv_alloc_rx_optimized()
1873 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD); in nv_alloc_rx_optimized()
1875 np->put_rx_ctx->skb = skb; in nv_alloc_rx_optimized()
1876 np->put_rx_ctx->dma = dma_map_single(&np->pci_dev->dev, in nv_alloc_rx_optimized()
1877 skb->data, in nv_alloc_rx_optimized()
1880 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_alloc_rx_optimized()
1881 np->put_rx_ctx->dma))) { in nv_alloc_rx_optimized()
1885 np->put_rx_ctx->dma_len = skb_tailroom(skb); in nv_alloc_rx_optimized()
1886 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma)); in nv_alloc_rx_optimized()
1887 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma)); in nv_alloc_rx_optimized()
1889 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); in nv_alloc_rx_optimized()
1890 if (unlikely(np->put_rx.ex++ == np->last_rx.ex)) in nv_alloc_rx_optimized()
1891 np->put_rx.ex = np->rx_ring.ex; in nv_alloc_rx_optimized()
1892 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) in nv_alloc_rx_optimized()
1893 np->put_rx_ctx = np->rx_skb; in nv_alloc_rx_optimized()
1896 u64_stats_update_begin(&np->swstats_rx_syncp); in nv_alloc_rx_optimized()
1898 u64_stats_update_end(&np->swstats_rx_syncp); in nv_alloc_rx_optimized()
1911 napi_schedule(&np->napi); in nv_do_rx_refill()
1919 np->get_rx = np->rx_ring; in nv_init_rx()
1920 np->put_rx = np->rx_ring; in nv_init_rx()
1923 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1]; in nv_init_rx()
1925 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1]; in nv_init_rx()
1926 np->get_rx_ctx = np->rx_skb; in nv_init_rx()
1927 np->put_rx_ctx = np->rx_skb; in nv_init_rx()
1928 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1]; in nv_init_rx()
1930 for (i = 0; i < np->rx_ring_size; i++) { in nv_init_rx()
1932 np->rx_ring.orig[i].flaglen = 0; in nv_init_rx()
1933 np->rx_ring.orig[i].buf = 0; in nv_init_rx()
1935 np->rx_ring.ex[i].flaglen = 0; in nv_init_rx()
1936 np->rx_ring.ex[i].txvlan = 0; in nv_init_rx()
1937 np->rx_ring.ex[i].bufhigh = 0; in nv_init_rx()
1938 np->rx_ring.ex[i].buflow = 0; in nv_init_rx()
1940 np->rx_skb[i].skb = NULL; in nv_init_rx()
1941 np->rx_skb[i].dma = 0; in nv_init_rx()
1950 np->get_tx = np->tx_ring; in nv_init_tx()
1951 np->put_tx = np->tx_ring; in nv_init_tx()
1954 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1]; in nv_init_tx()
1956 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1]; in nv_init_tx()
1957 np->get_tx_ctx = np->tx_skb; in nv_init_tx()
1958 np->put_tx_ctx = np->tx_skb; in nv_init_tx()
1959 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1]; in nv_init_tx()
1960 netdev_reset_queue(np->dev); in nv_init_tx()
1961 np->tx_pkts_in_progress = 0; in nv_init_tx()
1962 np->tx_change_owner = NULL; in nv_init_tx()
1963 np->tx_end_flip = NULL; in nv_init_tx()
1964 np->tx_stop = 0; in nv_init_tx()
1966 for (i = 0; i < np->tx_ring_size; i++) { in nv_init_tx()
1968 np->tx_ring.orig[i].flaglen = 0; in nv_init_tx()
1969 np->tx_ring.orig[i].buf = 0; in nv_init_tx()
1971 np->tx_ring.ex[i].flaglen = 0; in nv_init_tx()
1972 np->tx_ring.ex[i].txvlan = 0; in nv_init_tx()
1973 np->tx_ring.ex[i].bufhigh = 0; in nv_init_tx()
1974 np->tx_ring.ex[i].buflow = 0; in nv_init_tx()
1976 np->tx_skb[i].skb = NULL; in nv_init_tx()
1977 np->tx_skb[i].dma = 0; in nv_init_tx()
1978 np->tx_skb[i].dma_len = 0; in nv_init_tx()
1979 np->tx_skb[i].dma_single = 0; in nv_init_tx()
1980 np->tx_skb[i].first_tx_desc = NULL; in nv_init_tx()
1981 np->tx_skb[i].next_tx_ctx = NULL; in nv_init_tx()
2000 if (tx_skb->dma) { in nv_unmap_txskb()
2001 if (tx_skb->dma_single) in nv_unmap_txskb()
2002 dma_unmap_single(&np->pci_dev->dev, tx_skb->dma, in nv_unmap_txskb()
2003 tx_skb->dma_len, in nv_unmap_txskb()
2006 dma_unmap_page(&np->pci_dev->dev, tx_skb->dma, in nv_unmap_txskb()
2007 tx_skb->dma_len, in nv_unmap_txskb()
2009 tx_skb->dma = 0; in nv_unmap_txskb()
2016 if (tx_skb->skb) { in nv_release_txskb()
2017 dev_kfree_skb_any(tx_skb->skb); in nv_release_txskb()
2018 tx_skb->skb = NULL; in nv_release_txskb()
2029 for (i = 0; i < np->tx_ring_size; i++) { in nv_drain_tx()
2031 np->tx_ring.orig[i].flaglen = 0; in nv_drain_tx()
2032 np->tx_ring.orig[i].buf = 0; in nv_drain_tx()
2034 np->tx_ring.ex[i].flaglen = 0; in nv_drain_tx()
2035 np->tx_ring.ex[i].txvlan = 0; in nv_drain_tx()
2036 np->tx_ring.ex[i].bufhigh = 0; in nv_drain_tx()
2037 np->tx_ring.ex[i].buflow = 0; in nv_drain_tx()
2039 if (nv_release_txskb(np, &np->tx_skb[i])) { in nv_drain_tx()
2040 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_drain_tx()
2042 u64_stats_update_end(&np->swstats_tx_syncp); in nv_drain_tx()
2044 np->tx_skb[i].dma = 0; in nv_drain_tx()
2045 np->tx_skb[i].dma_len = 0; in nv_drain_tx()
2046 np->tx_skb[i].dma_single = 0; in nv_drain_tx()
2047 np->tx_skb[i].first_tx_desc = NULL; in nv_drain_tx()
2048 np->tx_skb[i].next_tx_ctx = NULL; in nv_drain_tx()
2050 np->tx_pkts_in_progress = 0; in nv_drain_tx()
2051 np->tx_change_owner = NULL; in nv_drain_tx()
2052 np->tx_end_flip = NULL; in nv_drain_tx()
2060 for (i = 0; i < np->rx_ring_size; i++) { in nv_drain_rx()
2062 np->rx_ring.orig[i].flaglen = 0; in nv_drain_rx()
2063 np->rx_ring.orig[i].buf = 0; in nv_drain_rx()
2065 np->rx_ring.ex[i].flaglen = 0; in nv_drain_rx()
2066 np->rx_ring.ex[i].txvlan = 0; in nv_drain_rx()
2067 np->rx_ring.ex[i].bufhigh = 0; in nv_drain_rx()
2068 np->rx_ring.ex[i].buflow = 0; in nv_drain_rx()
2071 if (np->rx_skb[i].skb) { in nv_drain_rx()
2072 dma_unmap_single(&np->pci_dev->dev, np->rx_skb[i].dma, in nv_drain_rx()
2073 (skb_end_pointer(np->rx_skb[i].skb) - in nv_drain_rx()
2074 np->rx_skb[i].skb->data), in nv_drain_rx()
2076 dev_kfree_skb(np->rx_skb[i].skb); in nv_drain_rx()
2077 np->rx_skb[i].skb = NULL; in nv_drain_rx()
2090 …return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_r… in nv_get_empty_tx_slots()
2105 * Caller has already gained np->lock. in nv_legacybackoff_reseed()
2195 temp |= main_seedset[seedset][i-1] & 0x3ff; in nv_gear_backoff_reseed()
2196 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR); in nv_gear_backoff_reseed()
2202 * nv_start_xmit: dev->hard_start_xmit function
2209 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); in nv_start_xmit()
2210 unsigned int fragments = skb_shinfo(skb)->nr_frags; in nv_start_xmit()
2215 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); in nv_start_xmit()
2227 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]); in nv_start_xmit()
2230 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); in nv_start_xmit()
2233 spin_lock_irqsave(&np->lock, flags); in nv_start_xmit()
2237 np->tx_stop = 1; in nv_start_xmit()
2238 spin_unlock_irqrestore(&np->lock, flags); in nv_start_xmit()
2246 spin_unlock_irqrestore(&np->lock, flags); in nv_start_xmit()
2248 start_tx = put_tx = np->put_tx.orig; in nv_start_xmit()
2253 np->put_tx_ctx->dma = dma_map_single(&np->pci_dev->dev, in nv_start_xmit()
2254 skb->data + offset, bcnt, in nv_start_xmit()
2256 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_start_xmit()
2257 np->put_tx_ctx->dma))) { in nv_start_xmit()
2258 /* on DMA mapping error - drop the packet */ in nv_start_xmit()
2260 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_start_xmit()
2262 u64_stats_update_end(&np->swstats_tx_syncp); in nv_start_xmit()
2268 np->put_tx_ctx->dma_len = bcnt; in nv_start_xmit()
2269 np->put_tx_ctx->dma_single = 1; in nv_start_xmit()
2270 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); in nv_start_xmit()
2271 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); in nv_start_xmit()
2273 tx_flags = np->tx_flags; in nv_start_xmit()
2275 size -= bcnt; in nv_start_xmit()
2276 if (unlikely(put_tx++ == np->last_tx.orig)) in nv_start_xmit()
2277 put_tx = np->tx_ring.orig; in nv_start_xmit()
2278 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) in nv_start_xmit()
2279 np->put_tx_ctx = np->tx_skb; in nv_start_xmit()
2284 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in nv_start_xmit()
2290 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx; in nv_start_xmit()
2293 np->put_tx_ctx->dma = skb_frag_dma_map( in nv_start_xmit()
2294 &np->pci_dev->dev, in nv_start_xmit()
2298 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_start_xmit()
2299 np->put_tx_ctx->dma))) { in nv_start_xmit()
2304 if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx)) in nv_start_xmit()
2305 tmp_tx_ctx = np->tx_skb; in nv_start_xmit()
2306 } while (tmp_tx_ctx != np->put_tx_ctx); in nv_start_xmit()
2308 np->put_tx_ctx = start_tx_ctx; in nv_start_xmit()
2309 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_start_xmit()
2311 u64_stats_update_end(&np->swstats_tx_syncp); in nv_start_xmit()
2318 np->put_tx_ctx->dma_len = bcnt; in nv_start_xmit()
2319 np->put_tx_ctx->dma_single = 0; in nv_start_xmit()
2320 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); in nv_start_xmit()
2321 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); in nv_start_xmit()
2324 frag_size -= bcnt; in nv_start_xmit()
2325 if (unlikely(put_tx++ == np->last_tx.orig)) in nv_start_xmit()
2326 put_tx = np->tx_ring.orig; in nv_start_xmit()
2327 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) in nv_start_xmit()
2328 np->put_tx_ctx = np->tx_skb; in nv_start_xmit()
2332 if (unlikely(put_tx == np->tx_ring.orig)) in nv_start_xmit()
2333 prev_tx = np->last_tx.orig; in nv_start_xmit()
2335 prev_tx = put_tx - 1; in nv_start_xmit()
2337 if (unlikely(np->put_tx_ctx == np->tx_skb)) in nv_start_xmit()
2338 prev_tx_ctx = np->last_tx_ctx; in nv_start_xmit()
2340 prev_tx_ctx = np->put_tx_ctx - 1; in nv_start_xmit()
2343 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra); in nv_start_xmit()
2346 prev_tx_ctx->skb = skb; in nv_start_xmit()
2349 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); in nv_start_xmit()
2351 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? in nv_start_xmit()
2354 spin_lock_irqsave(&np->lock, flags); in nv_start_xmit()
2357 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); in nv_start_xmit()
2359 netdev_sent_queue(np->dev, skb->len); in nv_start_xmit()
2363 np->put_tx.orig = put_tx; in nv_start_xmit()
2365 spin_unlock_irqrestore(&np->lock, flags); in nv_start_xmit()
2371 txrxctl_kick = NVREG_TXRXCTL_KICK | np->txrxctl_bits; in nv_start_xmit()
2384 unsigned int fragments = skb_shinfo(skb)->nr_frags; in nv_start_xmit_optimized()
2389 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); in nv_start_xmit_optimized()
2402 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]); in nv_start_xmit_optimized()
2405 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); in nv_start_xmit_optimized()
2408 spin_lock_irqsave(&np->lock, flags); in nv_start_xmit_optimized()
2412 np->tx_stop = 1; in nv_start_xmit_optimized()
2413 spin_unlock_irqrestore(&np->lock, flags); in nv_start_xmit_optimized()
2422 spin_unlock_irqrestore(&np->lock, flags); in nv_start_xmit_optimized()
2424 start_tx = put_tx = np->put_tx.ex; in nv_start_xmit_optimized()
2425 start_tx_ctx = np->put_tx_ctx; in nv_start_xmit_optimized()
2430 np->put_tx_ctx->dma = dma_map_single(&np->pci_dev->dev, in nv_start_xmit_optimized()
2431 skb->data + offset, bcnt, in nv_start_xmit_optimized()
2433 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_start_xmit_optimized()
2434 np->put_tx_ctx->dma))) { in nv_start_xmit_optimized()
2435 /* on DMA mapping error - drop the packet */ in nv_start_xmit_optimized()
2437 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_start_xmit_optimized()
2439 u64_stats_update_end(&np->swstats_tx_syncp); in nv_start_xmit_optimized()
2445 np->put_tx_ctx->dma_len = bcnt; in nv_start_xmit_optimized()
2446 np->put_tx_ctx->dma_single = 1; in nv_start_xmit_optimized()
2447 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); in nv_start_xmit_optimized()
2448 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); in nv_start_xmit_optimized()
2449 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); in nv_start_xmit_optimized()
2453 size -= bcnt; in nv_start_xmit_optimized()
2454 if (unlikely(put_tx++ == np->last_tx.ex)) in nv_start_xmit_optimized()
2455 put_tx = np->tx_ring.ex; in nv_start_xmit_optimized()
2456 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) in nv_start_xmit_optimized()
2457 np->put_tx_ctx = np->tx_skb; in nv_start_xmit_optimized()
2462 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in nv_start_xmit_optimized()
2469 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx; in nv_start_xmit_optimized()
2470 np->put_tx_ctx->dma = skb_frag_dma_map( in nv_start_xmit_optimized()
2471 &np->pci_dev->dev, in nv_start_xmit_optimized()
2476 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_start_xmit_optimized()
2477 np->put_tx_ctx->dma))) { in nv_start_xmit_optimized()
2482 if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx)) in nv_start_xmit_optimized()
2483 tmp_tx_ctx = np->tx_skb; in nv_start_xmit_optimized()
2484 } while (tmp_tx_ctx != np->put_tx_ctx); in nv_start_xmit_optimized()
2486 np->put_tx_ctx = start_tx_ctx; in nv_start_xmit_optimized()
2487 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_start_xmit_optimized()
2489 u64_stats_update_end(&np->swstats_tx_syncp); in nv_start_xmit_optimized()
2495 np->put_tx_ctx->dma_len = bcnt; in nv_start_xmit_optimized()
2496 np->put_tx_ctx->dma_single = 0; in nv_start_xmit_optimized()
2497 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); in nv_start_xmit_optimized()
2498 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); in nv_start_xmit_optimized()
2499 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); in nv_start_xmit_optimized()
2502 frag_size -= bcnt; in nv_start_xmit_optimized()
2503 if (unlikely(put_tx++ == np->last_tx.ex)) in nv_start_xmit_optimized()
2504 put_tx = np->tx_ring.ex; in nv_start_xmit_optimized()
2505 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) in nv_start_xmit_optimized()
2506 np->put_tx_ctx = np->tx_skb; in nv_start_xmit_optimized()
2510 if (unlikely(put_tx == np->tx_ring.ex)) in nv_start_xmit_optimized()
2511 prev_tx = np->last_tx.ex; in nv_start_xmit_optimized()
2513 prev_tx = put_tx - 1; in nv_start_xmit_optimized()
2515 if (unlikely(np->put_tx_ctx == np->tx_skb)) in nv_start_xmit_optimized()
2516 prev_tx_ctx = np->last_tx_ctx; in nv_start_xmit_optimized()
2518 prev_tx_ctx = np->put_tx_ctx - 1; in nv_start_xmit_optimized()
2521 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET); in nv_start_xmit_optimized()
2524 prev_tx_ctx->skb = skb; in nv_start_xmit_optimized()
2527 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); in nv_start_xmit_optimized()
2529 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? in nv_start_xmit_optimized()
2534 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | in nv_start_xmit_optimized()
2537 start_tx->txvlan = 0; in nv_start_xmit_optimized()
2539 spin_lock_irqsave(&np->lock, flags); in nv_start_xmit_optimized()
2541 if (np->tx_limit) { in nv_start_xmit_optimized()
2547 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) { in nv_start_xmit_optimized()
2548 if (!np->tx_change_owner) in nv_start_xmit_optimized()
2549 np->tx_change_owner = start_tx_ctx; in nv_start_xmit_optimized()
2553 start_tx_ctx->first_tx_desc = start_tx; in nv_start_xmit_optimized()
2554 start_tx_ctx->next_tx_ctx = np->put_tx_ctx; in nv_start_xmit_optimized()
2555 np->tx_end_flip = np->put_tx_ctx; in nv_start_xmit_optimized()
2557 np->tx_pkts_in_progress++; in nv_start_xmit_optimized()
2562 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); in nv_start_xmit_optimized()
2564 netdev_sent_queue(np->dev, skb->len); in nv_start_xmit_optimized()
2568 np->put_tx.ex = put_tx; in nv_start_xmit_optimized()
2570 spin_unlock_irqrestore(&np->lock, flags); in nv_start_xmit_optimized()
2576 txrxctl_kick = NVREG_TXRXCTL_KICK | np->txrxctl_bits; in nv_start_xmit_optimized()
2587 np->tx_pkts_in_progress--; in nv_tx_flip_ownership()
2588 if (np->tx_change_owner) { in nv_tx_flip_ownership()
2589 np->tx_change_owner->first_tx_desc->flaglen |= in nv_tx_flip_ownership()
2591 np->tx_pkts_in_progress++; in nv_tx_flip_ownership()
2593 np->tx_change_owner = np->tx_change_owner->next_tx_ctx; in nv_tx_flip_ownership()
2594 if (np->tx_change_owner == np->tx_end_flip) in nv_tx_flip_ownership()
2595 np->tx_change_owner = NULL; in nv_tx_flip_ownership()
2597 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_tx_flip_ownership()
2604 * Caller must own np->lock.
2611 struct ring_desc *orig_get_tx = np->get_tx.orig; in nv_tx_done()
2614 while ((np->get_tx.orig != np->put_tx.orig) && in nv_tx_done()
2615 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) && in nv_tx_done()
2618 nv_unmap_txskb(np, np->get_tx_ctx); in nv_tx_done()
2620 if (np->desc_ver == DESC_VER_1) { in nv_tx_done()
2629 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_tx_done()
2631 len = np->get_tx_ctx->skb->len; in nv_tx_done()
2633 u64_stats_update_end(&np->swstats_tx_syncp); in nv_tx_done()
2635 bytes_compl += np->get_tx_ctx->skb->len; in nv_tx_done()
2636 dev_kfree_skb_any(np->get_tx_ctx->skb); in nv_tx_done()
2637 np->get_tx_ctx->skb = NULL; in nv_tx_done()
2649 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_tx_done()
2651 len = np->get_tx_ctx->skb->len; in nv_tx_done()
2653 u64_stats_update_end(&np->swstats_tx_syncp); in nv_tx_done()
2655 bytes_compl += np->get_tx_ctx->skb->len; in nv_tx_done()
2656 dev_kfree_skb_any(np->get_tx_ctx->skb); in nv_tx_done()
2657 np->get_tx_ctx->skb = NULL; in nv_tx_done()
2661 if (unlikely(np->get_tx.orig++ == np->last_tx.orig)) in nv_tx_done()
2662 np->get_tx.orig = np->tx_ring.orig; in nv_tx_done()
2663 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) in nv_tx_done()
2664 np->get_tx_ctx = np->tx_skb; in nv_tx_done()
2667 netdev_completed_queue(np->dev, tx_work, bytes_compl); in nv_tx_done()
2669 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) { in nv_tx_done()
2670 np->tx_stop = 0; in nv_tx_done()
2681 struct ring_desc_ex *orig_get_tx = np->get_tx.ex; in nv_tx_done_optimized()
2684 while ((np->get_tx.ex != np->put_tx.ex) && in nv_tx_done_optimized()
2685 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) && in nv_tx_done_optimized()
2688 nv_unmap_txskb(np, np->get_tx_ctx); in nv_tx_done_optimized()
2694 if (np->driver_data & DEV_HAS_GEAR_MODE) in nv_tx_done_optimized()
2702 u64_stats_update_begin(&np->swstats_tx_syncp); in nv_tx_done_optimized()
2704 len = np->get_tx_ctx->skb->len; in nv_tx_done_optimized()
2706 u64_stats_update_end(&np->swstats_tx_syncp); in nv_tx_done_optimized()
2709 bytes_cleaned += np->get_tx_ctx->skb->len; in nv_tx_done_optimized()
2710 dev_kfree_skb_any(np->get_tx_ctx->skb); in nv_tx_done_optimized()
2711 np->get_tx_ctx->skb = NULL; in nv_tx_done_optimized()
2714 if (np->tx_limit) in nv_tx_done_optimized()
2718 if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) in nv_tx_done_optimized()
2719 np->get_tx.ex = np->tx_ring.ex; in nv_tx_done_optimized()
2720 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) in nv_tx_done_optimized()
2721 np->get_tx_ctx = np->tx_skb; in nv_tx_done_optimized()
2724 netdev_completed_queue(np->dev, tx_work, bytes_cleaned); in nv_tx_done_optimized()
2726 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) { in nv_tx_done_optimized()
2727 np->tx_stop = 0; in nv_tx_done_optimized()
2734 * nv_tx_timeout: dev->tx_timeout function
2745 if (np->msi_flags & NV_MSI_X_ENABLED) in nv_tx_timeout()
2755 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr); in nv_tx_timeout()
2757 for (i = 0; i <= np->register_size; i += 32) { in nv_tx_timeout()
2768 for (i = 0; i < np->tx_ring_size; i += 4) { in nv_tx_timeout()
2774 le32_to_cpu(np->tx_ring.orig[i].buf), in nv_tx_timeout()
2775 le32_to_cpu(np->tx_ring.orig[i].flaglen), in nv_tx_timeout()
2776 le32_to_cpu(np->tx_ring.orig[i+1].buf), in nv_tx_timeout()
2777 le32_to_cpu(np->tx_ring.orig[i+1].flaglen), in nv_tx_timeout()
2778 le32_to_cpu(np->tx_ring.orig[i+2].buf), in nv_tx_timeout()
2779 le32_to_cpu(np->tx_ring.orig[i+2].flaglen), in nv_tx_timeout()
2780 le32_to_cpu(np->tx_ring.orig[i+3].buf), in nv_tx_timeout()
2781 le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); in nv_tx_timeout()
2789 le32_to_cpu(np->tx_ring.ex[i].bufhigh), in nv_tx_timeout()
2790 le32_to_cpu(np->tx_ring.ex[i].buflow), in nv_tx_timeout()
2791 le32_to_cpu(np->tx_ring.ex[i].flaglen), in nv_tx_timeout()
2792 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), in nv_tx_timeout()
2793 le32_to_cpu(np->tx_ring.ex[i+1].buflow), in nv_tx_timeout()
2794 le32_to_cpu(np->tx_ring.ex[i+1].flaglen), in nv_tx_timeout()
2795 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), in nv_tx_timeout()
2796 le32_to_cpu(np->tx_ring.ex[i+2].buflow), in nv_tx_timeout()
2797 le32_to_cpu(np->tx_ring.ex[i+2].flaglen), in nv_tx_timeout()
2798 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), in nv_tx_timeout()
2799 le32_to_cpu(np->tx_ring.ex[i+3].buflow), in nv_tx_timeout()
2800 le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); in nv_tx_timeout()
2805 spin_lock_irq(&np->lock); in nv_tx_timeout()
2811 saved_tx_limit = np->tx_limit; in nv_tx_timeout()
2812 np->tx_limit = 0; /* prevent giving HW any limited pkts */ in nv_tx_timeout()
2813 np->tx_stop = 0; /* prevent waking tx queue */ in nv_tx_timeout()
2815 nv_tx_done(dev, np->tx_ring_size); in nv_tx_timeout()
2817 nv_tx_done_optimized(dev, np->tx_ring_size); in nv_tx_timeout()
2820 if (np->tx_change_owner) in nv_tx_timeout()
2821 put_tx.ex = np->tx_change_owner->first_tx_desc; in nv_tx_timeout()
2823 put_tx = np->put_tx; in nv_tx_timeout()
2830 np->get_tx = np->put_tx = put_tx; in nv_tx_timeout()
2831 np->tx_limit = saved_tx_limit; in nv_tx_timeout()
2836 spin_unlock_irq(&np->lock); in nv_tx_timeout()
2849 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) { in nv_getlen()
2850 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto); in nv_getlen()
2853 protolen = ntohs(((struct ethhdr *)packet)->h_proto); in nv_getlen()
2871 return -1; in nv_getlen()
2876 return -1; in nv_getlen()
2885 u64_stats_update_begin(&np->swstats_rx_syncp); in rx_missing_handler()
2887 u64_stats_update_end(&np->swstats_rx_syncp); in rx_missing_handler()
2899 while ((np->get_rx.orig != np->put_rx.orig) && in nv_rx_process()
2900 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) && in nv_rx_process()
2904 * the packet is for us - immediately tear down the pci mapping. in nv_rx_process()
2908 dma_unmap_single(&np->pci_dev->dev, np->get_rx_ctx->dma, in nv_rx_process()
2909 np->get_rx_ctx->dma_len, in nv_rx_process()
2911 skb = np->get_rx_ctx->skb; in nv_rx_process()
2912 np->get_rx_ctx->skb = NULL; in nv_rx_process()
2915 if (np->desc_ver == DESC_VER_1) { in nv_rx_process()
2920 len = nv_getlen(dev, skb->data, len); in nv_rx_process()
2929 len--; in nv_rx_process()
2947 len = nv_getlen(dev, skb->data, len); in nv_rx_process()
2956 len--; in nv_rx_process()
2966 skb->ip_summed = CHECKSUM_UNNECESSARY; in nv_rx_process()
2972 /* got a valid packet - forward it to the network core */ in nv_rx_process()
2974 skb->protocol = eth_type_trans(skb, dev); in nv_rx_process()
2975 napi_gro_receive(&np->napi, skb); in nv_rx_process()
2976 u64_stats_update_begin(&np->swstats_rx_syncp); in nv_rx_process()
2979 u64_stats_update_end(&np->swstats_rx_syncp); in nv_rx_process()
2981 if (unlikely(np->get_rx.orig++ == np->last_rx.orig)) in nv_rx_process()
2982 np->get_rx.orig = np->rx_ring.orig; in nv_rx_process()
2983 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) in nv_rx_process()
2984 np->get_rx_ctx = np->rx_skb; in nv_rx_process()
3001 while ((np->get_rx.ex != np->put_rx.ex) && in nv_rx_process_optimized()
3002 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) && in nv_rx_process_optimized()
3006 * the packet is for us - immediately tear down the pci mapping. in nv_rx_process_optimized()
3010 dma_unmap_single(&np->pci_dev->dev, np->get_rx_ctx->dma, in nv_rx_process_optimized()
3011 np->get_rx_ctx->dma_len, in nv_rx_process_optimized()
3013 skb = np->get_rx_ctx->skb; in nv_rx_process_optimized()
3014 np->get_rx_ctx->skb = NULL; in nv_rx_process_optimized()
3021 len = nv_getlen(dev, skb->data, len); in nv_rx_process_optimized()
3030 len--; in nv_rx_process_optimized()
3041 skb->ip_summed = CHECKSUM_UNNECESSARY; in nv_rx_process_optimized()
3043 /* got a valid packet - forward it to the network core */ in nv_rx_process_optimized()
3045 skb->protocol = eth_type_trans(skb, dev); in nv_rx_process_optimized()
3046 prefetch(skb->data); in nv_rx_process_optimized()
3048 vlanflags = le32_to_cpu(np->get_rx.ex->buflow); in nv_rx_process_optimized()
3055 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX && in nv_rx_process_optimized()
3061 napi_gro_receive(&np->napi, skb); in nv_rx_process_optimized()
3062 u64_stats_update_begin(&np->swstats_rx_syncp); in nv_rx_process_optimized()
3065 u64_stats_update_end(&np->swstats_rx_syncp); in nv_rx_process_optimized()
3070 if (unlikely(np->get_rx.ex++ == np->last_rx.ex)) in nv_rx_process_optimized()
3071 np->get_rx.ex = np->rx_ring.ex; in nv_rx_process_optimized()
3072 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) in nv_rx_process_optimized()
3073 np->get_rx_ctx = np->rx_skb; in nv_rx_process_optimized()
3085 if (dev->mtu <= ETH_DATA_LEN) in set_bufsize()
3086 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; in set_bufsize()
3088 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; in set_bufsize()
3092 * nv_change_mtu: dev->change_mtu function
3100 old_mtu = dev->mtu; in nv_change_mtu()
3101 WRITE_ONCE(dev->mtu, new_mtu); in nv_change_mtu()
3120 spin_lock(&np->lock); in nv_change_mtu()
3129 if (!np->in_shutdown) in nv_change_mtu()
3130 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_change_mtu()
3133 writel(np->rx_buf_sz, base + NvRegOffloadConfig); in nv_change_mtu()
3135 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH… in nv_change_mtu()
3138 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_change_mtu()
3143 spin_unlock(&np->lock); in nv_change_mtu()
3157 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + in nv_copy_mac_to_hw()
3158 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); in nv_copy_mac_to_hw()
3159 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); in nv_copy_mac_to_hw()
3166 * nv_set_mac_address: dev->set_mac_address function
3174 if (!is_valid_ether_addr(macaddr->sa_data)) in nv_set_mac_address()
3175 return -EADDRNOTAVAIL; in nv_set_mac_address()
3178 eth_hw_addr_set(dev, macaddr->sa_data); in nv_set_mac_address()
3183 spin_lock_irq(&np->lock); in nv_set_mac_address()
3193 spin_unlock_irq(&np->lock); in nv_set_mac_address()
3203 * nv_set_multicast: dev->set_multicast function
3217 if (dev->flags & IFF_PROMISC) { in nv_set_multicast()
3222 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) { in nv_set_multicast()
3227 if (dev->flags & IFF_ALLMULTI) { in nv_set_multicast()
3233 unsigned char *hw_addr = ha->addr; in nv_set_multicast()
3255 spin_lock_irq(&np->lock); in nv_set_multicast()
3263 spin_unlock_irq(&np->lock); in nv_set_multicast()
3271 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE); in nv_update_pause()
3273 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) { in nv_update_pause()
3277 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; in nv_update_pause()
3282 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) { in nv_update_pause()
3286 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) in nv_update_pause()
3288 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) { in nv_update_pause()
3295 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; in nv_update_pause()
3310 np->linkspeed = NVREG_LINKSPEED_FORCE|speed; in nv_force_linkspeed()
3311 np->duplex = duplex; in nv_force_linkspeed()
3314 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_force_linkspeed()
3316 np->gigabit = PHY_GIGABIT; in nv_force_linkspeed()
3319 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) in nv_force_linkspeed()
3321 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) in nv_force_linkspeed()
3323 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) in nv_force_linkspeed()
3330 if (np->duplex == 0) in nv_force_linkspeed()
3332 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) in nv_force_linkspeed()
3334 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == in nv_force_linkspeed()
3340 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == in nv_force_linkspeed()
3350 if (np->desc_ver == DESC_VER_1) { in nv_force_linkspeed()
3353 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == in nv_force_linkspeed()
3361 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), in nv_force_linkspeed()
3364 writel(np->linkspeed, base + NvRegLinkSpeed); in nv_force_linkspeed()
3369 * nv_update_linkspeed - Setup the MAC according to the link partner
3386 int newls = np->linkspeed; in nv_update_linkspeed()
3387 int newdup = np->duplex; in nv_update_linkspeed()
3398 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_update_linkspeed()
3411 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3412 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3421 if (np->autoneg == 0) { in nv_update_linkspeed()
3422 if (np->fixed_mode & LPA_100FULL) { in nv_update_linkspeed()
3425 } else if (np->fixed_mode & LPA_100HALF) { in nv_update_linkspeed()
3428 } else if (np->fixed_mode & LPA_10FULL) { in nv_update_linkspeed()
3440 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ in nv_update_linkspeed()
3447 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_update_linkspeed()
3448 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); in nv_update_linkspeed()
3451 if (np->gigabit == PHY_GIGABIT) { in nv_update_linkspeed()
3452 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_update_linkspeed()
3453 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); in nv_update_linkspeed()
3483 if (np->duplex == newdup && np->linkspeed == newls) in nv_update_linkspeed()
3486 np->duplex = newdup; in nv_update_linkspeed()
3487 np->linkspeed = newls; in nv_update_linkspeed()
3499 if (np->gigabit == PHY_GIGABIT) { in nv_update_linkspeed()
3502 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) || in nv_update_linkspeed()
3503 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)) in nv_update_linkspeed()
3505 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) in nv_update_linkspeed()
3512 if (np->duplex == 0) in nv_update_linkspeed()
3514 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) in nv_update_linkspeed()
3516 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) in nv_update_linkspeed()
3520 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ in nv_update_linkspeed()
3522 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) { in nv_update_linkspeed()
3525 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) { in nv_update_linkspeed()
3526 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10) in nv_update_linkspeed()
3535 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) in nv_update_linkspeed()
3542 if (np->desc_ver == DESC_VER_1) { in nv_update_linkspeed()
3545 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) in nv_update_linkspeed()
3552 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), in nv_update_linkspeed()
3555 writel(np->linkspeed, base + NvRegLinkSpeed); in nv_update_linkspeed()
3560 if (netif_running(dev) && (np->duplex != 0)) { in nv_update_linkspeed()
3561 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { in nv_update_linkspeed()
3569 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) in nv_update_linkspeed()
3580 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) in nv_update_linkspeed()
3588 pause_flags = np->pause_flags; in nv_update_linkspeed()
3638 if (np->msi_flags & NV_MSI_ENABLED) { in nv_msi_workaround()
3639 u8 __iomem *base = np->base; in nv_msi_workaround()
3653 np->quiet_count = 0; in nv_change_interrupt_mode()
3654 if (np->irqmask != NVREG_IRQMASK_CPU) { in nv_change_interrupt_mode()
3655 np->irqmask = NVREG_IRQMASK_CPU; in nv_change_interrupt_mode()
3659 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) { in nv_change_interrupt_mode()
3660 np->quiet_count++; in nv_change_interrupt_mode()
3664 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) { in nv_change_interrupt_mode()
3665 np->irqmask = NVREG_IRQMASK_THROUGHPUT; in nv_change_interrupt_mode()
3680 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { in nv_nic_irq()
3681 np->events = readl(base + NvRegIrqStatus); in nv_nic_irq()
3682 writel(np->events, base + NvRegIrqStatus); in nv_nic_irq()
3684 np->events = readl(base + NvRegMSIXIrqStatus); in nv_nic_irq()
3685 writel(np->events, base + NvRegMSIXIrqStatus); in nv_nic_irq()
3687 if (!(np->events & np->irqmask)) in nv_nic_irq()
3692 if (napi_schedule_prep(&np->napi)) { in nv_nic_irq()
3697 __napi_schedule(&np->napi); in nv_nic_irq()
3713 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { in nv_nic_irq_optimized()
3714 np->events = readl(base + NvRegIrqStatus); in nv_nic_irq_optimized()
3715 writel(np->events, base + NvRegIrqStatus); in nv_nic_irq_optimized()
3717 np->events = readl(base + NvRegMSIXIrqStatus); in nv_nic_irq_optimized()
3718 writel(np->events, base + NvRegMSIXIrqStatus); in nv_nic_irq_optimized()
3720 if (!(np->events & np->irqmask)) in nv_nic_irq_optimized()
3725 if (napi_schedule_prep(&np->napi)) { in nv_nic_irq_optimized()
3730 __napi_schedule(&np->napi); in nv_nic_irq_optimized()
3749 if (!(events & np->irqmask)) in nv_nic_irq_tx()
3752 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_tx()
3754 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_tx()
3757 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_tx()
3762 if (!np->in_shutdown) { in nv_nic_irq_tx()
3763 np->nic_poll_irq |= NVREG_IRQ_TX_ALL; in nv_nic_irq_tx()
3764 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); in nv_nic_irq_tx()
3766 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_tx()
3780 struct net_device *dev = np->dev; in nv_napi_poll()
3788 spin_lock_irqsave(&np->lock, flags); in nv_napi_poll()
3789 tx_work += nv_tx_done(dev, np->tx_ring_size); in nv_napi_poll()
3790 spin_unlock_irqrestore(&np->lock, flags); in nv_napi_poll()
3792 rx_count = nv_rx_process(dev, budget - rx_work); in nv_napi_poll()
3795 spin_lock_irqsave(&np->lock, flags); in nv_napi_poll()
3796 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size); in nv_napi_poll()
3797 spin_unlock_irqrestore(&np->lock, flags); in nv_napi_poll()
3800 budget - rx_work); in nv_napi_poll()
3807 spin_lock_irqsave(&np->lock, flags); in nv_napi_poll()
3808 if (!np->in_shutdown) in nv_napi_poll()
3809 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_napi_poll()
3810 spin_unlock_irqrestore(&np->lock, flags); in nv_napi_poll()
3815 if (unlikely(np->events & NVREG_IRQ_LINK)) { in nv_napi_poll()
3816 spin_lock_irqsave(&np->lock, flags); in nv_napi_poll()
3818 spin_unlock_irqrestore(&np->lock, flags); in nv_napi_poll()
3820 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { in nv_napi_poll()
3821 spin_lock_irqsave(&np->lock, flags); in nv_napi_poll()
3823 spin_unlock_irqrestore(&np->lock, flags); in nv_napi_poll()
3824 np->link_timeout = jiffies + LINK_TIMEOUT; in nv_napi_poll()
3826 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) { in nv_napi_poll()
3827 spin_lock_irqsave(&np->lock, flags); in nv_napi_poll()
3828 if (!np->in_shutdown) { in nv_napi_poll()
3829 np->nic_poll_irq = np->irqmask; in nv_napi_poll()
3830 np->recover_error = 1; in nv_napi_poll()
3831 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); in nv_napi_poll()
3833 spin_unlock_irqrestore(&np->lock, flags); in nv_napi_poll()
3839 /* re-enable interrupts in nv_napi_poll()
3843 writel(np->irqmask, base + NvRegIrqMask); in nv_napi_poll()
3861 if (!(events & np->irqmask)) in nv_nic_irq_rx()
3866 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_rx()
3867 if (!np->in_shutdown) in nv_nic_irq_rx()
3868 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_nic_irq_rx()
3869 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_rx()
3874 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_rx()
3879 if (!np->in_shutdown) { in nv_nic_irq_rx()
3880 np->nic_poll_irq |= NVREG_IRQ_RX_ALL; in nv_nic_irq_rx()
3881 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); in nv_nic_irq_rx()
3883 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_rx()
3906 if (!(events & np->irqmask)) in nv_nic_irq_other()
3910 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_other()
3912 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_other()
3915 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_other()
3917 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_other()
3919 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { in nv_nic_irq_other()
3920 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_other()
3922 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_other()
3923 np->link_timeout = jiffies + LINK_TIMEOUT; in nv_nic_irq_other()
3926 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_other()
3931 if (!np->in_shutdown) { in nv_nic_irq_other()
3932 np->nic_poll_irq |= NVREG_IRQ_OTHER; in nv_nic_irq_other()
3933 np->recover_error = 1; in nv_nic_irq_other()
3934 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); in nv_nic_irq_other()
3936 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_other()
3940 spin_lock_irqsave(&np->lock, flags); in nv_nic_irq_other()
3945 if (!np->in_shutdown) { in nv_nic_irq_other()
3946 np->nic_poll_irq |= NVREG_IRQ_OTHER; in nv_nic_irq_other()
3947 mod_timer(&np->nic_poll, jiffies + POLL_WAIT); in nv_nic_irq_other()
3949 spin_unlock_irqrestore(&np->lock, flags); in nv_nic_irq_other()
3967 if (!(np->msi_flags & NV_MSI_X_ENABLED)) { in nv_nic_irq_test()
3980 spin_lock(&np->lock); in nv_nic_irq_test()
3981 np->intr_test = 1; in nv_nic_irq_test()
3982 spin_unlock(&np->lock); in nv_nic_irq_test()
4028 if (np->msi_flags & NV_MSI_X_CAPABLE) { in nv_request_irq()
4029 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) in nv_request_irq()
4030 np->msi_x_entry[i].entry = i; in nv_request_irq()
4031 ret = pci_enable_msix_range(np->pci_dev, in nv_request_irq()
4032 np->msi_x_entry, in nv_request_irq()
4033 np->msi_flags & NV_MSI_X_VECTORS_MASK, in nv_request_irq()
4034 np->msi_flags & NV_MSI_X_VECTORS_MASK); in nv_request_irq()
4036 np->msi_flags |= NV_MSI_X_ENABLED; in nv_request_irq()
4039 sprintf(np->name_rx, "%s-rx", dev->name); in nv_request_irq()
4040 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, in nv_request_irq()
4041 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev); in nv_request_irq()
4046 pci_disable_msix(np->pci_dev); in nv_request_irq()
4047 np->msi_flags &= ~NV_MSI_X_ENABLED; in nv_request_irq()
4051 sprintf(np->name_tx, "%s-tx", dev->name); in nv_request_irq()
4052 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, in nv_request_irq()
4053 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev); in nv_request_irq()
4058 pci_disable_msix(np->pci_dev); in nv_request_irq()
4059 np->msi_flags &= ~NV_MSI_X_ENABLED; in nv_request_irq()
4063 sprintf(np->name_other, "%s-other", dev->name); in nv_request_irq()
4064 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, in nv_request_irq()
4065 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev); in nv_request_irq()
4070 pci_disable_msix(np->pci_dev); in nv_request_irq()
4071 np->msi_flags &= ~NV_MSI_X_ENABLED; in nv_request_irq()
4082 ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, in nv_request_irq()
4083 handler, IRQF_SHARED, dev->name, dev); in nv_request_irq()
4088 pci_disable_msix(np->pci_dev); in nv_request_irq()
4089 np->msi_flags &= ~NV_MSI_X_ENABLED; in nv_request_irq()
4097 netdev_info(dev, "MSI-X enabled\n"); in nv_request_irq()
4101 if (np->msi_flags & NV_MSI_CAPABLE) { in nv_request_irq()
4102 ret = pci_enable_msi(np->pci_dev); in nv_request_irq()
4104 np->msi_flags |= NV_MSI_ENABLED; in nv_request_irq()
4105 ret = request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev); in nv_request_irq()
4109 pci_disable_msi(np->pci_dev); in nv_request_irq()
4110 np->msi_flags &= ~NV_MSI_ENABLED; in nv_request_irq()
4124 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) in nv_request_irq()
4129 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); in nv_request_irq()
4131 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); in nv_request_irq()
4141 if (np->msi_flags & NV_MSI_X_ENABLED) { in nv_free_irq()
4142 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) in nv_free_irq()
4143 free_irq(np->msi_x_entry[i].vector, dev); in nv_free_irq()
4144 pci_disable_msix(np->pci_dev); in nv_free_irq()
4145 np->msi_flags &= ~NV_MSI_X_ENABLED; in nv_free_irq()
4147 free_irq(np->pci_dev->irq, dev); in nv_free_irq()
4148 if (np->msi_flags & NV_MSI_ENABLED) { in nv_free_irq()
4149 pci_disable_msi(np->pci_dev); in nv_free_irq()
4150 np->msi_flags &= ~NV_MSI_ENABLED; in nv_free_irq()
4158 struct net_device *dev = np->dev; in nv_do_nic_poll()
4171 if (np->msi_flags & NV_MSI_X_ENABLED) in nv_do_nic_poll()
4172 irq = np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector; in nv_do_nic_poll()
4174 irq = np->pci_dev->irq; in nv_do_nic_poll()
4175 mask = np->irqmask; in nv_do_nic_poll()
4177 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { in nv_do_nic_poll()
4178 irq = np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector; in nv_do_nic_poll()
4181 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { in nv_do_nic_poll()
4182 irq = np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector; in nv_do_nic_poll()
4185 if (np->nic_poll_irq & NVREG_IRQ_OTHER) { in nv_do_nic_poll()
4186 irq = np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector; in nv_do_nic_poll()
4194 if (np->recover_error) { in nv_do_nic_poll()
4195 np->recover_error = 0; in nv_do_nic_poll()
4200 spin_lock(&np->lock); in nv_do_nic_poll()
4203 if (np->driver_data & DEV_HAS_POWER_CNTRL) in nv_do_nic_poll()
4211 if (!np->in_shutdown) in nv_do_nic_poll()
4212 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_do_nic_poll()
4215 writel(np->rx_buf_sz, base + NvRegOffloadConfig); in nv_do_nic_poll()
4217 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH… in nv_do_nic_poll()
4220 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_do_nic_poll()
4223 if (!(np->msi_flags & NV_MSI_X_ENABLED)) in nv_do_nic_poll()
4230 spin_unlock(&np->lock); in nv_do_nic_poll()
4240 np->nic_poll_irq = 0; in nv_do_nic_poll()
4246 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { in nv_do_nic_poll()
4247 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL; in nv_do_nic_poll()
4250 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { in nv_do_nic_poll()
4251 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL; in nv_do_nic_poll()
4254 if (np->nic_poll_irq & NVREG_IRQ_OTHER) { in nv_do_nic_poll()
4255 np->nic_poll_irq &= ~NVREG_IRQ_OTHER; in nv_do_nic_poll()
4268 nv_do_nic_poll(&np->nic_poll); in nv_poll_controller()
4273 __acquires(&netdev_priv(dev)->hwstats_lock) in nv_do_stats_poll()
4274 __releases(&netdev_priv(dev)->hwstats_lock) in nv_do_stats_poll()
4277 struct net_device *dev = np->dev; in nv_do_stats_poll()
4281 if (spin_trylock(&np->hwstats_lock)) { in nv_do_stats_poll()
4283 spin_unlock(&np->hwstats_lock); in nv_do_stats_poll()
4286 if (!np->in_shutdown) in nv_do_stats_poll()
4287 mod_timer(&np->stats_poll, in nv_do_stats_poll()
4294 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); in nv_get_drvinfo()
4295 strscpy(info->version, FORCEDETH_VERSION, sizeof(info->version)); in nv_get_drvinfo()
4296 strscpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); in nv_get_drvinfo()
4302 wolinfo->supported = WAKE_MAGIC; in nv_get_wol()
4304 spin_lock_irq(&np->lock); in nv_get_wol()
4305 if (np->wolenabled) in nv_get_wol()
4306 wolinfo->wolopts = WAKE_MAGIC; in nv_get_wol()
4307 spin_unlock_irq(&np->lock); in nv_get_wol()
4316 if (wolinfo->wolopts == 0) { in nv_set_wol()
4317 np->wolenabled = 0; in nv_set_wol()
4318 } else if (wolinfo->wolopts & WAKE_MAGIC) { in nv_set_wol()
4319 np->wolenabled = 1; in nv_set_wol()
4323 spin_lock_irq(&np->lock); in nv_set_wol()
4325 spin_unlock_irq(&np->lock); in nv_set_wol()
4327 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled); in nv_set_wol()
4338 spin_lock_irq(&np->lock); in nv_get_link_ksettings()
4339 cmd->base.port = PORT_MII; in nv_get_link_ksettings()
4351 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) { in nv_get_link_ksettings()
4362 speed = -1; in nv_get_link_ksettings()
4365 cmd->base.duplex = DUPLEX_HALF; in nv_get_link_ksettings()
4366 if (np->duplex) in nv_get_link_ksettings()
4367 cmd->base.duplex = DUPLEX_FULL; in nv_get_link_ksettings()
4370 cmd->base.duplex = DUPLEX_UNKNOWN; in nv_get_link_ksettings()
4372 cmd->base.speed = speed; in nv_get_link_ksettings()
4373 cmd->base.autoneg = np->autoneg; in nv_get_link_ksettings()
4376 if (np->autoneg) { in nv_get_link_ksettings()
4378 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_get_link_ksettings()
4387 if (np->gigabit == PHY_GIGABIT) { in nv_get_link_ksettings()
4388 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_get_link_ksettings()
4397 if (np->gigabit == PHY_GIGABIT) in nv_get_link_ksettings()
4400 cmd->base.phy_address = np->phyaddr; in nv_get_link_ksettings()
4402 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, in nv_get_link_ksettings()
4404 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, in nv_get_link_ksettings()
4408 spin_unlock_irq(&np->lock); in nv_get_link_ksettings()
4416 u32 speed = cmd->base.speed; in nv_set_link_ksettings()
4420 cmd->link_modes.advertising); in nv_set_link_ksettings()
4422 if (cmd->base.port != PORT_MII) in nv_set_link_ksettings()
4423 return -EINVAL; in nv_set_link_ksettings()
4424 if (cmd->base.phy_address != np->phyaddr) { in nv_set_link_ksettings()
4427 return -EINVAL; in nv_set_link_ksettings()
4429 if (cmd->base.autoneg == AUTONEG_ENABLE) { in nv_set_link_ksettings()
4434 if (np->gigabit == PHY_GIGABIT) in nv_set_link_ksettings()
4438 return -EINVAL; in nv_set_link_ksettings()
4440 } else if (cmd->base.autoneg == AUTONEG_DISABLE) { in nv_set_link_ksettings()
4442 * forbidden - no one should need that. */ in nv_set_link_ksettings()
4445 return -EINVAL; in nv_set_link_ksettings()
4446 if (cmd->base.duplex != DUPLEX_HALF && in nv_set_link_ksettings()
4447 cmd->base.duplex != DUPLEX_FULL) in nv_set_link_ksettings()
4448 return -EINVAL; in nv_set_link_ksettings()
4450 return -EINVAL; in nv_set_link_ksettings()
4461 spin_lock_irqsave(&np->lock, flags); in nv_set_link_ksettings()
4472 spin_unlock_irqrestore(&np->lock, flags); in nv_set_link_ksettings()
4477 if (cmd->base.autoneg == AUTONEG_ENABLE) { in nv_set_link_ksettings()
4480 np->autoneg = 1; in nv_set_link_ksettings()
4483 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4493 …if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx p… in nv_set_link_ksettings()
4495 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) in nv_set_link_ksettings()
4497 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4499 if (np->gigabit == PHY_GIGABIT) { in nv_set_link_ksettings()
4500 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4504 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4509 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4510 if (np->phy_model == PHY_MODEL_MARVELL_E3016) { in nv_set_link_ksettings()
4516 return -EINVAL; in nv_set_link_ksettings()
4520 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4525 np->autoneg = 0; in nv_set_link_ksettings()
4527 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4529 if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_HALF) in nv_set_link_ksettings()
4531 if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_FULL) in nv_set_link_ksettings()
4533 if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_HALF) in nv_set_link_ksettings()
4535 if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_FULL) in nv_set_link_ksettings()
4537 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); in nv_set_link_ksettings()
4538 …if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx p… in nv_set_link_ksettings()
4540 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; in nv_set_link_ksettings()
4542 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) { in nv_set_link_ksettings()
4544 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; in nv_set_link_ksettings()
4546 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4547 np->fixed_mode = adv; in nv_set_link_ksettings()
4549 if (np->gigabit == PHY_GIGABIT) { in nv_set_link_ksettings()
4550 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4552 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4555 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4557 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL)) in nv_set_link_ksettings()
4559 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) in nv_set_link_ksettings()
4561 if (np->phy_oui == PHY_OUI_MARVELL) { in nv_set_link_ksettings()
4565 return -EINVAL; in nv_set_link_ksettings()
4568 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4590 return np->register_size; in nv_get_regs_len()
4600 regs->version = FORCEDETH_REGS_VER; in nv_get_regs()
4601 spin_lock_irq(&np->lock); in nv_get_regs()
4602 for (i = 0; i < np->register_size/sizeof(u32); i++) in nv_get_regs()
4604 spin_unlock_irq(&np->lock); in nv_get_regs()
4612 if (np->autoneg) { in nv_nway_reset()
4620 spin_lock(&np->lock); in nv_nway_reset()
4623 spin_unlock(&np->lock); in nv_nway_reset()
4629 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_nway_reset()
4630 if (np->phy_model == PHY_MODEL_MARVELL_E3016) { in nv_nway_reset()
4635 return -EINVAL; in nv_nway_reset()
4639 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_nway_reset()
4648 ret = -EINVAL; in nv_nway_reset()
4661 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; in nv_get_ringparam()
4662 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; in nv_get_ringparam()
4664 ring->rx_pending = np->rx_ring_size; in nv_get_ringparam()
4665 ring->tx_pending = np->tx_ring_size; in nv_get_ringparam()
4678 if (ring->rx_pending < RX_RING_MIN || in nv_set_ringparam()
4679 ring->tx_pending < TX_RING_MIN || in nv_set_ringparam()
4680 ring->rx_mini_pending != 0 || in nv_set_ringparam()
4681 ring->rx_jumbo_pending != 0 || in nv_set_ringparam()
4682 (np->desc_ver == DESC_VER_1 && in nv_set_ringparam()
4683 (ring->rx_pending > RING_MAX_DESC_VER_1 || in nv_set_ringparam()
4684 ring->tx_pending > RING_MAX_DESC_VER_1)) || in nv_set_ringparam()
4685 (np->desc_ver != DESC_VER_1 && in nv_set_ringparam()
4686 (ring->rx_pending > RING_MAX_DESC_VER_2_3 || in nv_set_ringparam()
4687 ring->tx_pending > RING_MAX_DESC_VER_2_3))) { in nv_set_ringparam()
4688 return -EINVAL; in nv_set_ringparam()
4693 rxtx_ring = dma_alloc_coherent(&np->pci_dev->dev, in nv_set_ringparam()
4695 (ring->rx_pending + in nv_set_ringparam()
4696 ring->tx_pending), in nv_set_ringparam()
4699 rxtx_ring = dma_alloc_coherent(&np->pci_dev->dev, in nv_set_ringparam()
4701 (ring->rx_pending + in nv_set_ringparam()
4702 ring->tx_pending), in nv_set_ringparam()
4705 rx_skbuff = kmalloc_array(ring->rx_pending, sizeof(struct nv_skb_map), in nv_set_ringparam()
4707 tx_skbuff = kmalloc_array(ring->tx_pending, sizeof(struct nv_skb_map), in nv_set_ringparam()
4713 dma_free_coherent(&np->pci_dev->dev, in nv_set_ringparam()
4715 (ring->rx_pending + in nv_set_ringparam()
4716 ring->tx_pending), in nv_set_ringparam()
4720 dma_free_coherent(&np->pci_dev->dev, in nv_set_ringparam()
4722 (ring->rx_pending + in nv_set_ringparam()
4723 ring->tx_pending), in nv_set_ringparam()
4737 spin_lock(&np->lock); in nv_set_ringparam()
4748 np->rx_ring_size = ring->rx_pending; in nv_set_ringparam()
4749 np->tx_ring_size = ring->tx_pending; in nv_set_ringparam()
4752 np->rx_ring.orig = (struct ring_desc *)rxtx_ring; in nv_set_ringparam()
4753 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; in nv_set_ringparam()
4755 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring; in nv_set_ringparam()
4756 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; in nv_set_ringparam()
4758 np->rx_skb = (struct nv_skb_map *)rx_skbuff; in nv_set_ringparam()
4759 np->tx_skb = (struct nv_skb_map *)tx_skbuff; in nv_set_ringparam()
4760 np->ring_addr = ring_addr; in nv_set_ringparam()
4762 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); in nv_set_ringparam()
4763 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); in nv_set_ringparam()
4769 if (!np->in_shutdown) in nv_set_ringparam()
4770 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_set_ringparam()
4774 writel(np->rx_buf_sz, base + NvRegOffloadConfig); in nv_set_ringparam()
4776 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH… in nv_set_ringparam()
4779 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_set_ringparam()
4784 spin_unlock(&np->lock); in nv_set_ringparam()
4792 return -ENOMEM; in nv_set_ringparam()
4799 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; in nv_get_pauseparam()
4800 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; in nv_get_pauseparam()
4801 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0; in nv_get_pauseparam()
4809 if ((!np->autoneg && np->duplex == 0) || in nv_set_pauseparam()
4810 (np->autoneg && !pause->autoneg && np->duplex == 0)) { in nv_set_pauseparam()
4812 return -EINVAL; in nv_set_pauseparam()
4814 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { in nv_set_pauseparam()
4816 return -EINVAL; in nv_set_pauseparam()
4824 spin_lock(&np->lock); in nv_set_pauseparam()
4827 spin_unlock(&np->lock); in nv_set_pauseparam()
4832 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ); in nv_set_pauseparam()
4833 if (pause->rx_pause) in nv_set_pauseparam()
4834 np->pause_flags |= NV_PAUSEFRAME_RX_REQ; in nv_set_pauseparam()
4835 if (pause->tx_pause) in nv_set_pauseparam()
4836 np->pause_flags |= NV_PAUSEFRAME_TX_REQ; in nv_set_pauseparam()
4838 if (np->autoneg && pause->autoneg) { in nv_set_pauseparam()
4839 np->pause_flags |= NV_PAUSEFRAME_AUTONEG; in nv_set_pauseparam()
4841 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_pauseparam()
4843 …if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pa… in nv_set_pauseparam()
4845 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) in nv_set_pauseparam()
4847 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_pauseparam()
4851 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_pauseparam()
4853 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_pauseparam()
4855 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); in nv_set_pauseparam()
4856 if (pause->rx_pause) in nv_set_pauseparam()
4857 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; in nv_set_pauseparam()
4858 if (pause->tx_pause) in nv_set_pauseparam()
4859 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; in nv_set_pauseparam()
4864 nv_update_pause(dev, np->pause_flags); in nv_set_pauseparam()
4881 spin_lock_irqsave(&np->lock, flags); in nv_set_loopback()
4882 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_loopback()
4885 spin_unlock_irqrestore(&np->lock, flags); in nv_set_loopback()
4892 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol); in nv_set_loopback()
4895 spin_unlock_irqrestore(&np->lock, flags); in nv_set_loopback()
4899 /* Force 1000 Mbps full-duplex */ in nv_set_loopback()
4905 spin_unlock_irqrestore(&np->lock, flags); in nv_set_loopback()
4911 spin_unlock_irqrestore(&np->lock, flags); in nv_set_loopback()
4917 spin_unlock_irqrestore(&np->lock, flags); in nv_set_loopback()
4922 spin_lock_irqsave(&np->lock, flags); in nv_set_loopback()
4924 spin_unlock_irqrestore(&np->lock, flags); in nv_set_loopback()
4943 spin_lock_irq(&np->lock); in nv_vlan_mode()
4946 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP; in nv_vlan_mode()
4948 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; in nv_vlan_mode()
4951 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS; in nv_vlan_mode()
4953 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; in nv_vlan_mode()
4955 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_vlan_mode()
4957 spin_unlock_irq(&np->lock); in nv_vlan_mode()
4964 netdev_features_t changed = dev->features ^ features; in nv_set_features()
4974 spin_lock_irq(&np->lock); in nv_set_features()
4977 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; in nv_set_features()
4979 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; in nv_set_features()
4982 writel(np->txrxctl_bits, base + NvRegTxRxControl); in nv_set_features()
4984 spin_unlock_irq(&np->lock); in nv_set_features()
4999 if (np->driver_data & DEV_HAS_TEST_EXTENDED) in nv_get_sset_count()
5004 if (np->driver_data & DEV_HAS_STATISTICS_V3) in nv_get_sset_count()
5006 else if (np->driver_data & DEV_HAS_STATISTICS_V2) in nv_get_sset_count()
5008 else if (np->driver_data & DEV_HAS_STATISTICS_V1) in nv_get_sset_count()
5013 return -EOPNOTSUPP; in nv_get_sset_count()
5019 __acquires(&netdev_priv(dev)->hwstats_lock) in nv_get_ethtool_stats()
5020 __releases(&netdev_priv(dev)->hwstats_lock) in nv_get_ethtool_stats()
5024 spin_lock_bh(&np->hwstats_lock); in nv_get_ethtool_stats()
5026 memcpy(buffer, &np->estats, in nv_get_ethtool_stats()
5028 spin_unlock_bh(&np->hwstats_lock); in nv_get_ethtool_stats()
5036 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
5037 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
5089 np->intr_test = 0; in nv_interrupt_test()
5092 save_msi_flags = np->msi_flags; in nv_interrupt_test()
5093 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK; in nv_interrupt_test()
5094 np->msi_flags |= 0x001; /* setup 1 vector */ in nv_interrupt_test()
5107 spin_lock_irq(&np->lock); in nv_interrupt_test()
5110 testcnt = np->intr_test; in nv_interrupt_test()
5115 if (!(np->msi_flags & NV_MSI_X_ENABLED)) in nv_interrupt_test()
5120 spin_unlock_irq(&np->lock); in nv_interrupt_test()
5124 np->msi_flags = save_msi_flags; in nv_interrupt_test()
5143 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); in nv_loopback_test()
5168 writel(np->rx_buf_sz, base + NvRegOffloadConfig); in nv_loopback_test()
5170 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH… in nv_loopback_test()
5184 test_dma_addr = dma_map_single(&np->pci_dev->dev, tx_skb->data, in nv_loopback_test()
5187 if (unlikely(dma_mapping_error(&np->pci_dev->dev, in nv_loopback_test()
5197 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr); in nv_loopback_test()
5198 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); in nv_loopback_test()
5200 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr)); in nv_loopback_test()
5201 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr)); in nv_loopback_test()
5202 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); in nv_loopback_test()
5204 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_loopback_test()
5211 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen); in nv_loopback_test()
5212 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); in nv_loopback_test()
5215 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen); in nv_loopback_test()
5216 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); in nv_loopback_test()
5221 } else if (np->desc_ver == DESC_VER_1) { in nv_loopback_test()
5233 rx_skb = np->rx_skb[0].skb; in nv_loopback_test()
5235 if (rx_skb->data[i] != (u8)(i & 0xff)) { in nv_loopback_test()
5243 dma_unmap_single(&np->pci_dev->dev, test_dma_addr, in nv_loopback_test()
5244 (skb_end_pointer(tx_skb) - tx_skb->data), in nv_loopback_test()
5273 test->flags |= ETH_TEST_FL_FAILED; in nv_self_test()
5277 if (test->flags & ETH_TEST_FL_OFFLINE) { in nv_self_test()
5283 spin_lock_irq(&np->lock); in nv_self_test()
5284 nv_disable_hw_interrupts(dev, np->irqmask); in nv_self_test()
5285 if (!(np->msi_flags & NV_MSI_X_ENABLED)) in nv_self_test()
5294 spin_unlock_irq(&np->lock); in nv_self_test()
5300 test->flags |= ETH_TEST_FL_FAILED; in nv_self_test()
5306 test->flags |= ETH_TEST_FL_FAILED; in nv_self_test()
5315 test->flags |= ETH_TEST_FL_FAILED; in nv_self_test()
5323 if (!np->in_shutdown) in nv_self_test()
5324 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_self_test()
5327 writel(np->rx_buf_sz, base + NvRegOffloadConfig); in nv_self_test()
5329 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH… in nv_self_test()
5332 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); in nv_self_test()
5338 nv_enable_hw_interrupts(dev, np->irqmask); in nv_self_test()
5403 np->mgmt_sema = 1; in nv_mgmt_acquire_sema()
5418 if (np->driver_data & DEV_HAS_MGMT_UNIT) { in nv_mgmt_release_sema()
5419 if (np->mgmt_sema) { in nv_mgmt_release_sema()
5452 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION; in nv_mgmt_get_version()
5466 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_open()
5467 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); in nv_open()
5471 if (np->driver_data & DEV_HAS_POWER_CNTRL) in nv_open()
5484 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) in nv_open()
5496 np->in_shutdown = 0; in nv_open()
5500 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH… in nv_open()
5503 writel(np->linkspeed, base + NvRegLinkSpeed); in nv_open()
5504 if (np->desc_ver == DESC_VER_1) in nv_open()
5508 writel(np->txrxctl_bits, base + NvRegTxRxControl); in nv_open()
5509 writel(np->vlanctl_bits, base + NvRegVlanControl); in nv_open()
5511 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); in nv_open()
5525 writel(np->rx_buf_sz, base + NvRegOffloadConfig); in nv_open()
5531 if (np->desc_ver == DESC_VER_1) { in nv_open()
5534 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) { in nv_open()
5544 if (poll_interval == -1) { in nv_open()
5552 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, in nv_open()
5556 if (np->wolenabled) in nv_open()
5567 nv_disable_hw_interrupts(dev, np->irqmask); in nv_open()
5577 nv_enable_hw_interrupts(dev, np->irqmask); in nv_open()
5579 spin_lock_irq(&np->lock); in nv_open()
5593 np->linkspeed = 0; in nv_open()
5606 mod_timer(&np->oom_kick, jiffies + OOM_REFILL); in nv_open()
5609 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) in nv_open()
5610 mod_timer(&np->stats_poll, in nv_open()
5613 spin_unlock_irq(&np->lock); in nv_open()
5618 if (dev->features & NETIF_F_LOOPBACK) in nv_open()
5619 nv_set_loopback(dev, dev->features); in nv_open()
5632 spin_lock_irq(&np->lock); in nv_close()
5633 np->in_shutdown = 1; in nv_close()
5634 spin_unlock_irq(&np->lock); in nv_close()
5636 synchronize_irq(np->pci_dev->irq); in nv_close()
5638 del_timer_sync(&np->oom_kick); in nv_close()
5639 del_timer_sync(&np->nic_poll); in nv_close()
5640 del_timer_sync(&np->stats_poll); in nv_close()
5643 spin_lock_irq(&np->lock); in nv_close()
5650 nv_disable_hw_interrupts(dev, np->irqmask); in nv_close()
5653 spin_unlock_irq(&np->lock); in nv_close()
5659 if (np->wolenabled || !phy_power_down) { in nv_close()
5665 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_close()
5666 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); in nv_close()
5727 err = -ENOMEM; in nv_probe()
5732 np->dev = dev; in nv_probe()
5733 np->pci_dev = pci_dev; in nv_probe()
5734 spin_lock_init(&np->lock); in nv_probe()
5735 spin_lock_init(&np->hwstats_lock); in nv_probe()
5736 SET_NETDEV_DEV(dev, &pci_dev->dev); in nv_probe()
5737 u64_stats_init(&np->swstats_rx_syncp); in nv_probe()
5738 u64_stats_init(&np->swstats_tx_syncp); in nv_probe()
5739 np->txrx_stats = alloc_percpu(struct nv_txrx_stats); in nv_probe()
5740 if (!np->txrx_stats) { in nv_probe()
5741 pr_err("np->txrx_stats, alloc memory error.\n"); in nv_probe()
5742 err = -ENOMEM; in nv_probe()
5746 timer_setup(&np->oom_kick, nv_do_rx_refill, 0); in nv_probe()
5747 timer_setup(&np->nic_poll, nv_do_nic_poll, 0); in nv_probe()
5748 timer_setup(&np->stats_poll, nv_do_stats_poll, TIMER_DEFERRABLE); in nv_probe()
5760 …if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HA… in nv_probe()
5761 np->register_size = NV_PCI_REGSZ_VER3; in nv_probe()
5762 else if (id->driver_data & DEV_HAS_STATISTICS_V1) in nv_probe()
5763 np->register_size = NV_PCI_REGSZ_VER2; in nv_probe()
5765 np->register_size = NV_PCI_REGSZ_VER1; in nv_probe()
5767 err = -EINVAL; in nv_probe()
5771 pci_resource_len(pci_dev, i) >= np->register_size) { in nv_probe()
5777 dev_info(&pci_dev->dev, "Couldn't find register window\n"); in nv_probe()
5782 np->driver_data = id->driver_data; in nv_probe()
5784 np->device_id = id->device; in nv_probe()
5787 if (id->driver_data & DEV_HAS_HIGH_DMA) { in nv_probe()
5788 /* packet format 3: supports 40-bit addressing */ in nv_probe()
5789 np->desc_ver = DESC_VER_3; in nv_probe()
5790 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; in nv_probe()
5792 if (dma_set_mask_and_coherent(&pci_dev->dev, DMA_BIT_MASK(39))) in nv_probe()
5793 dev_info(&pci_dev->dev, in nv_probe()
5794 "64-bit DMA failed, using 32-bit addressing\n"); in nv_probe()
5796 dev->features |= NETIF_F_HIGHDMA; in nv_probe()
5798 } else if (id->driver_data & DEV_HAS_LARGEDESC) { in nv_probe()
5800 np->desc_ver = DESC_VER_2; in nv_probe()
5801 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; in nv_probe()
5804 np->desc_ver = DESC_VER_1; in nv_probe()
5805 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; in nv_probe()
5808 np->pkt_limit = NV_PKTLIMIT_1; in nv_probe()
5809 if (id->driver_data & DEV_HAS_LARGEDESC) in nv_probe()
5810 np->pkt_limit = NV_PKTLIMIT_2; in nv_probe()
5812 if (id->driver_data & DEV_HAS_CHECKSUM) { in nv_probe()
5813 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; in nv_probe()
5814 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | in nv_probe()
5818 np->vlanctl_bits = 0; in nv_probe()
5819 if (id->driver_data & DEV_HAS_VLAN) { in nv_probe()
5820 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; in nv_probe()
5821 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | in nv_probe()
5825 dev->features |= dev->hw_features; in nv_probe()
5828 dev->hw_features |= NETIF_F_LOOPBACK; in nv_probe()
5830 /* MTU range: 64 - 1500 or 9100 */ in nv_probe()
5831 dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN; in nv_probe()
5832 dev->max_mtu = np->pkt_limit; in nv_probe()
5834 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG; in nv_probe()
5835 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) || in nv_probe()
5836 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) || in nv_probe()
5837 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) { in nv_probe()
5838 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ; in nv_probe()
5841 err = -ENOMEM; in nv_probe()
5842 np->base = ioremap(addr, np->register_size); in nv_probe()
5843 if (!np->base) in nv_probe()
5846 np->rx_ring_size = RX_RING_DEFAULT; in nv_probe()
5847 np->tx_ring_size = TX_RING_DEFAULT; in nv_probe()
5850 np->rx_ring.orig = dma_alloc_coherent(&pci_dev->dev, in nv_probe()
5852 (np->rx_ring_size + in nv_probe()
5853 np->tx_ring_size), in nv_probe()
5854 &np->ring_addr, in nv_probe()
5856 if (!np->rx_ring.orig) in nv_probe()
5858 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; in nv_probe()
5860 np->rx_ring.ex = dma_alloc_coherent(&pci_dev->dev, in nv_probe()
5862 (np->rx_ring_size + in nv_probe()
5863 np->tx_ring_size), in nv_probe()
5864 &np->ring_addr, GFP_KERNEL); in nv_probe()
5865 if (!np->rx_ring.ex) in nv_probe()
5867 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; in nv_probe()
5869 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); in nv_probe()
5870 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); in nv_probe()
5871 if (!np->rx_skb || !np->tx_skb) in nv_probe()
5875 dev->netdev_ops = &nv_netdev_ops; in nv_probe()
5877 dev->netdev_ops = &nv_netdev_ops_optimized; in nv_probe()
5879 netif_napi_add(dev, &np->napi, nv_napi_poll); in nv_probe()
5880 dev->ethtool_ops = &ops; in nv_probe()
5881 dev->watchdog_timeo = NV_WATCHDOG_TIMEO; in nv_probe()
5887 np->orig_mac[0] = readl(base + NvRegMacAddrA); in nv_probe()
5888 np->orig_mac[1] = readl(base + NvRegMacAddrB); in nv_probe()
5892 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) { in nv_probe()
5894 mac[0] = (np->orig_mac[0] >> 0) & 0xff; in nv_probe()
5895 mac[1] = (np->orig_mac[0] >> 8) & 0xff; in nv_probe()
5896 mac[2] = (np->orig_mac[0] >> 16) & 0xff; in nv_probe()
5897 mac[3] = (np->orig_mac[0] >> 24) & 0xff; in nv_probe()
5898 mac[4] = (np->orig_mac[1] >> 0) & 0xff; in nv_probe()
5899 mac[5] = (np->orig_mac[1] >> 8) & 0xff; in nv_probe()
5902 mac[0] = (np->orig_mac[0] >> 0) & 0xff; in nv_probe()
5903 mac[1] = (np->orig_mac[0] >> 8) & 0xff; in nv_probe()
5904 mac[2] = (np->orig_mac[0] >> 16) & 0xff; in nv_probe()
5905 mac[3] = (np->orig_mac[0] >> 24) & 0xff; in nv_probe()
5906 mac[4] = (np->orig_mac[1] >> 0) & 0xff; in nv_probe()
5907 mac[5] = (np->orig_mac[1] >> 8) & 0xff; in nv_probe()
5913 np->orig_mac[0] = (mac[5] << 0) + (mac[4] << 8) + in nv_probe()
5915 np->orig_mac[1] = (mac[1] << 0) + (mac[0] << 8); in nv_probe()
5918 mac[0] = (np->orig_mac[1] >> 8) & 0xff; in nv_probe()
5919 mac[1] = (np->orig_mac[1] >> 0) & 0xff; in nv_probe()
5920 mac[2] = (np->orig_mac[0] >> 24) & 0xff; in nv_probe()
5921 mac[3] = (np->orig_mac[0] >> 16) & 0xff; in nv_probe()
5922 mac[4] = (np->orig_mac[0] >> 8) & 0xff; in nv_probe()
5923 mac[5] = (np->orig_mac[0] >> 0) & 0xff; in nv_probe()
5925 dev_dbg(&pci_dev->dev, in nv_probe()
5937 dev_err(&pci_dev->dev, in nv_probe()
5938 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n", in nv_probe()
5941 dev_err(&pci_dev->dev, in nv_probe()
5942 "Using random MAC address: %pM\n", dev->dev_addr); in nv_probe()
5950 np->wolenabled = 0; in nv_probe()
5951 device_set_wakeup_enable(&pci_dev->dev, false); in nv_probe()
5953 if (id->driver_data & DEV_HAS_POWER_CNTRL) { in nv_probe()
5958 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) && in nv_probe()
5959 pci_dev->revision >= 0xA3) in nv_probe()
5964 if (np->desc_ver == DESC_VER_1) in nv_probe()
5965 np->tx_flags = NV_TX_VALID; in nv_probe()
5967 np->tx_flags = NV_TX2_VALID; in nv_probe()
5969 np->msi_flags = 0; in nv_probe()
5970 if ((id->driver_data & DEV_HAS_MSI) && msi) in nv_probe()
5971 np->msi_flags |= NV_MSI_CAPABLE; in nv_probe()
5973 if ((id->driver_data & DEV_HAS_MSI_X) && msix) { in nv_probe()
5978 np->msi_flags |= NV_MSI_X_CAPABLE; in nv_probe()
5983 np->irqmask = NVREG_IRQMASK_CPU; in nv_probe()
5984 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ in nv_probe()
5985 np->msi_flags |= 0x0001; in nv_probe()
5987 !(id->driver_data & DEV_NEED_TIMERIRQ)) { in nv_probe()
5989 np->irqmask = NVREG_IRQMASK_THROUGHPUT; in nv_probe()
5991 np->msi_flags &= ~NV_MSI_X_CAPABLE; in nv_probe()
5994 np->irqmask = NVREG_IRQMASK_THROUGHPUT; in nv_probe()
5995 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ in nv_probe()
5996 np->msi_flags |= 0x0003; in nv_probe()
5999 if (id->driver_data & DEV_NEED_TIMERIRQ) in nv_probe()
6000 np->irqmask |= NVREG_IRQ_TIMER; in nv_probe()
6001 if (id->driver_data & DEV_NEED_LINKTIMER) { in nv_probe()
6002 np->need_linktimer = 1; in nv_probe()
6003 np->link_timeout = jiffies + LINK_TIMEOUT; in nv_probe()
6005 np->need_linktimer = 0; in nv_probe()
6009 if (id->driver_data & DEV_NEED_TX_LIMIT) { in nv_probe()
6010 np->tx_limit = 1; in nv_probe()
6011 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) && in nv_probe()
6012 pci_dev->revision >= 0xA2) in nv_probe()
6013 np->tx_limit = 0; in nv_probe()
6026 if (id->driver_data & DEV_HAS_MGMT_UNIT) { in nv_probe()
6032 np->mac_in_use = 1; in nv_probe()
6033 if (np->mgmt_version > 0) in nv_probe()
6034 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE; in nv_probe()
6036 if (np->mac_in_use && in nv_probe()
6049 int id1, id2; in nv_probe() local
6052 spin_lock_irq(&np->lock); in nv_probe()
6054 spin_unlock_irq(&np->lock); in nv_probe()
6057 spin_lock_irq(&np->lock); in nv_probe()
6058 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); in nv_probe()
6059 spin_unlock_irq(&np->lock); in nv_probe()
6060 if (id2 < 0 || id2 == 0xffff) in nv_probe()
6063 np->phy_model = id2 & PHYID2_MODEL_MASK; in nv_probe()
6065 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; in nv_probe()
6066 np->phyaddr = phyaddr; in nv_probe()
6067 np->phy_oui = id1 | id2; in nv_probe()
6070 if (np->phy_oui == PHY_OUI_REALTEK2) in nv_probe()
6071 np->phy_oui = PHY_OUI_REALTEK; in nv_probe()
6072 /* Setup phy revision for Realtek */ in nv_probe()
6073 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211) in nv_probe()
6074 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; in nv_probe()
6079 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n"); in nv_probe()
6088 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_probe()
6090 np->gigabit = PHY_GIGABIT; in nv_probe()
6094 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; in nv_probe()
6095 np->duplex = 0; in nv_probe()
6096 np->autoneg = 1; in nv_probe()
6100 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err); in nv_probe()
6114 if (id->driver_data & DEV_HAS_VLAN) in nv_probe()
6115 nv_vlan_mode(dev, dev->features); in nv_probe()
6117 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n", in nv_probe()
6118 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr); in nv_probe()
6120 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n", in nv_probe()
6121 dev->features & NETIF_F_HIGHDMA ? "highdma " : "", in nv_probe()
6122 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ? in nv_probe()
6124 dev->features & (NETIF_F_HW_VLAN_CTAG_RX | in nv_probe()
6127 dev->features & (NETIF_F_LOOPBACK) ? in nv_probe()
6129 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "", in nv_probe()
6130 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "", in nv_probe()
6131 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "", in nv_probe()
6132 np->gigabit == PHY_GIGABIT ? "gbit " : "", in nv_probe()
6133 np->need_linktimer ? "lnktim " : "", in nv_probe()
6134 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "", in nv_probe()
6135 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "", in nv_probe()
6136 np->desc_ver); in nv_probe()
6153 free_percpu(np->txrx_stats); in nv_probe()
6165 if (np->phy_oui == PHY_OUI_REALTEK && in nv_restore_phy()
6166 np->phy_model == PHY_MODEL_REALTEK_8201 && in nv_restore_phy()
6168 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); in nv_restore_phy()
6169 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); in nv_restore_phy()
6172 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); in nv_restore_phy()
6173 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); in nv_restore_phy()
6176 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_restore_phy()
6178 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); in nv_restore_phy()
6188 /* special op: write back the misordered MAC address - otherwise in nv_restore_mac_addr()
6191 writel(np->orig_mac[0], base + NvRegMacAddrA); in nv_restore_mac_addr()
6192 writel(np->orig_mac[1], base + NvRegMacAddrB); in nv_restore_mac_addr()
6202 free_percpu(np->txrx_stats); in nv_remove()
6235 /* save non-pci configuration space */ in nv_suspend()
6236 for (i = 0; i <= np->register_size/sizeof(u32); i++) in nv_suspend()
6237 np->saved_config_space[i] = readl(base + i*sizeof(u32)); in nv_suspend()
6250 /* restore non-pci configuration space */ in nv_resume()
6251 for (i = 0; i <= np->register_size/sizeof(u32); i++) in nv_resume()
6252 writel(np->saved_config_space[i], base+i*sizeof(u32)); in nv_resume()
6254 if (np->driver_data & DEV_NEED_MSI_FIX) in nv_resume()
6298 pci_wake_from_d3(pdev, np->wolenabled); in nv_shutdown()