30 #define XAXIDMA_RX_CR_OFFSET	0x30 /* Channel control */  macro
344 	cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);  in nixge_hw_dma_bd_init()
354 	nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);  in nixge_hw_dma_bd_init()
373 	cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);  in nixge_hw_dma_bd_init()
374 	nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,  in nixge_hw_dma_bd_init()
417 	__nixge_device_reset(priv, XAXIDMA_RX_CR_OFFSET);  in nixge_device_reset()
689 			cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);  in nixge_poll()
691 			nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);  in nixge_poll()
729 		cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);  in nixge_tx_irq()
733 		nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);  in nixge_tx_irq()
754 		cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);  in nixge_rx_irq()
756 		nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);  in nixge_rx_irq()
777 		cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);  in nixge_rx_irq()
781 		nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);  in nixge_rx_irq()
798 	__nixge_device_reset(lp, XAXIDMA_RX_CR_OFFSET);  in nixge_dma_err_handler()
821 	cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET);  in nixge_dma_err_handler()
831 	nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET, cr);  in nixge_dma_err_handler()
850 	cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET);  in nixge_dma_err_handler()
851 	nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET,  in nixge_dma_err_handler()
923 	cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);  in nixge_stop()
924 	nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,  in nixge_stop()
1006 	regval = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);  in nixge_ethtools_get_coalesce()