25 #define XAXIDMA_TX_CR_OFFSET	0x00 /* Channel control */
26 #define XAXIDMA_TX_SR_OFFSET	0x04 /* Status */
27 #define XAXIDMA_TX_CDESC_OFFSET	0x08 /* Current descriptor pointer */
28 #define XAXIDMA_TX_TDESC_OFFSET	0x10 /* Tail descriptor pointer */
30 #define XAXIDMA_RX_CR_OFFSET	0x30 /* Channel control */
31 #define XAXIDMA_RX_SR_OFFSET	0x34 /* Status */
32 #define XAXIDMA_RX_CDESC_OFFSET	0x38 /* Current descriptor pointer */
33 #define XAXIDMA_RX_TDESC_OFFSET	0x40 /* Tail descriptor pointer */
35 #define XAXIDMA_CR_RUNSTOP_MASK	0x1 /* Start/stop DMA channel */
36 #define XAXIDMA_CR_RESET_MASK	0x4 /* Reset DMA engine */
38 #define XAXIDMA_BD_CTRL_LENGTH_MASK	0x007FFFFF /* Requested len */
39 #define XAXIDMA_BD_CTRL_TXSOF_MASK	0x08000000 /* First tx packet */
40 #define XAXIDMA_BD_CTRL_TXEOF_MASK	0x04000000 /* Last tx packet */
41 #define XAXIDMA_BD_CTRL_ALL_MASK	0x0C000000 /* All control bits */
43 #define XAXIDMA_DELAY_MASK		0xFF000000 /* Delay timeout counter */
44 #define XAXIDMA_COALESCE_MASK		0x00FF0000 /* Coalesce counter */
49 #define XAXIDMA_IRQ_IOC_MASK		0x00001000 /* Completion intr */
50 #define XAXIDMA_IRQ_DELAY_MASK		0x00002000 /* Delay interrupt */
51 #define XAXIDMA_IRQ_ERROR_MASK		0x00004000 /* Error interrupt */
52 #define XAXIDMA_IRQ_ALL_MASK		0x00007000 /* All interrupts */
60 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK	0x007FFFFF /* Actual len */
61 #define XAXIDMA_BD_STS_COMPLETE_MASK	0x80000000 /* Completed */
62 #define XAXIDMA_BD_STS_DEC_ERR_MASK	0x40000000 /* Decode error */
63 #define XAXIDMA_BD_STS_SLV_ERR_MASK	0x20000000 /* Slave error */
64 #define XAXIDMA_BD_STS_INT_ERR_MASK	0x10000000 /* Internal err */
65 #define XAXIDMA_BD_STS_ALL_ERR_MASK	0x70000000 /* All errors */
66 #define XAXIDMA_BD_STS_RXSOF_MASK	0x08000000 /* First rx pkt */
67 #define XAXIDMA_BD_STS_RXEOF_MASK	0x04000000 /* Last rx pkt */
68 #define XAXIDMA_BD_STS_ALL_MASK		0xFC000000 /* All status bits */
70 #define NIXGE_REG_CTRL_OFFSET	0x4000
71 #define NIXGE_REG_INFO		0x00
72 #define NIXGE_REG_MAC_CTL	0x04
73 #define NIXGE_REG_PHY_CTL	0x08
74 #define NIXGE_REG_LED_CTL	0x0c
75 #define NIXGE_REG_MDIO_DATA	0x10
76 #define NIXGE_REG_MDIO_ADDR	0x14
77 #define NIXGE_REG_MDIO_OP	0x18
78 #define NIXGE_REG_MDIO_CTRL	0x1c
80 #define NIXGE_ID_LED_CTL_EN	BIT(0)
84 #define NIXGE_MDIO_CLAUSE22	0
85 #define NIXGE_MDIO_OP(n)     (((n) & 0x3) << 10)
86 #define NIXGE_MDIO_OP_ADDRESS	0
87 #define NIXGE_MDIO_C45_WRITE	BIT(0)
88 #define NIXGE_MDIO_C45_READ	(BIT(1) | BIT(0))
89 #define NIXGE_MDIO_C22_WRITE	BIT(0)
91 #define NIXGE_MDIO_ADDR(n)   (((n) & 0x1f) << 5)
92 #define NIXGE_MDIO_MMD(n)    (((n) & 0x1f) << 0)
94 #define NIXGE_REG_MAC_LSB	0x1000
95 #define NIXGE_REG_MAC_MSB	0x1004
137 	} while (0)
252 		for (i = 0; i < RX_BD_NUM; i++) {  in nixge_hw_dma_bd_release()
291 	priv->tx_bd_ci = 0;  in nixge_hw_dma_bd_init()
292 	priv->tx_bd_tail = 0;  in nixge_hw_dma_bd_init()
293 	priv->rx_bd_ci = 0;  in nixge_hw_dma_bd_init()
314 	for (i = 0; i < TX_BD_NUM; i++) {  in nixge_hw_dma_bd_init()
321 	for (i = 0; i < RX_BD_NUM; i++) {  in nixge_hw_dma_bd_init()
388 	return 0;  in nixge_hw_dma_bd_init()
451 		tx_skb->mapping = 0;  in nixge_tx_skb_unmap()
465 	unsigned int status = 0;  in nixge_start_xmit_done()
466 	u32 packets = 0;  in nixge_start_xmit_done()
467 	u32 size = 0;  in nixge_start_xmit_done()
476 		cur_p->status = 0;  in nixge_start_xmit_done()
503 	return 0;  in nixge_check_tx_bd_space()
540 	for (ii = 0; ii < num_frag; ii++) {  in nixge_start_xmit()
547 		cur_phys = skb_frag_dma_map(ndev->dev.parent, frag, 0,  in nixge_start_xmit()
575 	for (; ii > 0; ii--) {  in nixge_start_xmit()
585 		cur_p->status = 0;  in nixge_start_xmit()
600 	dma_addr_t tail_p = 0, cur_phys = 0;  in nixge_recv()
601 	u32 packets = 0;  in nixge_recv()
602 	u32 length = 0;  in nixge_recv()
603 	u32 size = 0;  in nixge_recv()
653 		cur_p->status = 0;  in nixge_recv()
676 	work_done = 0;  in nixge_poll()
720 		netdev_err(ndev, "DMA Tx error 0x%x\n", status);  in nixge_tx_irq()
721 		netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);  in nixge_tx_irq()
768 		netdev_err(ndev, "DMA Rx error 0x%x\n", status);  in nixge_rx_irq()
769 		netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);  in nixge_rx_irq()
800 	for (i = 0; i < TX_BD_NUM; i++) {  in nixge_dma_err_handler()
805 		nixge_hw_dma_bd_set_phys(cur_p, 0);  in nixge_dma_err_handler()
806 		cur_p->cntrl = 0;  in nixge_dma_err_handler()
807 		cur_p->status = 0;  in nixge_dma_err_handler()
808 		nixge_hw_dma_bd_set_offset(cur_p, 0);  in nixge_dma_err_handler()
811 	for (i = 0; i < RX_BD_NUM; i++) {  in nixge_dma_err_handler()
813 		cur_p->status = 0;  in nixge_dma_err_handler()
816 	lp->tx_bd_ci = 0;  in nixge_dma_err_handler()
817 	lp->tx_bd_tail = 0;  in nixge_dma_err_handler()
818 	lp->rx_bd_ci = 0;  in nixge_dma_err_handler()
875 			     &nixge_handle_link_change, 0, priv->phy_mode);  in nixge_open()
887 	ret = request_irq(priv->tx_irq, nixge_tx_irq, 0, ndev->name, ndev);  in nixge_open()
891 	ret = request_irq(priv->rx_irq, nixge_rx_irq, 0, ndev->name, ndev);  in nixge_open()
897 	return 0;  in nixge_open()
937 	return 0;  in nixge_stop()
951 	return 0;  in nixge_change_mtu()
962 			     (ndev->dev_addr[5] << 0));  in __nixge_hw_set_mac_address()
965 			     (ndev->dev_addr[1] | (ndev->dev_addr[0] << 8)));  in __nixge_hw_set_mac_address()
967 	return 0;  in __nixge_hw_set_mac_address()
1004 	u32 regval = 0;  in nixge_ethtools_get_coalesce()
1012 	return 0;  in nixge_ethtools_get_coalesce()
1034 	return 0;  in nixge_ethtools_set_coalesce()
1068 	return 0;  in nixge_ethtools_set_phys_id()
1089 	device = reg & 0x1f;  in nixge_mdio_read_c22()
1116 	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);  in nixge_mdio_read_c45()
1158 	device = reg & 0x1f;  in nixge_mdio_write_c22()
1182 	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);  in nixge_mdio_write_c45()
1273 		priv->dma_regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);  in nixge_of_get_resources()
1288 	return 0;  in nixge_of_get_resources()
1333 	if (priv->tx_irq < 0) {  in nixge_probe()
1340 	if (priv->rx_irq < 0) {  in nixge_probe()
1365 	phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);  in nixge_probe()
1368 		if (err < 0) {  in nixge_probe()
1382 	return 0;  in nixge_probe()