Lines Matching +full:0 +full:xf00
18 #define TX_REG_OFFSET_DESC0 0
23 #define RX_REG_OFFSET_DESC0 0
28 #define TX_DESC0_PKT_LATE_COL 0x1 /* abort, late collision */
29 #define TX_DESC0_RX_PKT_EXS_COL 0x2 /* abort, >16 collisions */
30 #define TX_DESC0_DMA_OWN 0x80000000 /* owned by controller */
31 #define TX_DESC1_BUF_SIZE_MASK 0x7ff
32 #define TX_DESC1_LTS 0x8000000 /* last TX packet */
33 #define TX_DESC1_FTS 0x10000000 /* first TX packet */
34 #define TX_DESC1_FIFO_COMPLETE 0x20000000
35 #define TX_DESC1_INTR_COMPLETE 0x40000000
36 #define TX_DESC1_END 0x80000000
37 #define TX_DESC2_ADDRESS_PHYS 0
40 #define RX_DESC0_FRAME_LEN 0
41 #define RX_DESC0_FRAME_LEN_MASK 0x7FF
42 #define RX_DESC0_MULTICAST 0x10000
43 #define RX_DESC0_BROADCAST 0x20000
44 #define RX_DESC0_ERR 0x40000
45 #define RX_DESC0_CRC_ERR 0x80000
46 #define RX_DESC0_FTL 0x100000
47 #define RX_DESC0_RUNT 0x200000 /* packet less than 64 bytes */
48 #define RX_DESC0_ODD_NB 0x400000 /* receive odd nibbles */
49 #define RX_DESC0_LRS 0x10000000 /* last receive segment */
50 #define RX_DESC0_FRS 0x20000000 /* first receive segment */
51 #define RX_DESC0_DMA_OWN 0x80000000
52 #define RX_DESC1_BUF_SIZE_MASK 0x7FF
53 #define RX_DESC1_END 0x80000000
54 #define RX_DESC2_ADDRESS_PHYS 0
70 #define REG_INTERRUPT_STATUS 0
106 #define REG_PHY_CTRL_OFFSET 0x0
107 #define REG_PHY_STATUS 0x1
108 #define REG_PHY_ID1 0x2
109 #define REG_PHY_ID2 0x3
110 #define REG_PHY_ANA 0x4
111 #define REG_PHY_ANLPAR 0x5
112 #define REG_PHY_ANE 0x6
113 #define REG_PHY_ECTRL1 0x10
114 #define REG_PHY_QPDS 0x11
115 #define REG_PHY_10BOP 0x12
116 #define REG_PHY_ECTRL2 0x13
117 #define REG_PHY_FTMAC100_WRITE 0x8000000
118 #define REG_PHY_FTMAC100_READ 0x4000000
121 #define RPKT_FINISH BIT(0) /* DMA data received */
133 #define RPKT_FINISH_M BIT(0)
145 #define MAC_MADR_MASK 0xffff /* 2 MSB MAC address */
149 #define TXINT_THR_MASK 0x7000
150 #define TXINT_CNT_MASK 0xf00
152 #define RXINT_THR_MASK 0x70
153 #define RXINT_CNT_MASK 0xF
157 #define TXPOLL_CNT_MASK 0xf00
160 #define RXPOLL_CNT_MASK 0xF
161 #define RXPOLL_CNT_SHIFT_BIT 0
165 #define RXFIFO_HTHR_MASK 0x1c0
166 #define RXFIFO_LTHR_MASK 0x38
169 #define INCR4_EN BIT(0) /* AHB bus INCR4 burst command */
187 #define XDMA_EN BIT(0) /* enable transmit DMA chan */
201 #define MCPU_MULTICAST BIT(0)
206 #define REGAD_MASK 0x3e00000
207 #define PHYAD_MASK 0x1f0000
208 #define MIIRDATA_MASK 0xffff
211 #define MIIWDATA_MASK 0xffff
214 #define PAUSE_TIME_MASK 0xffff0000
215 #define FC_HIGH_MASK 0xf000
216 #define FC_LOW_MASK 0xf00
221 #define FC_EN BIT(0) /* flow control mode enable */
224 #define BACKP_LOW_MASK 0xf00
225 #define BACKP_JAM_LEN_MASK 0xf0
227 #define BACKP_ENABLE BIT(0)
230 #define TEST_SEED_MASK 0x3fff
239 #define TX_DMA2_SM_MASK 0x7000
240 #define TX_DMA1_SM_MASK 0xf00
241 #define RX_DMA2_SM_MASK 0x70
242 #define RX_DMA1_SM_MASK 0xF
251 #define TEST_TIME_MASK 0xffc00
252 #define TEST_EXCEL_MASK 0x3e0
255 #define TX_MCOL_MASK 0xffff0000
257 #define TX_SCOL_MASK 0xffff
258 #define TX_SCOL_SHIFT_BIT 0
261 #define RPF_MASK 0xffff0000
263 #define AEP_MASK 0xffff
264 #define AEP_SHIFT_BIT 0
267 #define XM_MASK 0xffff0000
269 #define PG_MASK 0xffff
270 #define PG_SHIFT_BIT 0
273 #define RUNT_CNT_MASK 0xffff0000
275 #define TLCC_MASK 0xffff
276 #define TLCC_SHIFT_BIT 0
279 #define CRCER_CNT_MASK 0xffff0000
281 #define FTL_CNT_MASK 0xffff
282 #define FTL_CNT_SHIFT_BIT 0
285 #define RLC_MASK 0xffff0000
287 #define RCC_MASK 0xffff
288 #define RCC_SHIFT_BIT 0
291 #define AN_COMPLETE 0x20
292 #define LINK_STATUS 0x4