Lines Matching +full:40 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0+
12 /* The IFH bit position of the first VSTAX bit. This is because the
13 * VSTAX bit positions in Data sheet is starting from zero.
21 /* Max width is 5 bytes - 40 bits. In worst case this will
22 * spread over 6 bytes - 48 bits
24 compiletime_assert(width <= 40, \
25 "Unsupported width, must be <= 40"); \
32 /* Calculate the Start IFH byte position of this IFH bit position */ in __ifh_encode_bitfield()
33 u32 byte = (35 - (pos / 8)); in __ifh_encode_bitfield()
34 /* Calculate the Start bit position in the Start IFH byte */ in __ifh_encode_bitfield()
35 u32 bit = (pos % 8); in __ifh_encode_bitfield() local
36 u64 encode = GENMASK_ULL(bit + width - 1, bit) & (value << bit); in __ifh_encode_bitfield()
38 /* The b0-b7 goes into the start IFH byte */ in __ifh_encode_bitfield()
41 /* The b8-b15 goes into the next IFH byte */ in __ifh_encode_bitfield()
43 ifh_hdr[byte - 1] |= (u8)((encode & 0xFF00) >> 8); in __ifh_encode_bitfield()
44 /* The b16-b23 goes into the next IFH byte */ in __ifh_encode_bitfield()
46 ifh_hdr[byte - 2] |= (u8)((encode & 0xFF0000) >> 16); in __ifh_encode_bitfield()
47 /* The b24-b31 goes into the next IFH byte */ in __ifh_encode_bitfield()
49 ifh_hdr[byte - 3] |= (u8)((encode & 0xFF000000) >> 24); in __ifh_encode_bitfield()
50 /* The b32-b39 goes into the next IFH byte */ in __ifh_encode_bitfield()
52 ifh_hdr[byte - 4] |= (u8)((encode & 0xFF00000000) >> 32); in __ifh_encode_bitfield()
53 /* The b40-b47 goes into the next IFH byte */ in __ifh_encode_bitfield()
55 ifh_hdr[byte - 5] |= (u8)((encode & 0xFF0000000000) >> 40); in __ifh_encode_bitfield()
62 /* VSTAX.INGR_DROP_MODE = Enable. Don't make head-of-line blocking */ in sparx5_set_port_ifh()
95 ifh_encode_bitfield(ifh_hdr, timestamp, 232, 40); in sparx5_set_port_ifh_timestamp()
104 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); in sparx5_port_open()
110 phylink_start(port->phylink); in sparx5_port_open()
112 if (!ndev->phydev) { in sparx5_port_open()
114 port->conf.power_down = false; in sparx5_port_open()
115 if (port->conf.serdes_reset) in sparx5_port_open()
116 err = sparx5_serdes_set(port->sparx5, port, &port->conf); in sparx5_port_open()
118 err = phy_power_on(port->serdes); in sparx5_port_open()
128 phylink_stop(port->phylink); in sparx5_port_open()
129 phylink_disconnect_phy(port->phylink); in sparx5_port_open()
142 phylink_stop(port->phylink); in sparx5_port_stop()
143 phylink_disconnect_phy(port->phylink); in sparx5_port_stop()
145 if (!ndev->phydev) { in sparx5_port_stop()
147 port->conf.power_down = true; in sparx5_port_stop()
148 if (port->conf.serdes_reset) in sparx5_port_stop()
149 err = sparx5_serdes_set(port->sparx5, port, &port->conf); in sparx5_port_stop()
151 err = phy_power_off(port->serdes); in sparx5_port_stop()
161 struct sparx5 *sparx5 = port->sparx5; in sparx5_set_rx_mode()
163 if (!test_bit(port->portno, sparx5->bridge_mask)) in sparx5_set_rx_mode()
173 ret = snprintf(buf, len, "p%d", port->portno); in sparx5_port_get_phys_port_name()
175 return -EINVAL; in sparx5_port_get_phys_port_name()
183 struct sparx5 *sparx5 = port->sparx5; in sparx5_set_mac_address()
186 if (!is_valid_ether_addr(addr->sa_data)) in sparx5_set_mac_address()
187 return -EADDRNOTAVAIL; in sparx5_set_mac_address()
190 sparx5_mact_forget(sparx5, dev->dev_addr, port->pvid); in sparx5_set_mac_address()
193 sparx5_mact_learn(sparx5, PGID_CPU, addr->sa_data, port->pvid); in sparx5_set_mac_address()
196 eth_hw_addr_set(dev, addr->sa_data); in sparx5_set_mac_address()
205 struct sparx5 *sparx5 = sparx5_port->sparx5; in sparx5_get_port_parent_id()
207 ppid->id_len = sizeof(sparx5->base_mac); in sparx5_get_port_parent_id()
208 memcpy(&ppid->id, &sparx5->base_mac, ppid->id_len); in sparx5_get_port_parent_id()
217 struct sparx5 *sparx5 = sparx5_port->sparx5; in sparx5_port_hwtstamp_get()
219 if (!sparx5->ptp) in sparx5_port_hwtstamp_get()
220 return -EOPNOTSUPP; in sparx5_port_hwtstamp_get()
232 struct sparx5 *sparx5 = sparx5_port->sparx5; in sparx5_port_hwtstamp_set()
234 if (!sparx5->ptp) in sparx5_port_hwtstamp_set()
235 return -EOPNOTSUPP; in sparx5_port_hwtstamp_set()
258 return dev && (dev->netdev_ops == &sparx5_port_netdev_ops); in sparx5_netdevice_check()
266 ndev = devm_alloc_etherdev_mqs(sparx5->dev, sizeof(struct sparx5_port), in sparx5_create_netdev()
269 return ERR_PTR(-ENOMEM); in sparx5_create_netdev()
271 ndev->hw_features |= NETIF_F_HW_TC; in sparx5_create_netdev()
272 ndev->features |= NETIF_F_HW_TC; in sparx5_create_netdev()
274 SET_NETDEV_DEV(ndev, sparx5->dev); in sparx5_create_netdev()
276 spx5_port->ndev = ndev; in sparx5_create_netdev()
277 spx5_port->sparx5 = sparx5; in sparx5_create_netdev()
278 spx5_port->portno = portno; in sparx5_create_netdev()
280 ndev->netdev_ops = &sparx5_port_netdev_ops; in sparx5_create_netdev()
281 ndev->ethtool_ops = &sparx5_ethtool_ops; in sparx5_create_netdev()
283 eth_hw_addr_gen(ndev, sparx5->base_mac, portno + 1); in sparx5_create_netdev()
294 if (sparx5->ports[portno]) { in sparx5_register_netdevs()
295 err = register_netdev(sparx5->ports[portno]->ndev); in sparx5_register_netdevs()
297 dev_err(sparx5->dev, in sparx5_register_netdevs()
302 sparx5_port_inj_timer_setup(sparx5->ports[portno]); in sparx5_register_netdevs()
313 port = sparx5->ports[portno]; in sparx5_destroy_netdevs()
314 if (port && port->phylink) { in sparx5_destroy_netdevs()
317 sparx5_port_stop(port->ndev); in sparx5_destroy_netdevs()
318 phylink_disconnect_phy(port->phylink); in sparx5_destroy_netdevs()
320 phylink_destroy(port->phylink); in sparx5_destroy_netdevs()
321 port->phylink = NULL; in sparx5_destroy_netdevs()
331 if (sparx5->ports[portno]) in sparx5_unregister_netdevs()
332 unregister_netdev(sparx5->ports[portno]->ndev); in sparx5_unregister_netdevs()