Lines Matching +full:28 +full:g
87 #define ANA_AC_PROBE_CFG(g) \ argument
88 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 0, 0, 1, 4)
127 #define ANA_AC_PROBE_PORT_CFG(g) \ argument
128 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 8, 0, 1, 4)
131 #define ANA_AC_PROBE_PORT_CFG1(g) \ argument
132 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 12, 0, 1, 4)
135 #define ANA_AC_PROBE_PORT_CFG2(g) \ argument
136 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 16, 0, 1, 4)
145 #define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC,\ argument
146 0, 1, 849920, g, 102, 16, 0, 0, 1, 4)
149 #define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC,\ argument
150 0, 1, 849920, g, 102, 16, 4, 0, 1, 4)
153 #define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC,\ argument
154 0, 1, 849920, g, 102, 16, 8, 0, 1, 4)
163 #define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC,\ argument
164 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4)
167 #define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC,\ argument
168 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4)
171 #define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC,\ argument
172 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4)
181 #define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC,\ argument
182 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4)
219 #define ANA_AC_TSN_SF_CFG(g) __REG(TARGET_ANA_AC,\ argument
220 0, 1, 839680, g, 1024, 4, 0, 0, 1, 4)
284 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28)
360 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA BIT(28)
471 #define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC,\ argument
472 0, 1, 843776, g, 70, 64, 4, r, 4, 4)
493 #define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC,\ argument
494 0, 1, 843776, g, 70, 64, 20, r, 4, 4)
530 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA BIT(28)
697 #define ANA_ACL_VCAP_S2_KEY_SEL(g, r) __REG(TARGET_ANA_ACL,\ argument
698 0, 1, 34200, g, 134, 16, 0, r, 4, 4)
749 #define ANA_ACL_CNT_A(g) __REG(TARGET_ANA_ACL,\ argument
750 0, 1, 0, g, 4096, 4, 0, 0, 1, 4)
753 #define ANA_ACL_CNT_B(g) __REG(TARGET_ANA_ACL,\ argument
754 0, 1, 16384, g, 4096, 4, 0, 0, 1, 4)
935 #define ANA_AC_SDLB_XLB_START(g) __REG(TARGET_ANA_AC_SDLB,\ argument
936 0, 1, 295468, g, 10, 24, 0, 0, 1, 4)
945 #define ANA_AC_SDLB_PUP_INTERVAL(g) __REG(TARGET_ANA_AC_SDLB,\ argument
946 0, 1, 295468, g, 10, 24, 4, 0, 1, 4)
955 #define ANA_AC_SDLB_PUP_CTRL(g) __REG(TARGET_ANA_AC_SDLB,\ argument
956 0, 1, 295468, g, 10, 24, 8, 0, 1, 4)
971 #define ANA_AC_SDLB_LBGRP_MISC(g) __REG(TARGET_ANA_AC_SDLB,\ argument
972 0, 1, 295468, g, 10, 24, 12, 0, 1, 4)
981 #define ANA_AC_SDLB_FRM_RATE_TOKENS(g) __REG(TARGET_ANA_AC_SDLB,\ argument
982 0, 1, 295468, g, 10, 24, 16, 0, 1, 4)
991 #define ANA_AC_SDLB_LBGRP_STATE_TBL(g) __REG(TARGET_ANA_AC_SDLB,\ argument
992 0, 1, 295468, g, 10, 24, 20, 0, 1, 4)
1006 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT GENMASK(28, 16)
1013 #define ANA_AC_SDLB_PUP_TOKENS(g, r) __REG(TARGET_ANA_AC_SDLB,\ argument
1014 0, 1, 0, g, 4616, 64, 0, r, 2, 4)
1023 #define ANA_AC_SDLB_THRES(g, r) __REG(TARGET_ANA_AC_SDLB,\ argument
1024 0, 1, 0, g, 4616, 64, 8, r, 2, 4)
1039 #define ANA_AC_SDLB_XLB_NEXT(g) __REG(TARGET_ANA_AC_SDLB,\ argument
1040 0, 1, 0, g, 4616, 64, 16, 0, 1, 4)
1055 #define ANA_AC_SDLB_INH_CTRL(g, r) __REG(TARGET_ANA_AC_SDLB,\ argument
1056 0, 1, 0, g, 4616, 64, 20, r, 2, 4)
1077 #define ANA_AC_SDLB_INH_LBSET_ADDR(g) __REG(TARGET_ANA_AC_SDLB,\ argument
1078 0, 1, 0, g, 4616, 64, 28, 0, 1, 4)
1087 #define ANA_AC_SDLB_DLB_MISC(g) __REG(TARGET_ANA_AC_SDLB,\ argument
1088 0, 1, 0, g, 4616, 64, 32, 0, 1, 4)
1109 #define ANA_AC_SDLB_DLB_CFG(g) __REG(TARGET_ANA_AC_SDLB,\ argument
1110 0, 1, 0, g, 4616, 64, 36, 0, 1, 4)
1161 #define ANA_CL_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\ argument
1162 0, 1, 131072, g, 70, 512, 4, 0, 1, 4)
1183 #define ANA_CL_VLAN_FILTER_CTRL(g, r) __REG(TARGET_ANA_CL,\ argument
1184 0, 1, 131072, g, 70, 512, 8, r, 3, 4)
1253 #define ANA_CL_ETAG_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\ argument
1254 0, 1, 131072, g, 70, 512, 20, 0, 1, 4)
1269 #define ANA_CL_VLAN_CTRL(g) __REG(TARGET_ANA_CL,\ argument
1270 0, 1, 131072, g, 70, 512, 32, 0, 1, 4)
1339 #define ANA_CL_VLAN_CTRL_2(g) __REG(TARGET_ANA_CL,\ argument
1340 0, 1, 131072, g, 70, 512, 36, 0, 1, 4)
1349 #define ANA_CL_PCP_DEI_MAP_CFG(g, r) __REG(TARGET_ANA_CL,\ argument
1350 0, 1, 131072, g, 70, 512, 108, r, 16, 4)
1365 #define ANA_CL_QOS_CFG(g) __REG(TARGET_ANA_CL,\ argument
1366 0, 1, 131072, g, 70, 512, 172, 0, 1, 4)
1441 #define ANA_CL_CAPTURE_BPDU_CFG(g) __REG(TARGET_ANA_CL,\ argument
1442 0, 1, 131072, g, 70, 512, 196, 0, 1, 4)
1445 #define ANA_CL_ADV_CL_CFG_2(g, r) __REG(TARGET_ANA_CL,\ argument
1446 0, 1, 131072, g, 70, 512, 200, r, 6, 4)
1461 #define ANA_CL_ADV_CL_CFG(g, r) __REG(TARGET_ANA_CL,\ argument
1462 0, 1, 131072, g, 70, 512, 224, r, 6, 4)
1642 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4)
1665 #define ANA_L2_DLB_CFG(g) __REG(TARGET_ANA_L2,\ argument
1666 0, 1, 0, g, 4096, 128, 56, 0, 1, 4)
1675 #define ANA_L2_TSN_CFG(g) __REG(TARGET_ANA_L2,\ argument
1676 0, 1, 0, g, 4096, 128, 100, 0, 1, 4)
1695 #define ANA_L3_VLAN_CFG(g) __REG(TARGET_ANA_L3,\ argument
1696 0, 1, 0, g, 5120, 64, 8, 0, 1, 4)
1753 #define ANA_L3_VLAN_MASK_CFG(g) __REG(TARGET_ANA_L3,\ argument
1754 0, 1, 0, g, 5120, 64, 16, 0, 1, 4)
1757 #define ANA_L3_VLAN_MASK_CFG1(g) __REG(TARGET_ANA_L3,\ argument
1758 0, 1, 0, g, 5120, 64, 20, 0, 1, 4)
1761 #define ANA_L3_VLAN_MASK_CFG2(g) __REG(TARGET_ANA_L3,\ argument
1762 0, 1, 0, g, 5120, 64, 24, 0, 1, 4)
1771 #define ASM_RX_IN_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1772 0, 1, 0, g, 65, 512, 0, 0, 1, 4)
1775 #define ASM_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1776 0, 1, 0, g, 65, 512, 4, 0, 1, 4)
1779 #define ASM_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\ argument
1780 0, 1, 0, g, 65, 512, 8, 0, 1, 4)
1783 #define ASM_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\ argument
1784 0, 1, 0, g, 65, 512, 12, 0, 1, 4)
1787 #define ASM_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1788 0, 1, 0, g, 65, 512, 16, 0, 1, 4)
1791 #define ASM_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1792 0, 1, 0, g, 65, 512, 20, 0, 1, 4)
1795 #define ASM_RX_UC_CNT(g) __REG(TARGET_ASM,\ argument
1796 0, 1, 0, g, 65, 512, 24, 0, 1, 4)
1799 #define ASM_RX_MC_CNT(g) __REG(TARGET_ASM,\ argument
1800 0, 1, 0, g, 65, 512, 28, 0, 1, 4)
1803 #define ASM_RX_BC_CNT(g) __REG(TARGET_ASM,\ argument
1804 0, 1, 0, g, 65, 512, 32, 0, 1, 4)
1807 #define ASM_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1808 0, 1, 0, g, 65, 512, 36, 0, 1, 4)
1811 #define ASM_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\ argument
1812 0, 1, 0, g, 65, 512, 40, 0, 1, 4)
1815 #define ASM_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\ argument
1816 0, 1, 0, g, 65, 512, 44, 0, 1, 4)
1819 #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1820 0, 1, 0, g, 65, 512, 48, 0, 1, 4)
1823 #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1824 0, 1, 0, g, 65, 512, 52, 0, 1, 4)
1827 #define ASM_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\ argument
1828 0, 1, 0, g, 65, 512, 56, 0, 1, 4)
1831 #define ASM_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\ argument
1832 0, 1, 0, g, 65, 512, 60, 0, 1, 4)
1835 #define ASM_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\ argument
1836 0, 1, 0, g, 65, 512, 64, 0, 1, 4)
1839 #define ASM_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ argument
1840 0, 1, 0, g, 65, 512, 68, 0, 1, 4)
1843 #define ASM_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ argument
1844 0, 1, 0, g, 65, 512, 72, 0, 1, 4)
1847 #define ASM_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ argument
1848 0, 1, 0, g, 65, 512, 76, 0, 1, 4)
1851 #define ASM_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ argument
1852 0, 1, 0, g, 65, 512, 80, 0, 1, 4)
1855 #define ASM_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ argument
1856 0, 1, 0, g, 65, 512, 84, 0, 1, 4)
1859 #define ASM_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ argument
1860 0, 1, 0, g, 65, 512, 88, 0, 1, 4)
1863 #define ASM_RX_IPG_SHRINK_CNT(g) __REG(TARGET_ASM,\ argument
1864 0, 1, 0, g, 65, 512, 92, 0, 1, 4)
1867 #define ASM_TX_OUT_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1868 0, 1, 0, g, 65, 512, 96, 0, 1, 4)
1871 #define ASM_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\ argument
1872 0, 1, 0, g, 65, 512, 100, 0, 1, 4)
1875 #define ASM_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1876 0, 1, 0, g, 65, 512, 104, 0, 1, 4)
1879 #define ASM_TX_UC_CNT(g) __REG(TARGET_ASM,\ argument
1880 0, 1, 0, g, 65, 512, 108, 0, 1, 4)
1883 #define ASM_TX_MC_CNT(g) __REG(TARGET_ASM,\ argument
1884 0, 1, 0, g, 65, 512, 112, 0, 1, 4)
1887 #define ASM_TX_BC_CNT(g) __REG(TARGET_ASM,\ argument
1888 0, 1, 0, g, 65, 512, 116, 0, 1, 4)
1891 #define ASM_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\ argument
1892 0, 1, 0, g, 65, 512, 120, 0, 1, 4)
1895 #define ASM_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ argument
1896 0, 1, 0, g, 65, 512, 124, 0, 1, 4)
1899 #define ASM_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ argument
1900 0, 1, 0, g, 65, 512, 128, 0, 1, 4)
1903 #define ASM_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ argument
1904 0, 1, 0, g, 65, 512, 132, 0, 1, 4)
1907 #define ASM_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ argument
1908 0, 1, 0, g, 65, 512, 136, 0, 1, 4)
1911 #define ASM_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ argument
1912 0, 1, 0, g, 65, 512, 140, 0, 1, 4)
1915 #define ASM_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ argument
1916 0, 1, 0, g, 65, 512, 144, 0, 1, 4)
1919 #define ASM_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\ argument
1920 0, 1, 0, g, 65, 512, 148, 0, 1, 4)
1923 #define ASM_RX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ argument
1924 0, 1, 0, g, 65, 512, 152, 0, 1, 4)
1927 #define ASM_RX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ argument
1928 0, 1, 0, g, 65, 512, 156, 0, 1, 4)
1931 #define ASM_TX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ argument
1932 0, 1, 0, g, 65, 512, 160, 0, 1, 4)
1935 #define ASM_TX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ argument
1936 0, 1, 0, g, 65, 512, 164, 0, 1, 4)
1939 #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1940 0, 1, 0, g, 65, 512, 168, 0, 1, 4)
1943 #define ASM_PMAC_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\ argument
1944 0, 1, 0, g, 65, 512, 172, 0, 1, 4)
1947 #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\ argument
1948 0, 1, 0, g, 65, 512, 176, 0, 1, 4)
1951 #define ASM_PMAC_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1952 0, 1, 0, g, 65, 512, 180, 0, 1, 4)
1955 #define ASM_PMAC_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
1956 0, 1, 0, g, 65, 512, 184, 0, 1, 4)
1959 #define ASM_PMAC_RX_UC_CNT(g) __REG(TARGET_ASM,\ argument
1960 0, 1, 0, g, 65, 512, 188, 0, 1, 4)
1963 #define ASM_PMAC_RX_MC_CNT(g) __REG(TARGET_ASM,\ argument
1964 0, 1, 0, g, 65, 512, 192, 0, 1, 4)
1967 #define ASM_PMAC_RX_BC_CNT(g) __REG(TARGET_ASM,\ argument
1968 0, 1, 0, g, 65, 512, 196, 0, 1, 4)
1971 #define ASM_PMAC_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1972 0, 1, 0, g, 65, 512, 200, 0, 1, 4)
1975 #define ASM_PMAC_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\ argument
1976 0, 1, 0, g, 65, 512, 204, 0, 1, 4)
1979 #define ASM_PMAC_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\ argument
1980 0, 1, 0, g, 65, 512, 208, 0, 1, 4)
1983 #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1984 0, 1, 0, g, 65, 512, 212, 0, 1, 4)
1987 #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ argument
1988 0, 1, 0, g, 65, 512, 216, 0, 1, 4)
1991 #define ASM_PMAC_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\ argument
1992 0, 1, 0, g, 65, 512, 220, 0, 1, 4)
1995 #define ASM_PMAC_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\ argument
1996 0, 1, 0, g, 65, 512, 224, 0, 1, 4)
1999 #define ASM_PMAC_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\ argument
2000 0, 1, 0, g, 65, 512, 228, 0, 1, 4)
2003 #define ASM_PMAC_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ argument
2004 0, 1, 0, g, 65, 512, 232, 0, 1, 4)
2007 #define ASM_PMAC_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ argument
2008 0, 1, 0, g, 65, 512, 236, 0, 1, 4)
2011 #define ASM_PMAC_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ argument
2012 0, 1, 0, g, 65, 512, 240, 0, 1, 4)
2015 #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ argument
2016 0, 1, 0, g, 65, 512, 244, 0, 1, 4)
2019 #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ argument
2020 0, 1, 0, g, 65, 512, 248, 0, 1, 4)
2023 #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ argument
2024 0, 1, 0, g, 65, 512, 252, 0, 1, 4)
2027 #define ASM_PMAC_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\ argument
2028 0, 1, 0, g, 65, 512, 256, 0, 1, 4)
2031 #define ASM_PMAC_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ argument
2032 0, 1, 0, g, 65, 512, 260, 0, 1, 4)
2035 #define ASM_PMAC_TX_UC_CNT(g) __REG(TARGET_ASM,\ argument
2036 0, 1, 0, g, 65, 512, 264, 0, 1, 4)
2039 #define ASM_PMAC_TX_MC_CNT(g) __REG(TARGET_ASM,\ argument
2040 0, 1, 0, g, 65, 512, 268, 0, 1, 4)
2043 #define ASM_PMAC_TX_BC_CNT(g) __REG(TARGET_ASM,\ argument
2044 0, 1, 0, g, 65, 512, 272, 0, 1, 4)
2047 #define ASM_PMAC_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\ argument
2048 0, 1, 0, g, 65, 512, 276, 0, 1, 4)
2051 #define ASM_PMAC_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ argument
2052 0, 1, 0, g, 65, 512, 280, 0, 1, 4)
2055 #define ASM_PMAC_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ argument
2056 0, 1, 0, g, 65, 512, 284, 0, 1, 4)
2059 #define ASM_PMAC_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ argument
2060 0, 1, 0, g, 65, 512, 288, 0, 1, 4)
2063 #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ argument
2064 0, 1, 0, g, 65, 512, 292, 0, 1, 4)
2067 #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ argument
2068 0, 1, 0, g, 65, 512, 296, 0, 1, 4)
2071 #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ argument
2072 0, 1, 0, g, 65, 512, 300, 0, 1, 4)
2075 #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\ argument
2076 0, 1, 0, g, 65, 512, 304, 0, 1, 4)
2079 #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) __REG(TARGET_ASM,\ argument
2080 0, 1, 0, g, 65, 512, 308, 0, 1, 4)
2083 #define ASM_MM_RX_SMD_ERR_CNT(g) __REG(TARGET_ASM,\ argument
2084 0, 1, 0, g, 65, 512, 312, 0, 1, 4)
2087 #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) __REG(TARGET_ASM,\ argument
2088 0, 1, 0, g, 65, 512, 316, 0, 1, 4)
2091 #define ASM_MM_RX_MERGE_FRAG_CNT(g) __REG(TARGET_ASM,\ argument
2092 0, 1, 0, g, 65, 512, 320, 0, 1, 4)
2095 #define ASM_MM_TX_PFRAGMENT_CNT(g) __REG(TARGET_ASM,\ argument
2096 0, 1, 0, g, 65, 512, 324, 0, 1, 4)
2099 #define ASM_TX_MULTI_COLL_CNT(g) __REG(TARGET_ASM,\ argument
2100 0, 1, 0, g, 65, 512, 328, 0, 1, 4)
2103 #define ASM_TX_LATE_COLL_CNT(g) __REG(TARGET_ASM,\ argument
2104 0, 1, 0, g, 65, 512, 332, 0, 1, 4)
2107 #define ASM_TX_XCOLL_CNT(g) __REG(TARGET_ASM,\ argument
2108 0, 1, 0, g, 65, 512, 336, 0, 1, 4)
2111 #define ASM_TX_DEFER_CNT(g) __REG(TARGET_ASM,\ argument
2112 0, 1, 0, g, 65, 512, 340, 0, 1, 4)
2115 #define ASM_TX_XDEFER_CNT(g) __REG(TARGET_ASM,\ argument
2116 0, 1, 0, g, 65, 512, 344, 0, 1, 4)
2119 #define ASM_TX_BACKOFF1_CNT(g) __REG(TARGET_ASM,\ argument
2120 0, 1, 0, g, 65, 512, 348, 0, 1, 4)
2123 #define ASM_TX_CSENSE_CNT(g) __REG(TARGET_ASM,\ argument
2124 0, 1, 0, g, 65, 512, 352, 0, 1, 4)
2127 #define ASM_RX_IN_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2128 0, 1, 0, g, 65, 512, 356, 0, 1, 4)
2137 #define ASM_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2138 0, 1, 0, g, 65, 512, 360, 0, 1, 4)
2147 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2148 0, 1, 0, g, 65, 512, 364, 0, 1, 4)
2157 #define ASM_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2158 0, 1, 0, g, 65, 512, 368, 0, 1, 4)
2167 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2168 0, 1, 0, g, 65, 512, 372, 0, 1, 4)
2177 #define ASM_TX_OUT_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2178 0, 1, 0, g, 65, 512, 376, 0, 1, 4)
2187 #define ASM_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2188 0, 1, 0, g, 65, 512, 380, 0, 1, 4)
2197 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ argument
2198 0, 1, 0, g, 65, 512, 384, 0, 1, 4)
2207 #define ASM_RX_SYNC_LOST_ERR_CNT(g) __REG(TARGET_ASM,\ argument
2208 0, 1, 0, g, 65, 512, 388, 0, 1, 4)
2488 t, 12, 0, 0, 1, 60, 28, 0, 1, 4)
2570 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28)
2668 t, 8, 0, 0, 1, 60, 28, 0, 1, 4)
2716 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28)
2986 t, 65, 52, 0, 1, 36, 28, 0, 1, 4)
3374 t, 13, 0, 0, 1, 60, 28, 0, 1, 4)
3448 t, 13, 60, 0, 1, 312, 28, 0, 1, 4)
3778 t, 13, 372, 0, 1, 64, 28, 0, 1, 4)
3846 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28)
4071 #define EACL_VCAP_ES2_KEY_SEL(g, r) __REG(TARGET_EACL,\ argument
4072 0, 1, 149504, g, 138, 8, 0, r, 2, 4)
4099 #define EACL_ES2_CNT(g) __REG(TARGET_EACL,\ argument
4100 0, 1, 122880, g, 2048, 4, 0, 0, 1, 4)
4416 #define FDMA_ERRORS_ERR_XTR_OVF GENMASK(29, 28)
4482 #define GCB_CHIP_ID_REV_ID GENMASK(31, 28)
4555 #define GCB_SIO_CLOCK(g) __REG(TARGET_GCB,\ argument
4556 0, 1, 876, g, 3, 280, 20, 0, 1, 4)
4571 #define HSCH_CIR_CFG(g) __REG(TARGET_HSCH,\ argument
4572 0, 1, 0, g, 5040, 32, 0, 0, 1, 4)
4587 #define HSCH_EIR_CFG(g) __REG(TARGET_HSCH,\ argument
4588 0, 1, 0, g, 5040, 32, 4, 0, 1, 4)
4603 #define HSCH_SE_CFG(g) __REG(TARGET_HSCH,\ argument
4604 0, 1, 0, g, 5040, 32, 8, 0, 1, 4)
4637 #define HSCH_SE_CONNECT(g) __REG(TARGET_HSCH,\ argument
4638 0, 1, 0, g, 5040, 32, 12, 0, 1, 4)
4647 #define HSCH_SE_DLB_SENSE(g) __REG(TARGET_HSCH,\ argument
4648 0, 1, 0, g, 5040, 32, 16, 0, 1, 4)
4681 #define HSCH_DWRR_ENTRY(g) __REG(TARGET_HSCH,\ argument
4682 0, 1, 162816, g, 72, 4, 0, 0, 1, 4)
4729 #define HSCH_HSCH_TIMER_CFG(g, r) __REG(TARGET_HSCH,\ argument
4730 0, 1, 161664, g, 4, 32, 0, r, 4, 4)
4739 #define HSCH_HSCH_LEAK_CFG(g, r) __REG(TARGET_HSCH,\ argument
4740 0, 1, 161664, g, 4, 32, 16, r, 4, 4)
4902 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID GENMASK(28, 16)
4922 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD BIT(28)
5118 #define LRN_AUTOAGE_CFG_UNIT_SIZE GENMASK(29, 28)
5238 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE BIT(28)
5897 #define PORT_CONF_USGMII_CFG(g) __REG(TARGET_PORT_CONF,\ argument
5898 0, 1, 72, g, 6, 8, 0, 0, 1, 4)
6001 #define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP,\ argument
6002 0, 1, 336, g, 3, 28, 0, r, 2, 4)
6005 #define PTP_PTP_CUR_NSEC(g) __REG(TARGET_PTP,\ argument
6006 0, 1, 336, g, 3, 28, 8, 0, 1, 4)
6015 #define PTP_PTP_CUR_NSEC_FRAC(g) __REG(TARGET_PTP,\ argument
6016 0, 1, 336, g, 3, 28, 12, 0, 1, 4)
6025 #define PTP_PTP_CUR_SEC_LSB(g) __REG(TARGET_PTP,\ argument
6026 0, 1, 336, g, 3, 28, 16, 0, 1, 4)
6029 #define PTP_PTP_CUR_SEC_MSB(g) __REG(TARGET_PTP,\ argument
6030 0, 1, 336, g, 3, 28, 20, 0, 1, 4)
6039 #define PTP_NTP_CUR_NSEC(g) __REG(TARGET_PTP,\ argument
6040 0, 1, 336, g, 3, 28, 24, 0, 1, 4)
6043 #define PTP_PTP_PIN_CFG(g) __REG(TARGET_PTP,\ argument
6044 0, 1, 0, g, 5, 64, 0, 0, 1, 4)
6046 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION GENMASK(28, 26)
6101 #define PTP_PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP,\ argument
6102 0, 1, 0, g, 5, 64, 4, 0, 1, 4)
6111 #define PTP_PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP,\ argument
6112 0, 1, 0, g, 5, 64, 8, 0, 1, 4)
6115 #define PTP_PTP_TOD_NSEC(g) __REG(TARGET_PTP,\ argument
6116 0, 1, 0, g, 5, 64, 12, 0, 1, 4)
6125 #define PTP_PTP_TOD_NSEC_FRAC(g) __REG(TARGET_PTP,\ argument
6126 0, 1, 0, g, 5, 64, 16, 0, 1, 4)
6135 #define PTP_NTP_NSEC(g) __REG(TARGET_PTP,\ argument
6136 0, 1, 0, g, 5, 64, 20, 0, 1, 4)
6139 #define PTP_PIN_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\ argument
6140 0, 1, 0, g, 5, 64, 24, 0, 1, 4)
6149 #define PTP_PIN_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\ argument
6150 0, 1, 0, g, 5, 64, 28, 0, 1, 4)
6159 #define PTP_PIN_IOBOUNCH_DELAY(g) __REG(TARGET_PTP,\ argument
6160 0, 1, 0, g, 5, 64, 32, 0, 1, 4)
6175 #define PTP_PHAD_CTRL(g) __REG(TARGET_PTP,\ argument
6176 0, 1, 420, g, 5, 8, 0, 0, 1, 4)
6203 #define PTP_PHAD_CYC_STAT(g) __REG(TARGET_PTP,\ argument
6204 0, 1, 420, g, 5, 8, 4, 0, 1, 4)
6275 #define QRES_RES_CFG(g) __REG(TARGET_QRES,\ argument
6276 0, 1, 0, g, 5120, 16, 0, 0, 1, 4)
6285 #define QRES_RES_STAT(g) __REG(TARGET_QRES,\ argument
6286 0, 1, 0, g, 5120, 16, 4, 0, 1, 4)
6295 #define QRES_RES_STAT_CUR(g) __REG(TARGET_QRES,\ argument
6296 0, 1, 0, g, 5120, 16, 8, 0, 1, 4)
6342 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
6611 #define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW,\ argument
6612 0, 1, 360448, g, 70, 256, 0, 0, 1, 4)
6633 #define REW_PCP_MAP_DE0(g, r) __REG(TARGET_REW,\ argument
6634 0, 1, 360448, g, 70, 256, 4, r, 8, 4)
6643 #define REW_PCP_MAP_DE1(g, r) __REG(TARGET_REW,\ argument
6644 0, 1, 360448, g, 70, 256, 36, r, 8, 4)
6653 #define REW_DEI_MAP_DE0(g, r) __REG(TARGET_REW,\ argument
6654 0, 1, 360448, g, 70, 256, 68, r, 8, 4)
6663 #define REW_DEI_MAP_DE1(g, r) __REG(TARGET_REW,\ argument
6664 0, 1, 360448, g, 70, 256, 100, r, 8, 4)
6673 #define REW_TAG_CTRL(g) __REG(TARGET_REW,\ argument
6674 0, 1, 360448, g, 70, 256, 132, 0, 1, 4)
6713 #define REW_DSCP_MAP(g) __REG(TARGET_REW,\ argument
6714 0, 1, 360448, g, 70, 256, 136, 0, 1, 4)
6990 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7152 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7304 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7375 #define XQS_QLIMIT_SHR_TOP_CFG(g) __REG(TARGET_XQS,\ argument
7376 0, 1, 7936, g, 4, 48, 0, 0, 1, 4)
7385 #define XQS_QLIMIT_SHR_ATOP_CFG(g) __REG(TARGET_XQS,\ argument
7386 0, 1, 7936, g, 4, 48, 4, 0, 1, 4)
7395 #define XQS_QLIMIT_SHR_CTOP_CFG(g) __REG(TARGET_XQS,\ argument
7396 0, 1, 7936, g, 4, 48, 8, 0, 1, 4)
7405 #define XQS_QLIMIT_SHR_QLIM_CFG(g) __REG(TARGET_XQS,\ argument
7406 0, 1, 7936, g, 4, 48, 12, 0, 1, 4)
7415 #define XQS_CNT(g) __REG(TARGET_XQS,\ argument
7416 0, 1, 0, g, 1024, 4, 0, 0, 1, 4)