Lines Matching +full:1 +full:x
19 TARGET_ANA_AC = 1,
62 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4)
64 #define ANA_AC_RAM_INIT_RAM_INIT BIT(1)
65 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ argument
66 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
67 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\ argument
68 FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)
71 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
72 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
73 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
74 FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
78 0, 1, 894472, 0, 1, 352, 52, r, 3, 4)
81 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ argument
82 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
83 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\ argument
84 FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x)
88 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 0, 0, 1, 4)
91 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x)\ argument
92 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x)
93 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x)\ argument
94 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x)
97 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x)\ argument
98 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x)
99 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x)\ argument
100 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x)
103 #define ANA_AC_PROBE_CFG_PROBE_VID_SET(x)\ argument
104 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VID, x)
105 #define ANA_AC_PROBE_CFG_PROBE_VID_GET(x)\ argument
106 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VID, x)
109 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x)\ argument
110 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x)
111 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x)\ argument
112 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x)
115 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x)\ argument
116 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x)
117 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x)\ argument
118 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x)
120 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION GENMASK(1, 0)
121 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x)\ argument
122 FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x)
123 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x)\ argument
124 FIELD_GET(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x)
128 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 8, 0, 1, 4)
132 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 12, 0, 1, 4)
136 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 16, 0, 1, 4)
139 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x)\ argument
140 FIELD_PREP(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x)
141 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x)\ argument
142 FIELD_GET(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x)
146 0, 1, 849920, g, 102, 16, 0, 0, 1, 4)
150 0, 1, 849920, g, 102, 16, 4, 0, 1, 4)
154 0, 1, 849920, g, 102, 16, 8, 0, 1, 4)
157 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\ argument
158 FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x)
159 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\ argument
160 FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x)
164 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4)
168 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4)
172 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4)
175 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\ argument
176 FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x)
177 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\ argument
178 FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x)
182 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4)
185 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\ argument
186 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
187 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\ argument
188 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
190 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA BIT(1)
191 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\ argument
192 FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
193 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\ argument
194 FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
197 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\ argument
198 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
199 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\ argument
200 FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
204 0, 1, 839136, 0, 1, 4, 0, 0, 1, 4)
207 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\ argument
208 FIELD_PREP(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x)
209 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\ argument
210 FIELD_GET(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x)
213 #define ANA_AC_TSN_SF_PORT_NUM_SET(x)\ argument
214 FIELD_PREP(ANA_AC_TSN_SF_PORT_NUM, x)
215 #define ANA_AC_TSN_SF_PORT_NUM_GET(x)\ argument
216 FIELD_GET(ANA_AC_TSN_SF_PORT_NUM, x)
220 0, 1, 839680, g, 1024, 4, 0, 0, 1, 4)
223 #define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\ argument
224 FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_SGID, x)
225 #define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\ argument
226 FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_SGID, x)
229 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\ argument
230 FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x)
231 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_GET(x)\ argument
232 FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x)
234 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA BIT(1)
235 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_SET(x)\ argument
236 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x)
237 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_GET(x)\ argument
238 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x)
241 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_SET(x)\ argument
242 FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x)
243 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x)\ argument
244 FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x)
248 0, 1, 839072, 0, 1, 16, 0, 0, 1, 4)
251 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\ argument
252 FIELD_PREP(ANA_AC_TSN_SF_STATUS_FRM_LEN, x)
253 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_GET(x)\ argument
254 FIELD_GET(ANA_AC_TSN_SF_STATUS_FRM_LEN, x)
257 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_SET(x)\ argument
258 FIELD_PREP(ANA_AC_TSN_SF_STATUS_DLB_DROP, x)
259 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\ argument
260 FIELD_GET(ANA_AC_TSN_SF_STATUS_DLB_DROP, x)
262 #define ANA_AC_TSN_SF_STATUS_TSN_SFID GENMASK(10, 1)
263 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\ argument
264 FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSN_SFID, x)
265 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\ argument
266 FIELD_GET(ANA_AC_TSN_SF_STATUS_TSN_SFID, x)
269 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\ argument
270 FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x)
271 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\ argument
272 FIELD_GET(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x)
276 0, 1, 839140, 0, 1, 12, 0, 0, 1, 4)
279 #define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\ argument
280 FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_SGID, x)
281 #define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\ argument
282 FIELD_GET(ANA_AC_SG_ACCESS_CTRL_SGID, x)
285 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\ argument
286 FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x)
287 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\ argument
288 FIELD_GET(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x)
292 0, 1, 839140, 0, 1, 12, 8, 0, 1, 4)
295 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\ argument
296 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x)
297 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_GET(x)\ argument
298 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x)
301 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(x)\ argument
302 FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x)
303 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\ argument
304 FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x)
308 0, 1, 851584, 0, 1, 128, 48, 0, 1, 4)
312 0, 1, 851584, 0, 1, 128, 52, 0, 1, 4)
316 0, 1, 851584, 0, 1, 128, 56, 0, 1, 4)
319 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\ argument
320 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x)
321 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_GET(x)\ argument
322 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x)
325 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_SET(x)\ argument
326 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x)
327 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_GET(x)\ argument
328 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x)
331 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_SET(x)\ argument
332 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x)
333 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_GET(x)\ argument
334 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x)
337 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_SET(x)\ argument
338 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x)
339 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_GET(x)\ argument
340 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x)
343 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_SET(x)\ argument
344 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x)
345 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_GET(x)\ argument
346 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x)
349 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_SET(x)\ argument
350 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x)
351 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_GET(x)\ argument
352 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x)
355 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_SET(x)\ argument
356 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x)
357 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_GET(x)\ argument
358 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x)
361 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_SET(x)\ argument
362 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x)
363 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_GET(x)\ argument
364 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x)
367 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_SET(x)\ argument
368 FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x)
369 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\ argument
370 FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x)
374 0, 1, 851584, 0, 1, 128, 60, 0, 1, 4)
378 0, 1, 851584, 0, 1, 128, 64, 0, 1, 4)
382 0, 1, 851584, 0, 1, 128, 0, r, 4, 4)
385 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\ argument
386 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_IPS, x)
387 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_GET(x)\ argument
388 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_IPS, x)
391 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(x)\ argument
392 FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x)
393 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\ argument
394 FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x)
398 0, 1, 851584, 0, 1, 128, 16, r, 4, 4)
402 0, 1, 851584, 0, 1, 128, 32, r, 4, 4)
406 0, 1, 839088, 0, 1, 16, 0, 0, 1, 4)
410 0, 1, 839088, 0, 1, 16, 4, 0, 1, 4)
414 0, 1, 839088, 0, 1, 16, 8, 0, 1, 4)
417 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\ argument
418 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x)
419 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_GET(x)\ argument
420 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x)
423 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_SET(x)\ argument
424 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x)
425 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_GET(x)\ argument
426 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x)
429 #define ANA_AC_SG_STATUS_REG_3_IPS_SET(x)\ argument
430 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_IPS, x)
431 #define ANA_AC_SG_STATUS_REG_3_IPS_GET(x)\ argument
432 FIELD_GET(ANA_AC_SG_STATUS_REG_3_IPS, x)
435 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_SET(x)\ argument
436 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x)
437 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_GET(x)\ argument
438 FIELD_GET(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x)
441 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_SET(x)\ argument
442 FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x)
443 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\ argument
444 FIELD_GET(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x)
448 0, 1, 839088, 0, 1, 16, 12, 0, 1, 4)
452 0, 1, 851552, 0, 1, 20, 0, r, 4, 4)
455 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\ argument
456 FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x)
457 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\ argument
458 FIELD_GET(ANA_AC_PORT_SGE_CFG_MASK, x)
462 0, 1, 851552, 0, 1, 20, 16, 0, 1, 4)
465 #define ANA_AC_STAT_RESET_RESET_SET(x)\ argument
466 FIELD_PREP(ANA_AC_STAT_RESET_RESET, x)
467 #define ANA_AC_STAT_RESET_RESET_GET(x)\ argument
468 FIELD_GET(ANA_AC_STAT_RESET_RESET, x)
472 0, 1, 843776, g, 70, 64, 4, r, 4, 4)
475 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\ argument
476 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
477 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\ argument
478 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
480 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE GENMASK(3, 1)
481 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\ argument
482 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
483 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\ argument
484 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
487 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\ argument
488 FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
489 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\ argument
490 FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
494 0, 1, 843776, g, 70, 64, 20, r, 4, 4)
498 0, 1, 893792, 0, 1, 24, 0, r, 2, 4)
501 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x)\ argument
502 FIELD_PREP(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x)
503 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x)\ argument
504 FIELD_GET(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x)
508 0, 1, 893792, 0, 1, 24, 8, r, 2, 4)
511 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x)\ argument
512 FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x)
513 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x)\ argument
514 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x)
518 0, 1, 893792, 0, 1, 24, 16, r, 2, 4)
521 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x)\ argument
522 FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x)
523 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x)\ argument
524 FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x)
528 0, 1, 32768, 0, 1, 592, 0, r, 70, 4)
531 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\ argument
532 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x)
533 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_GET(x)\ argument
534 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x)
537 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_SET(x)\ argument
538 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x)
539 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_GET(x)\ argument
540 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x)
543 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_SET(x)\ argument
544 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x)
545 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_GET(x)\ argument
546 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x)
549 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_SET(x)\ argument
550 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x)
551 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_GET(x)\ argument
552 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x)
555 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_SET(x)\ argument
556 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x)
557 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_GET(x)\ argument
558 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x)
561 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_SET(x)\ argument
562 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x)
563 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_GET(x)\ argument
564 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x)
567 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_SET(x)\ argument
568 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x)
569 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_GET(x)\ argument
570 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x)
573 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_SET(x)\ argument
574 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x)
575 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_GET(x)\ argument
576 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x)
579 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_SET(x)\ argument
580 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x)
581 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_GET(x)\ argument
582 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x)
585 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_SET(x)\ argument
586 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x)
587 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_GET(x)\ argument
588 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x)
591 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_SET(x)\ argument
592 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x)
593 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_GET(x)\ argument
594 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x)
597 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_SET(x)\ argument
598 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x)
599 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_GET(x)\ argument
600 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x)
603 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_SET(x)\ argument
604 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x)
605 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_GET(x)\ argument
606 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x)
609 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(x)\ argument
610 FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x)
611 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\ argument
612 FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x)
616 0, 1, 32768, 0, 1, 592, 412, 0, 1, 4)
619 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\ argument
620 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x)
621 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_GET(x)\ argument
622 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x)
625 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_SET(x)\ argument
626 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x)
627 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_GET(x)\ argument
628 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x)
631 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_SET(x)\ argument
632 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x)
633 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_GET(x)\ argument
634 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x)
636 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA BIT(1)
637 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_SET(x)\ argument
638 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x)
639 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_GET(x)\ argument
640 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x)
643 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_SET(x)\ argument
644 FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x)
645 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\ argument
646 FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x)
650 0, 1, 32768, 0, 1, 592, 424, r, 4, 4)
653 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\ argument
654 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x)
655 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_GET(x)\ argument
656 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x)
659 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_SET(x)\ argument
660 FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x)
661 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\ argument
662 FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x)
666 0, 1, 32768, 0, 1, 592, 440, 0, 1, 4)
669 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\ argument
670 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x)
671 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_GET(x)\ argument
672 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x)
675 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_SET(x)\ argument
676 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x)
677 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_GET(x)\ argument
678 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x)
681 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_SET(x)\ argument
682 FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x)
683 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\ argument
684 FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x)
688 0, 1, 32768, 0, 1, 592, 580, r, 3, 4)
691 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\ argument
692 FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
693 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\ argument
694 FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
698 0, 1, 34200, g, 134, 16, 0, r, 4, 4)
701 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\ argument
702 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x)
703 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_GET(x)\ argument
704 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x)
707 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_SET(x)\ argument
708 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x)
709 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_GET(x)\ argument
710 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x)
713 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(x)\ argument
714 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x)
715 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_GET(x)\ argument
716 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x)
719 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(x)\ argument
720 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x)
721 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(x)\ argument
722 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x)
725 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(x)\ argument
726 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x)
727 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(x)\ argument
728 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x)
731 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(x)\ argument
732 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x)
733 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_GET(x)\ argument
734 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x)
736 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL GENMASK(2, 1)
737 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(x)\ argument
738 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x)
739 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_GET(x)\ argument
740 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x)
743 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(x)\ argument
744 FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x)
745 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\ argument
746 FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x)
750 0, 1, 0, g, 4096, 4, 0, 0, 1, 4)
754 0, 1, 16384, g, 4096, 4, 0, 0, 1, 4)
758 0, 1, 36408, 0, 1, 16, 0, r, 4, 4)
761 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\ argument
762 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x)
763 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_GET(x)\ argument
764 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x)
767 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_SET(x)\ argument
768 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x)
769 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_GET(x)\ argument
770 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x)
773 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_SET(x)\ argument
774 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x)
775 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_GET(x)\ argument
776 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x)
779 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_SET(x)\ argument
780 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x)
781 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_GET(x)\ argument
782 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x)
785 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_SET(x)\ argument
786 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x)
787 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_GET(x)\ argument
788 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x)
791 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_SET(x)\ argument
792 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x)
793 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_GET(x)\ argument
794 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x)
797 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_SET(x)\ argument
798 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x)
799 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_GET(x)\ argument
800 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x)
803 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\ argument
804 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
805 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\ argument
806 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
809 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\ argument
810 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
811 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\ argument
812 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
815 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_SET(x)\ argument
816 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x)
817 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_GET(x)\ argument
818 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x)
821 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ argument
822 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
823 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\ argument
824 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
827 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\ argument
828 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
829 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\ argument
830 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
833 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\ argument
834 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
835 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\ argument
836 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
839 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\ argument
840 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
841 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\ argument
842 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
845 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\ argument
846 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
847 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\ argument
848 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
851 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_SET(x)\ argument
852 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x)
853 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_GET(x)\ argument
854 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x)
856 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY BIT(1)
857 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_SET(x)\ argument
858 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x)
859 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_GET(x)\ argument
860 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x)
863 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\ argument
864 FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
865 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ argument
866 FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
870 0, 1, 75968, 0, 1, 1160, 1148, 0, 1, 4)
873 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\ argument
874 FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
875 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\ argument
876 FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
880 0, 1, 79048, 0, 1, 8, 0, 0, 1, 4)
883 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ argument
884 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
885 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ argument
886 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
889 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ argument
890 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
891 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ argument
892 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
894 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA BIT(1)
895 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\ argument
896 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
897 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\ argument
898 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
901 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ argument
902 FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
903 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ argument
904 FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
908 0, 1, 79056, 0, 1, 20, 0, 0, 1, 4)
911 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ argument
912 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
913 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\ argument
914 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
917 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\ argument
918 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
919 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\ argument
920 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
922 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA BIT(1)
923 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\ argument
924 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
925 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\ argument
926 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
929 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\ argument
930 FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
931 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ argument
932 FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
936 0, 1, 295468, g, 10, 24, 0, 0, 1, 4)
939 #define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\ argument
940 FIELD_PREP(ANA_AC_SDLB_XLB_START_LBSET_START, x)
941 #define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\ argument
942 FIELD_GET(ANA_AC_SDLB_XLB_START_LBSET_START, x)
946 0, 1, 295468, g, 10, 24, 4, 0, 1, 4)
949 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\ argument
950 FIELD_PREP(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x)
951 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\ argument
952 FIELD_GET(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x)
956 0, 1, 295468, g, 10, 24, 8, 0, 1, 4)
959 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\ argument
960 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x)
961 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_GET(x)\ argument
962 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x)
965 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(x)\ argument
966 FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x)
967 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\ argument
968 FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x)
972 0, 1, 295468, g, 10, 24, 12, 0, 1, 4)
975 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\ argument
976 FIELD_PREP(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x)
977 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\ argument
978 FIELD_GET(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x)
982 0, 1, 295468, g, 10, 24, 16, 0, 1, 4)
985 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\ argument
986 FIELD_PREP(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x)
987 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\ argument
988 FIELD_GET(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x)
992 0, 1, 295468, g, 10, 24, 20, 0, 1, 4)
995 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\ argument
996 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x)
997 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_GET(x)\ argument
998 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x)
1000 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK BIT(1)
1001 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_SET(x)\ argument
1002 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x)
1003 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\ argument
1004 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x)
1007 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\ argument
1008 FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x)
1009 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\ argument
1010 FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x)
1014 0, 1, 0, g, 4616, 64, 0, r, 2, 4)
1017 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\ argument
1018 FIELD_PREP(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x)
1019 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\ argument
1020 FIELD_GET(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x)
1024 0, 1, 0, g, 4616, 64, 8, r, 2, 4)
1027 #define ANA_AC_SDLB_THRES_THRES_SET(x)\ argument
1028 FIELD_PREP(ANA_AC_SDLB_THRES_THRES, x)
1029 #define ANA_AC_SDLB_THRES_THRES_GET(x)\ argument
1030 FIELD_GET(ANA_AC_SDLB_THRES_THRES, x)
1033 #define ANA_AC_SDLB_THRES_THRES_HYS_SET(x)\ argument
1034 FIELD_PREP(ANA_AC_SDLB_THRES_THRES_HYS, x)
1035 #define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\ argument
1036 FIELD_GET(ANA_AC_SDLB_THRES_THRES_HYS, x)
1040 0, 1, 0, g, 4616, 64, 16, 0, 1, 4)
1043 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\ argument
1044 FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x)
1045 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\ argument
1046 FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x)
1049 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\ argument
1050 FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBGRP, x)
1051 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\ argument
1052 FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBGRP, x)
1056 0, 1, 0, g, 4616, 64, 20, r, 2, 4)
1059 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\ argument
1060 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x)
1061 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_GET(x)\ argument
1062 FIELD_GET(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x)
1065 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_SET(x)\ argument
1066 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_MODE, x)
1067 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_GET(x)\ argument
1068 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_MODE, x)
1071 #define ANA_AC_SDLB_INH_CTRL_INH_LB_SET(x)\ argument
1072 FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_LB, x)
1073 #define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\ argument
1074 FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_LB, x)
1078 0, 1, 0, g, 4616, 64, 28, 0, 1, 4)
1081 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\ argument
1082 FIELD_PREP(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x)
1083 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\ argument
1084 FIELD_GET(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x)
1088 0, 1, 0, g, 4616, 64, 32, 0, 1, 4)
1091 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\ argument
1092 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x)
1093 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_GET(x)\ argument
1094 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x)
1097 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_SET(x)\ argument
1098 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x)
1099 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_GET(x)\ argument
1100 FIELD_GET(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x)
1103 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_SET(x)\ argument
1104 FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x)
1105 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\ argument
1106 FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x)
1110 0, 1, 0, g, 4616, 64, 36, 0, 1, 4)
1113 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\ argument
1114 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x)
1115 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_GET(x)\ argument
1116 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x)
1119 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_SET(x)\ argument
1120 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x)
1121 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_GET(x)\ argument
1122 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x)
1125 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_SET(x)\ argument
1126 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x)
1127 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_GET(x)\ argument
1128 FIELD_GET(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x)
1131 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_SET(x)\ argument
1132 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x)
1133 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_GET(x)\ argument
1134 FIELD_GET(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x)
1137 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_SET(x)\ argument
1138 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x)
1139 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_GET(x)\ argument
1140 FIELD_GET(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x)
1143 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_SET(x)\ argument
1144 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x)
1145 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_GET(x)\ argument
1146 FIELD_GET(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x)
1149 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_SET(x)\ argument
1150 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x)
1151 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_GET(x)\ argument
1152 FIELD_GET(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x)
1154 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK GENMASK(1, 0)
1155 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_SET(x)\ argument
1156 FIELD_PREP(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x)
1157 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\ argument
1158 FIELD_GET(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x)
1162 0, 1, 131072, g, 70, 512, 4, 0, 1, 4)
1165 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\ argument
1166 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
1167 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\ argument
1168 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
1170 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS BIT(1)
1171 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\ argument
1172 FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
1173 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\ argument
1174 FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
1177 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\ argument
1178 FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
1179 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\ argument
1180 FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
1184 0, 1, 131072, g, 70, 512, 8, r, 3, 4)
1187 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\ argument
1188 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
1189 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\ argument
1190 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
1193 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\ argument
1194 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
1195 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\ argument
1196 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
1199 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\ argument
1200 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
1201 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\ argument
1202 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
1205 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\ argument
1206 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
1207 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\ argument
1208 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
1211 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\ argument
1212 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
1213 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\ argument
1214 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
1217 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\ argument
1218 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
1219 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\ argument
1220 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
1223 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\ argument
1224 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
1225 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\ argument
1226 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
1229 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\ argument
1230 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
1231 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\ argument
1232 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
1235 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\ argument
1236 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
1237 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\ argument
1238 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
1240 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS BIT(1)
1241 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\ argument
1242 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
1243 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\ argument
1244 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
1247 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\ argument
1248 FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
1249 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\ argument
1250 FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
1254 0, 1, 131072, g, 70, 512, 20, 0, 1, 4)
1256 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1)
1257 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\ argument
1258 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
1259 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\ argument
1260 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
1263 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\ argument
1264 FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
1265 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\ argument
1266 FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
1270 0, 1, 131072, g, 70, 512, 32, 0, 1, 4)
1273 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\ argument
1274 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
1275 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\ argument
1276 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
1279 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\ argument
1280 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
1281 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\ argument
1282 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
1285 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\ argument
1286 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
1287 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\ argument
1288 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
1291 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\ argument
1292 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
1293 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\ argument
1294 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
1297 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\ argument
1298 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
1299 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\ argument
1300 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
1303 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\ argument
1304 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
1305 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\ argument
1306 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
1309 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\ argument
1310 FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
1311 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\ argument
1312 FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
1315 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\ argument
1316 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
1317 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\ argument
1318 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
1321 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\ argument
1322 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x)
1323 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\ argument
1324 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x)
1327 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\ argument
1328 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x)
1329 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\ argument
1330 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x)
1333 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\ argument
1334 FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x)
1335 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\ argument
1336 FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x)
1340 0, 1, 131072, g, 70, 512, 36, 0, 1, 4)
1342 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0)
1343 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\ argument
1344 FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
1345 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\ argument
1346 FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
1350 0, 1, 131072, g, 70, 512, 108, r, 16, 4)
1353 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\ argument
1354 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x)
1355 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_GET(x)\ argument
1356 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x)
1359 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(x)\ argument
1360 FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x)
1361 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\ argument
1362 FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x)
1366 0, 1, 131072, g, 70, 512, 172, 0, 1, 4)
1369 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\ argument
1370 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x)
1371 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_GET(x)\ argument
1372 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x)
1375 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_SET(x)\ argument
1376 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x)
1377 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_GET(x)\ argument
1378 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x)
1381 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(x)\ argument
1382 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x)
1383 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_GET(x)\ argument
1384 FIELD_GET(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x)
1387 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_SET(x)\ argument
1388 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x)
1389 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_GET(x)\ argument
1390 FIELD_GET(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x)
1393 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_SET(x)\ argument
1394 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x)
1395 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_GET(x)\ argument
1396 FIELD_GET(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x)
1399 #define ANA_CL_QOS_CFG_KEEP_ENA_SET(x)\ argument
1400 FIELD_PREP(ANA_CL_QOS_CFG_KEEP_ENA, x)
1401 #define ANA_CL_QOS_CFG_KEEP_ENA_GET(x)\ argument
1402 FIELD_GET(ANA_CL_QOS_CFG_KEEP_ENA, x)
1405 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(x)\ argument
1406 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x)
1407 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_GET(x)\ argument
1408 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x)
1411 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(x)\ argument
1412 FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x)
1413 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_GET(x)\ argument
1414 FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x)
1417 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(x)\ argument
1418 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_DP_ENA, x)
1419 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_GET(x)\ argument
1420 FIELD_GET(ANA_CL_QOS_CFG_DSCP_DP_ENA, x)
1423 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(x)\ argument
1424 FIELD_PREP(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x)
1425 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_GET(x)\ argument
1426 FIELD_GET(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x)
1429 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(x)\ argument
1430 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x)
1431 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_GET(x)\ argument
1432 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x)
1435 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(x)\ argument
1436 FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x)
1437 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\ argument
1438 FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x)
1442 0, 1, 131072, g, 70, 512, 196, 0, 1, 4)
1446 0, 1, 131072, g, 70, 512, 200, r, 6, 4)
1448 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA BIT(1)
1449 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x)\ argument
1450 FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x)
1451 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_GET(x)\ argument
1452 FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x)
1455 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_SET(x)\ argument
1456 FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x)
1457 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x)\ argument
1458 FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x)
1462 0, 1, 131072, g, 70, 512, 224, r, 6, 4)
1465 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x)\ argument
1466 FIELD_PREP(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x)
1467 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_GET(x)\ argument
1468 FIELD_GET(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x)
1471 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(x)\ argument
1472 FIELD_PREP(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x)
1473 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_GET(x)\ argument
1474 FIELD_GET(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x)
1477 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_SET(x)\ argument
1478 FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x)
1479 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_GET(x)\ argument
1480 FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x)
1483 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_SET(x)\ argument
1484 FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x)
1485 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_GET(x)\ argument
1486 FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x)
1489 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_SET(x)\ argument
1490 FIELD_PREP(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x)
1491 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_GET(x)\ argument
1492 FIELD_GET(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x)
1494 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL GENMASK(5, 1)
1495 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(x)\ argument
1496 FIELD_PREP(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x)
1497 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_GET(x)\ argument
1498 FIELD_GET(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x)
1501 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(x)\ argument
1502 FIELD_PREP(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x)
1503 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x)\ argument
1504 FIELD_GET(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x)
1508 0, 1, 166912, 0, 1, 756, 0, r, 3, 4)
1511 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\ argument
1512 FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x)
1513 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\ argument
1514 FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x)
1518 0, 1, 166912, 0, 1, 756, 256, r, 64, 4)
1521 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\ argument
1522 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x)
1523 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_GET(x)\ argument
1524 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x)
1527 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(x)\ argument
1528 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x)
1529 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_GET(x)\ argument
1530 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x)
1533 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_SET(x)\ argument
1534 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x)
1535 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_GET(x)\ argument
1536 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x)
1538 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA BIT(1)
1539 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_SET(x)\ argument
1540 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x)
1541 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_GET(x)\ argument
1542 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x)
1545 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\ argument
1546 FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x)
1547 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\ argument
1548 FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x)
1552 0, 1, 166912, 0, 1, 756, 512, r, 32, 4)
1555 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x)\ argument
1556 FIELD_PREP(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x)
1557 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x)\ argument
1558 FIELD_GET(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x)
1562 0, 1, 566024, 0, 1, 700, 0, 0, 1, 4)
1565 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x)\ argument
1566 FIELD_PREP(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x)
1567 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_GET(x)\ argument
1568 FIELD_GET(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x)
1571 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_SET(x)\ argument
1572 FIELD_PREP(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x)
1573 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_GET(x)\ argument
1574 FIELD_GET(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x)
1577 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_SET(x)\ argument
1578 FIELD_PREP(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x)
1579 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_GET(x)\ argument
1580 FIELD_GET(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x)
1583 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(x)\ argument
1584 FIELD_PREP(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x)
1585 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_GET(x)\ argument
1586 FIELD_GET(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x)
1589 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_SET(x)\ argument
1590 FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_QU, x)
1591 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_GET(x)\ argument
1592 FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_QU, x)
1595 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_SET(x)\ argument
1596 FIELD_PREP(ANA_L2_FWD_CFG_LOOPBACK_ENA, x)
1597 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_GET(x)\ argument
1598 FIELD_GET(ANA_L2_FWD_CFG_LOOPBACK_ENA, x)
1601 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(x)\ argument
1602 FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x)
1603 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_GET(x)\ argument
1604 FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x)
1607 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_SET(x)\ argument
1608 FIELD_PREP(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x)
1609 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_GET(x)\ argument
1610 FIELD_GET(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x)
1613 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_SET(x)\ argument
1614 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x)
1615 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_GET(x)\ argument
1616 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x)
1619 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_SET(x)\ argument
1620 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x)
1621 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_GET(x)\ argument
1622 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x)
1624 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA BIT(1)
1625 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_SET(x)\ argument
1626 FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x)
1627 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_GET(x)\ argument
1628 FIELD_GET(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x)
1631 #define ANA_L2_FWD_CFG_FWD_ENA_SET(x)\ argument
1632 FIELD_PREP(ANA_L2_FWD_CFG_FWD_ENA, x)
1633 #define ANA_L2_FWD_CFG_FWD_ENA_GET(x)\ argument
1634 FIELD_GET(ANA_L2_FWD_CFG_FWD_ENA, x)
1638 0, 1, 566024, 0, 1, 700, 24, 0, 1, 4)
1642 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4)
1646 0, 1, 566024, 0, 1, 700, 32, 0, 1, 4)
1649 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\ argument
1650 FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
1651 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\ argument
1652 FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
1656 0, 1, 566024, 0, 1, 700, 672, r, 3, 4)
1659 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\ argument
1660 FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x)
1661 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\ argument
1662 FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x)
1666 0, 1, 0, g, 4096, 128, 56, 0, 1, 4)
1669 #define ANA_L2_DLB_CFG_DLB_IDX_SET(x)\ argument
1670 FIELD_PREP(ANA_L2_DLB_CFG_DLB_IDX, x)
1671 #define ANA_L2_DLB_CFG_DLB_IDX_GET(x)\ argument
1672 FIELD_GET(ANA_L2_DLB_CFG_DLB_IDX, x)
1676 0, 1, 0, g, 4096, 128, 100, 0, 1, 4)
1679 #define ANA_L2_TSN_CFG_TSN_SFID_SET(x)\ argument
1680 FIELD_PREP(ANA_L2_TSN_CFG_TSN_SFID, x)
1681 #define ANA_L2_TSN_CFG_TSN_SFID_GET(x)\ argument
1682 FIELD_GET(ANA_L2_TSN_CFG_TSN_SFID, x)
1686 0, 1, 493632, 0, 1, 184, 4, 0, 1, 4)
1689 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\ argument
1690 FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
1691 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\ argument
1692 FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
1696 0, 1, 0, g, 5120, 64, 8, 0, 1, 4)
1699 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\ argument
1700 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
1701 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\ argument
1702 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
1705 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\ argument
1706 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x)
1707 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\ argument
1708 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x)
1711 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\ argument
1712 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
1713 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\ argument
1714 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
1717 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\ argument
1718 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
1719 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\ argument
1720 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
1723 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\ argument
1724 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
1725 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\ argument
1726 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
1729 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\ argument
1730 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
1731 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\ argument
1732 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
1735 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\ argument
1736 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
1737 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\ argument
1738 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
1740 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA BIT(1)
1741 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\ argument
1742 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
1743 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\ argument
1744 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
1747 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\ argument
1748 FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
1749 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\ argument
1750 FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
1754 0, 1, 0, g, 5120, 64, 16, 0, 1, 4)
1758 0, 1, 0, g, 5120, 64, 20, 0, 1, 4)
1762 0, 1, 0, g, 5120, 64, 24, 0, 1, 4)
1765 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\ argument
1766 FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
1767 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\ argument
1768 FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
1772 0, 1, 0, g, 65, 512, 0, 0, 1, 4)
1776 0, 1, 0, g, 65, 512, 4, 0, 1, 4)
1780 0, 1, 0, g, 65, 512, 8, 0, 1, 4)
1784 0, 1, 0, g, 65, 512, 12, 0, 1, 4)
1788 0, 1, 0, g, 65, 512, 16, 0, 1, 4)
1792 0, 1, 0, g, 65, 512, 20, 0, 1, 4)
1796 0, 1, 0, g, 65, 512, 24, 0, 1, 4)
1800 0, 1, 0, g, 65, 512, 28, 0, 1, 4)
1804 0, 1, 0, g, 65, 512, 32, 0, 1, 4)
1808 0, 1, 0, g, 65, 512, 36, 0, 1, 4)
1812 0, 1, 0, g, 65, 512, 40, 0, 1, 4)
1816 0, 1, 0, g, 65, 512, 44, 0, 1, 4)
1820 0, 1, 0, g, 65, 512, 48, 0, 1, 4)
1824 0, 1, 0, g, 65, 512, 52, 0, 1, 4)
1828 0, 1, 0, g, 65, 512, 56, 0, 1, 4)
1832 0, 1, 0, g, 65, 512, 60, 0, 1, 4)
1836 0, 1, 0, g, 65, 512, 64, 0, 1, 4)
1840 0, 1, 0, g, 65, 512, 68, 0, 1, 4)
1844 0, 1, 0, g, 65, 512, 72, 0, 1, 4)
1848 0, 1, 0, g, 65, 512, 76, 0, 1, 4)
1852 0, 1, 0, g, 65, 512, 80, 0, 1, 4)
1856 0, 1, 0, g, 65, 512, 84, 0, 1, 4)
1860 0, 1, 0, g, 65, 512, 88, 0, 1, 4)
1864 0, 1, 0, g, 65, 512, 92, 0, 1, 4)
1868 0, 1, 0, g, 65, 512, 96, 0, 1, 4)
1872 0, 1, 0, g, 65, 512, 100, 0, 1, 4)
1876 0, 1, 0, g, 65, 512, 104, 0, 1, 4)
1880 0, 1, 0, g, 65, 512, 108, 0, 1, 4)
1884 0, 1, 0, g, 65, 512, 112, 0, 1, 4)
1888 0, 1, 0, g, 65, 512, 116, 0, 1, 4)
1892 0, 1, 0, g, 65, 512, 120, 0, 1, 4)
1896 0, 1, 0, g, 65, 512, 124, 0, 1, 4)
1900 0, 1, 0, g, 65, 512, 128, 0, 1, 4)
1904 0, 1, 0, g, 65, 512, 132, 0, 1, 4)
1908 0, 1, 0, g, 65, 512, 136, 0, 1, 4)
1912 0, 1, 0, g, 65, 512, 140, 0, 1, 4)
1916 0, 1, 0, g, 65, 512, 144, 0, 1, 4)
1920 0, 1, 0, g, 65, 512, 148, 0, 1, 4)
1924 0, 1, 0, g, 65, 512, 152, 0, 1, 4)
1928 0, 1, 0, g, 65, 512, 156, 0, 1, 4)
1932 0, 1, 0, g, 65, 512, 160, 0, 1, 4)
1936 0, 1, 0, g, 65, 512, 164, 0, 1, 4)
1940 0, 1, 0, g, 65, 512, 168, 0, 1, 4)
1944 0, 1, 0, g, 65, 512, 172, 0, 1, 4)
1948 0, 1, 0, g, 65, 512, 176, 0, 1, 4)
1952 0, 1, 0, g, 65, 512, 180, 0, 1, 4)
1956 0, 1, 0, g, 65, 512, 184, 0, 1, 4)
1960 0, 1, 0, g, 65, 512, 188, 0, 1, 4)
1964 0, 1, 0, g, 65, 512, 192, 0, 1, 4)
1968 0, 1, 0, g, 65, 512, 196, 0, 1, 4)
1972 0, 1, 0, g, 65, 512, 200, 0, 1, 4)
1976 0, 1, 0, g, 65, 512, 204, 0, 1, 4)
1980 0, 1, 0, g, 65, 512, 208, 0, 1, 4)
1984 0, 1, 0, g, 65, 512, 212, 0, 1, 4)
1988 0, 1, 0, g, 65, 512, 216, 0, 1, 4)
1992 0, 1, 0, g, 65, 512, 220, 0, 1, 4)
1996 0, 1, 0, g, 65, 512, 224, 0, 1, 4)
2000 0, 1, 0, g, 65, 512, 228, 0, 1, 4)
2004 0, 1, 0, g, 65, 512, 232, 0, 1, 4)
2008 0, 1, 0, g, 65, 512, 236, 0, 1, 4)
2012 0, 1, 0, g, 65, 512, 240, 0, 1, 4)
2016 0, 1, 0, g, 65, 512, 244, 0, 1, 4)
2020 0, 1, 0, g, 65, 512, 248, 0, 1, 4)
2024 0, 1, 0, g, 65, 512, 252, 0, 1, 4)
2028 0, 1, 0, g, 65, 512, 256, 0, 1, 4)
2032 0, 1, 0, g, 65, 512, 260, 0, 1, 4)
2036 0, 1, 0, g, 65, 512, 264, 0, 1, 4)
2040 0, 1, 0, g, 65, 512, 268, 0, 1, 4)
2044 0, 1, 0, g, 65, 512, 272, 0, 1, 4)
2048 0, 1, 0, g, 65, 512, 276, 0, 1, 4)
2052 0, 1, 0, g, 65, 512, 280, 0, 1, 4)
2056 0, 1, 0, g, 65, 512, 284, 0, 1, 4)
2060 0, 1, 0, g, 65, 512, 288, 0, 1, 4)
2064 0, 1, 0, g, 65, 512, 292, 0, 1, 4)
2068 0, 1, 0, g, 65, 512, 296, 0, 1, 4)
2072 0, 1, 0, g, 65, 512, 300, 0, 1, 4)
2076 0, 1, 0, g, 65, 512, 304, 0, 1, 4)
2080 0, 1, 0, g, 65, 512, 308, 0, 1, 4)
2084 0, 1, 0, g, 65, 512, 312, 0, 1, 4)
2088 0, 1, 0, g, 65, 512, 316, 0, 1, 4)
2092 0, 1, 0, g, 65, 512, 320, 0, 1, 4)
2096 0, 1, 0, g, 65, 512, 324, 0, 1, 4)
2100 0, 1, 0, g, 65, 512, 328, 0, 1, 4)
2104 0, 1, 0, g, 65, 512, 332, 0, 1, 4)
2108 0, 1, 0, g, 65, 512, 336, 0, 1, 4)
2112 0, 1, 0, g, 65, 512, 340, 0, 1, 4)
2116 0, 1, 0, g, 65, 512, 344, 0, 1, 4)
2120 0, 1, 0, g, 65, 512, 348, 0, 1, 4)
2124 0, 1, 0, g, 65, 512, 352, 0, 1, 4)
2128 0, 1, 0, g, 65, 512, 356, 0, 1, 4)
2131 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ argument
2132 FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2133 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ argument
2134 FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2138 0, 1, 0, g, 65, 512, 360, 0, 1, 4)
2141 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ argument
2142 FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2143 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ argument
2144 FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2148 0, 1, 0, g, 65, 512, 364, 0, 1, 4)
2151 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ argument
2152 FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2153 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ argument
2154 FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2158 0, 1, 0, g, 65, 512, 368, 0, 1, 4)
2161 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ argument
2162 FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2163 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ argument
2164 FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2168 0, 1, 0, g, 65, 512, 372, 0, 1, 4)
2171 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ argument
2172 FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2173 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ argument
2174 FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2178 0, 1, 0, g, 65, 512, 376, 0, 1, 4)
2181 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ argument
2182 FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2183 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ argument
2184 FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2188 0, 1, 0, g, 65, 512, 380, 0, 1, 4)
2191 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ argument
2192 FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2193 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ argument
2194 FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2198 0, 1, 0, g, 65, 512, 384, 0, 1, 4)
2201 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ argument
2202 FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2203 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ argument
2204 FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2208 0, 1, 0, g, 65, 512, 388, 0, 1, 4)
2212 0, 1, 33280, 0, 1, 1088, 0, 0, 1, 4)
2215 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\ argument
2216 FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
2217 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\ argument
2218 FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
2222 0, 1, 33280, 0, 1, 1088, 540, r, 67, 4)
2225 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\ argument
2226 FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x)
2227 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\ argument
2228 FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x)
2231 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\ argument
2232 FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
2233 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\ argument
2234 FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
2237 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\ argument
2238 FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
2239 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\ argument
2240 FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
2243 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\ argument
2244 FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
2245 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\ argument
2246 FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
2249 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\ argument
2250 FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
2251 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\ argument
2252 FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
2255 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\ argument
2256 FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x)
2257 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\ argument
2258 FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x)
2261 #define ASM_PORT_CFG_PAD_ENA_SET(x)\ argument
2262 FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x)
2263 #define ASM_PORT_CFG_PAD_ENA_GET(x)\ argument
2264 FIELD_GET(ASM_PORT_CFG_PAD_ENA, x)
2267 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\ argument
2268 FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
2269 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\ argument
2270 FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
2273 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\ argument
2274 FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
2275 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\ argument
2276 FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
2278 #define ASM_PORT_CFG_VSTAX2_AWR_ENA BIT(1)
2279 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\ argument
2280 FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
2281 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\ argument
2282 FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
2285 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\ argument
2286 FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x)
2287 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\ argument
2288 FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x)
2292 0, 1, 34832, 0, 1, 4, 0, 0, 1, 4)
2294 #define ASM_RAM_INIT_RAM_INIT BIT(1)
2295 #define ASM_RAM_INIT_RAM_INIT_SET(x)\ argument
2296 FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x)
2297 #define ASM_RAM_INIT_RAM_INIT_GET(x)\ argument
2298 FIELD_GET(ASM_RAM_INIT_RAM_INIT, x)
2301 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
2302 FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x)
2303 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
2304 FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x)
2308 0, 1, 12, 0, 1, 36, 0, 0, 1, 4)
2311 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\ argument
2312 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
2313 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\ argument
2314 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
2317 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\ argument
2318 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
2319 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\ argument
2320 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
2323 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\ argument
2324 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
2325 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\ argument
2326 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
2329 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\ argument
2330 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
2331 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\ argument
2332 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
2335 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\ argument
2336 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
2337 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\ argument
2338 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
2341 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\ argument
2342 FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
2343 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\ argument
2344 FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
2348 0, 1, 0, 0, 1, 204, 176, 0, 1, 4)
2351 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\ argument
2352 FIELD_PREP(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
2353 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\ argument
2354 FIELD_GET(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
2357 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\ argument
2358 FIELD_PREP(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
2359 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\ argument
2360 FIELD_GET(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
2363 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\ argument
2364 FIELD_PREP(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
2365 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\ argument
2366 FIELD_GET(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
2369 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\ argument
2370 FIELD_PREP(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
2371 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\ argument
2372 FIELD_GET(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
2375 #define CPU_PROC_CTRL_VINITHI_SET(x)\ argument
2376 FIELD_PREP(CPU_PROC_CTRL_VINITHI, x)
2377 #define CPU_PROC_CTRL_VINITHI_GET(x)\ argument
2378 FIELD_GET(CPU_PROC_CTRL_VINITHI, x)
2381 #define CPU_PROC_CTRL_CFGTE_SET(x)\ argument
2382 FIELD_PREP(CPU_PROC_CTRL_CFGTE, x)
2383 #define CPU_PROC_CTRL_CFGTE_GET(x)\ argument
2384 FIELD_GET(CPU_PROC_CTRL_CFGTE, x)
2387 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\ argument
2388 FIELD_PREP(CPU_PROC_CTRL_CP15S_DISABLE, x)
2389 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\ argument
2390 FIELD_GET(CPU_PROC_CTRL_CP15S_DISABLE, x)
2393 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\ argument
2394 FIELD_PREP(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
2395 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\ argument
2396 FIELD_GET(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
2399 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\ argument
2400 FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
2401 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\ argument
2402 FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
2405 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\ argument
2406 FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x)
2407 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\ argument
2408 FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x)
2411 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\ argument
2412 FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x)
2413 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\ argument
2414 FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x)
2416 #define CPU_PROC_CTRL_L2_FLUSH_REQ BIT(1)
2417 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\ argument
2418 FIELD_PREP(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
2419 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\ argument
2420 FIELD_GET(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
2423 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\ argument
2424 FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x)
2425 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ argument
2426 FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x)
2430 t, 12, 0, 0, 1, 60, 0, 0, 1, 4)
2433 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\ argument
2434 FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x)
2435 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\ argument
2436 FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x)
2439 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\ argument
2440 FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x)
2441 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\ argument
2442 FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x)
2446 t, 12, 0, 0, 1, 60, 8, 0, 1, 4)
2449 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ argument
2450 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2451 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ argument
2452 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2455 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ argument
2456 FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
2457 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ argument
2458 FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
2462 t, 12, 0, 0, 1, 60, 12, 0, 1, 4)
2464 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0)
2465 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\ argument
2466 FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
2467 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\ argument
2468 FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
2472 t, 12, 0, 0, 1, 60, 16, r, 3, 4)
2475 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\ argument
2476 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
2477 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\ argument
2478 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
2481 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\ argument
2482 FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
2483 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\ argument
2484 FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
2488 t, 12, 0, 0, 1, 60, 28, 0, 1, 4)
2491 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ argument
2492 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2493 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ argument
2494 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2497 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ argument
2498 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2499 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ argument
2500 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2503 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ argument
2504 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2505 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ argument
2506 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2509 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ argument
2510 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2511 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ argument
2512 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2515 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ argument
2516 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2517 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ argument
2518 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2521 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ argument
2522 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2523 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ argument
2524 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2527 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ argument
2528 FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2529 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ argument
2530 FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2534 t, 12, 0, 0, 1, 60, 48, 0, 1, 4)
2537 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\ argument
2538 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
2539 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\ argument
2540 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
2543 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\ argument
2544 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
2545 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\ argument
2546 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
2549 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\ argument
2550 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
2551 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\ argument
2552 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
2554 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY BIT(1)
2555 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\ argument
2556 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
2557 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\ argument
2558 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
2561 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\ argument
2562 FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
2563 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\ argument
2564 FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
2568 t, 12, 436, 0, 1, 52, 0, 0, 1, 4)
2571 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ argument
2572 FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2573 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ argument
2574 FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2577 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ argument
2578 FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2579 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ argument
2580 FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2583 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ argument
2584 FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2585 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ argument
2586 FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2589 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ argument
2590 FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2591 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ argument
2592 FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2595 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ argument
2596 FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
2597 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ argument
2598 FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
2601 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ argument
2602 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
2603 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ argument
2604 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
2607 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ argument
2608 FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
2609 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ argument
2610 FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
2613 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ argument
2614 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
2615 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ argument
2616 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
2619 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ argument
2620 FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
2621 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ argument
2622 FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
2626 t, 12, 488, 0, 1, 32, 0, 0, 1, 4)
2629 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\ argument
2630 FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
2631 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\ argument
2632 FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
2636 t, 8, 0, 0, 1, 60, 0, 0, 1, 4)
2639 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\ argument
2640 FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x)
2641 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\ argument
2642 FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x)
2645 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\ argument
2646 FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x)
2647 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\ argument
2648 FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x)
2652 t, 8, 0, 0, 1, 60, 8, 0, 1, 4)
2655 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ argument
2656 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2657 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ argument
2658 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2661 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ argument
2662 FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
2663 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ argument
2664 FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
2668 t, 8, 0, 0, 1, 60, 28, 0, 1, 4)
2671 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ argument
2672 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2673 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ argument
2674 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2677 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ argument
2678 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2679 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ argument
2680 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2683 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ argument
2684 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2685 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ argument
2686 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2689 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ argument
2690 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2691 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ argument
2692 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2695 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ argument
2696 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2697 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ argument
2698 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2701 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ argument
2702 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2703 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ argument
2704 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2707 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ argument
2708 FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2709 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ argument
2710 FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2714 t, 8, 436, 0, 1, 52, 0, 0, 1, 4)
2717 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ argument
2718 FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2719 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ argument
2720 FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2723 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ argument
2724 FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2725 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ argument
2726 FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2729 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ argument
2730 FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2731 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ argument
2732 FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2735 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ argument
2736 FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2737 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ argument
2738 FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2741 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ argument
2742 FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
2743 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ argument
2744 FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
2747 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ argument
2748 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
2749 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ argument
2750 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
2753 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ argument
2754 FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
2755 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ argument
2756 FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
2759 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ argument
2760 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
2761 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ argument
2762 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
2765 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ argument
2766 FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
2767 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ argument
2768 FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
2772 t, 8, 488, 0, 1, 32, 0, 0, 1, 4)
2775 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\ argument
2776 FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
2777 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\ argument
2778 FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
2782 t, 8, 488, 0, 1, 32, 4, 0, 1, 4)
2785 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\ argument
2786 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
2787 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\ argument
2788 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
2791 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\ argument
2792 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x)
2793 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\ argument
2794 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x)
2797 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\ argument
2798 FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
2799 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\ argument
2800 FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
2804 t, 65, 0, 0, 1, 36, 0, 0, 1, 4)
2807 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ argument
2808 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2809 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ argument
2810 FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2813 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\ argument
2814 FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
2815 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\ argument
2816 FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
2819 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\ argument
2820 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
2821 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\ argument
2822 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
2825 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\ argument
2826 FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
2827 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\ argument
2828 FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
2831 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ argument
2832 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
2833 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ argument
2834 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
2837 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ argument
2838 FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
2839 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ argument
2840 FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
2843 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ argument
2844 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
2845 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ argument
2846 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
2849 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ argument
2850 FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
2851 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ argument
2852 FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
2856 t, 65, 52, 0, 1, 36, 0, 0, 1, 4)
2859 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\ argument
2860 FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
2861 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\ argument
2862 FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
2865 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\ argument
2866 FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
2867 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\ argument
2868 FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
2872 t, 65, 52, 0, 1, 36, 4, 0, 1, 4)
2875 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\ argument
2876 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
2877 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\ argument
2878 FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
2881 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ argument
2882 FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
2883 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ argument
2884 FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
2887 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\ argument
2888 FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
2889 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\ argument
2890 FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
2894 t, 65, 52, 0, 1, 36, 8, 0, 1, 4)
2897 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ argument
2898 FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
2899 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ argument
2900 FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
2904 t, 65, 52, 0, 1, 36, 12, 0, 1, 4)
2907 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\ argument
2908 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
2909 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\ argument
2910 FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
2913 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\ argument
2914 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
2915 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\ argument
2916 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
2918 #define DEV2G5_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1)
2919 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\ argument
2920 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
2921 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\ argument
2922 FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
2925 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ argument
2926 FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
2927 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ argument
2928 FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
2932 t, 65, 52, 0, 1, 36, 16, 0, 1, 4)
2935 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\ argument
2936 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
2937 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\ argument
2938 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
2941 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\ argument
2942 FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
2943 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\ argument
2944 FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
2948 t, 65, 52, 0, 1, 36, 20, 0, 1, 4)
2951 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\ argument
2952 FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
2953 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\ argument
2954 FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
2958 t, 65, 52, 0, 1, 36, 24, 0, 1, 4)
2961 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\ argument
2962 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
2963 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\ argument
2964 FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
2967 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\ argument
2968 FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
2969 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\ argument
2970 FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
2973 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\ argument
2974 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
2975 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\ argument
2976 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
2979 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\ argument
2980 FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
2981 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\ argument
2982 FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
2986 t, 65, 52, 0, 1, 36, 28, 0, 1, 4)
2989 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\ argument
2990 FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
2991 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\ argument
2992 FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
2995 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\ argument
2996 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x)
2997 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\ argument
2998 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x)
3001 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\ argument
3002 FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
3003 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\ argument
3004 FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
3007 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\ argument
3008 FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
3009 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\ argument
3010 FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
3013 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\ argument
3014 FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
3015 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\ argument
3016 FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
3020 t, 65, 88, 0, 1, 68, 0, 0, 1, 4)
3023 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\ argument
3024 FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
3025 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\ argument
3026 FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
3028 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1)
3029 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\ argument
3030 FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
3031 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\ argument
3032 FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
3035 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\ argument
3036 FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x)
3037 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\ argument
3038 FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x)
3042 t, 65, 88, 0, 1, 68, 4, 0, 1, 4)
3045 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\ argument
3046 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
3047 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\ argument
3048 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
3050 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA BIT(1)
3051 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ argument
3052 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
3053 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ argument
3054 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
3057 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ argument
3058 FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
3059 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ argument
3060 FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
3064 t, 65, 88, 0, 1, 68, 8, 0, 1, 4)
3067 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\ argument
3068 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
3069 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\ argument
3070 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
3073 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\ argument
3074 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
3075 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\ argument
3076 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
3079 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\ argument
3080 FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
3081 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\ argument
3082 FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
3086 t, 65, 88, 0, 1, 68, 12, 0, 1, 4)
3089 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ argument
3090 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
3091 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ argument
3092 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
3095 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ argument
3096 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
3097 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ argument
3098 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
3100 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
3101 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\ argument
3102 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
3103 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\ argument
3104 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
3107 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\ argument
3108 FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
3109 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\ argument
3110 FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
3114 t, 65, 88, 0, 1, 68, 20, 0, 1, 4)
3117 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\ argument
3118 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
3119 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\ argument
3120 FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
3122 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1)
3123 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\ argument
3124 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
3125 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\ argument
3126 FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
3129 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\ argument
3130 FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
3131 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\ argument
3132 FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
3136 t, 65, 88, 0, 1, 68, 32, 0, 1, 4)
3139 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\ argument
3140 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
3141 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\ argument
3142 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
3145 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\ argument
3146 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
3147 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\ argument
3148 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
3151 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\ argument
3152 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
3153 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\ argument
3154 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
3157 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ argument
3158 FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
3159 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ argument
3160 FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
3164 t, 65, 88, 0, 1, 68, 40, 0, 1, 4)
3167 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\ argument
3168 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
3169 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\ argument
3170 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
3173 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\ argument
3174 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
3175 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\ argument
3176 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
3179 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ argument
3180 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
3181 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ argument
3182 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
3185 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ argument
3186 FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
3187 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ argument
3188 FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
3192 t, 65, 88, 0, 1, 68, 48, 0, 1, 4)
3195 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ argument
3196 FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
3197 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ argument
3198 FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
3201 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\ argument
3202 FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
3203 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\ argument
3204 FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
3208 t, 65, 164, 0, 1, 4, 0, 0, 1, 4)
3211 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\ argument
3212 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
3213 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\ argument
3214 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
3217 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\ argument
3218 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x)
3219 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\ argument
3220 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x)
3223 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\ argument
3224 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
3225 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\ argument
3226 FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
3229 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\ argument
3230 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
3231 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\ argument
3232 FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
3235 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\ argument
3236 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
3237 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\ argument
3238 FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
3241 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\ argument
3242 FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
3243 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\ argument
3244 FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
3247 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\ argument
3248 FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
3249 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\ argument
3250 FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
3253 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\ argument
3254 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
3255 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\ argument
3256 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
3259 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\ argument
3260 FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
3261 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\ argument
3262 FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
3265 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\ argument
3266 FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
3267 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\ argument
3268 FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
3271 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\ argument
3272 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
3273 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\ argument
3274 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
3276 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA BIT(1)
3277 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\ argument
3278 FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
3279 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\ argument
3280 FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
3283 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\ argument
3284 FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
3285 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\ argument
3286 FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
3290 t, 65, 168, 0, 1, 4, 0, 0, 1, 4)
3293 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\ argument
3294 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
3295 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\ argument
3296 FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
3299 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\ argument
3300 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
3301 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\ argument
3302 FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
3305 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\ argument
3306 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
3307 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\ argument
3308 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
3311 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\ argument
3312 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
3313 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\ argument
3314 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
3317 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\ argument
3318 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
3319 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\ argument
3320 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
3323 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\ argument
3324 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
3325 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\ argument
3326 FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
3328 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1)
3329 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\ argument
3330 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
3331 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\ argument
3332 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
3335 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\ argument
3336 FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
3337 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\ argument
3338 FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
3342 t, 13, 0, 0, 1, 60, 0, 0, 1, 4)
3345 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\ argument
3346 FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x)
3347 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\ argument
3348 FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x)
3351 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\ argument
3352 FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x)
3353 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\ argument
3354 FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x)
3358 t, 13, 0, 0, 1, 60, 8, 0, 1, 4)
3361 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ argument
3362 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
3363 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\ argument
3364 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
3367 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ argument
3368 FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
3369 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ argument
3370 FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
3374 t, 13, 0, 0, 1, 60, 28, 0, 1, 4)
3377 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ argument
3378 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
3379 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\ argument
3380 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
3383 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\ argument
3384 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
3385 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\ argument
3386 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
3389 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\ argument
3390 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
3391 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\ argument
3392 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
3395 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\ argument
3396 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
3397 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\ argument
3398 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
3401 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\ argument
3402 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
3403 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\ argument
3404 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
3407 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\ argument
3408 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
3409 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\ argument
3410 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
3413 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\ argument
3414 FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
3415 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ argument
3416 FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
3420 t, 13, 60, 0, 1, 312, 0, 0, 1, 4)
3424 t, 13, 60, 0, 1, 312, 4, 0, 1, 4)
3428 t, 13, 60, 0, 1, 312, 8, 0, 1, 4)
3432 t, 13, 60, 0, 1, 312, 12, 0, 1, 4)
3436 t, 13, 60, 0, 1, 312, 16, 0, 1, 4)
3440 t, 13, 60, 0, 1, 312, 20, 0, 1, 4)
3444 t, 13, 60, 0, 1, 312, 24, 0, 1, 4)
3448 t, 13, 60, 0, 1, 312, 28, 0, 1, 4)
3452 t, 13, 60, 0, 1, 312, 32, 0, 1, 4)
3456 t, 13, 60, 0, 1, 312, 36, 0, 1, 4)
3460 t, 13, 60, 0, 1, 312, 40, 0, 1, 4)
3464 t, 13, 60, 0, 1, 312, 44, 0, 1, 4)
3468 t, 13, 60, 0, 1, 312, 48, 0, 1, 4)
3472 t, 13, 60, 0, 1, 312, 52, 0, 1, 4)
3476 t, 13, 60, 0, 1, 312, 56, 0, 1, 4)
3480 t, 13, 60, 0, 1, 312, 60, 0, 1, 4)
3484 t, 13, 60, 0, 1, 312, 64, 0, 1, 4)
3488 t, 13, 60, 0, 1, 312, 68, 0, 1, 4)
3492 t, 13, 60, 0, 1, 312, 72, 0, 1, 4)
3496 t, 13, 60, 0, 1, 312, 76, 0, 1, 4)
3500 t, 13, 60, 0, 1, 312, 80, 0, 1, 4)
3504 t, 13, 60, 0, 1, 312, 84, 0, 1, 4)
3508 t, 13, 60, 0, 1, 312, 88, 0, 1, 4)
3512 t, 13, 60, 0, 1, 312, 92, 0, 1, 4)
3516 t, 13, 60, 0, 1, 312, 96, 0, 1, 4)
3520 t, 13, 60, 0, 1, 312, 100, 0, 1, 4)
3524 t, 13, 60, 0, 1, 312, 104, 0, 1, 4)
3528 t, 13, 60, 0, 1, 312, 108, 0, 1, 4)
3532 t, 13, 60, 0, 1, 312, 112, 0, 1, 4)
3536 t, 13, 60, 0, 1, 312, 116, 0, 1, 4)
3540 t, 13, 60, 0, 1, 312, 120, 0, 1, 4)
3544 t, 13, 60, 0, 1, 312, 124, 0, 1, 4)
3548 t, 13, 60, 0, 1, 312, 128, 0, 1, 4)
3552 t, 13, 60, 0, 1, 312, 132, 0, 1, 4)
3556 t, 13, 60, 0, 1, 312, 136, 0, 1, 4)
3560 t, 13, 60, 0, 1, 312, 140, 0, 1, 4)
3564 t, 13, 60, 0, 1, 312, 144, 0, 1, 4)
3568 t, 13, 60, 0, 1, 312, 148, 0, 1, 4)
3572 t, 13, 60, 0, 1, 312, 152, 0, 1, 4)
3576 t, 13, 60, 0, 1, 312, 156, 0, 1, 4)
3580 t, 13, 60, 0, 1, 312, 160, 0, 1, 4)
3584 t, 13, 60, 0, 1, 312, 164, 0, 1, 4)
3588 t, 13, 60, 0, 1, 312, 168, 0, 1, 4)
3592 t, 13, 60, 0, 1, 312, 172, 0, 1, 4)
3596 t, 13, 60, 0, 1, 312, 176, 0, 1, 4)
3600 t, 13, 60, 0, 1, 312, 180, 0, 1, 4)
3604 t, 13, 60, 0, 1, 312, 184, 0, 1, 4)
3608 t, 13, 60, 0, 1, 312, 188, 0, 1, 4)
3612 t, 13, 60, 0, 1, 312, 192, 0, 1, 4)
3616 t, 13, 60, 0, 1, 312, 196, 0, 1, 4)
3620 t, 13, 60, 0, 1, 312, 200, 0, 1, 4)
3624 t, 13, 60, 0, 1, 312, 204, 0, 1, 4)
3628 t, 13, 60, 0, 1, 312, 208, 0, 1, 4)
3632 t, 13, 60, 0, 1, 312, 212, 0, 1, 4)
3636 t, 13, 60, 0, 1, 312, 216, 0, 1, 4)
3640 t, 13, 60, 0, 1, 312, 220, 0, 1, 4)
3644 t, 13, 60, 0, 1, 312, 224, 0, 1, 4)
3648 t, 13, 60, 0, 1, 312, 228, 0, 1, 4)
3652 t, 13, 60, 0, 1, 312, 232, 0, 1, 4)
3656 t, 13, 60, 0, 1, 312, 236, 0, 1, 4)
3660 t, 13, 60, 0, 1, 312, 240, 0, 1, 4)
3664 t, 13, 60, 0, 1, 312, 244, 0, 1, 4)
3668 t, 13, 60, 0, 1, 312, 248, 0, 1, 4)
3672 t, 13, 60, 0, 1, 312, 252, 0, 1, 4)
3676 t, 13, 60, 0, 1, 312, 256, 0, 1, 4)
3680 t, 13, 60, 0, 1, 312, 260, 0, 1, 4)
3684 t, 13, 60, 0, 1, 312, 264, 0, 1, 4)
3688 t, 13, 60, 0, 1, 312, 268, 0, 1, 4)
3692 t, 13, 60, 0, 1, 312, 272, 0, 1, 4)
3696 t, 13, 60, 0, 1, 312, 276, 0, 1, 4)
3700 t, 13, 60, 0, 1, 312, 280, 0, 1, 4)
3704 t, 13, 60, 0, 1, 312, 284, 0, 1, 4)
3708 t, 13, 60, 0, 1, 312, 288, 0, 1, 4)
3712 t, 13, 60, 0, 1, 312, 292, 0, 1, 4)
3716 t, 13, 60, 0, 1, 312, 296, 0, 1, 4)
3720 t, 13, 60, 0, 1, 312, 300, 0, 1, 4)
3724 t, 13, 60, 0, 1, 312, 304, 0, 1, 4)
3728 t, 13, 60, 0, 1, 312, 308, 0, 1, 4)
3732 t, 13, 372, 0, 1, 64, 0, 0, 1, 4)
3736 t, 13, 372, 0, 1, 64, 4, 0, 1, 4)
3739 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ argument
3740 FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
3741 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ argument
3742 FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
3746 t, 13, 372, 0, 1, 64, 8, 0, 1, 4)
3750 t, 13, 372, 0, 1, 64, 12, 0, 1, 4)
3753 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ argument
3754 FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
3755 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ argument
3756 FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
3760 t, 13, 372, 0, 1, 64, 16, 0, 1, 4)
3764 t, 13, 372, 0, 1, 64, 20, 0, 1, 4)
3767 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ argument
3768 FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
3769 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ argument
3770 FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
3774 t, 13, 372, 0, 1, 64, 24, 0, 1, 4)
3778 t, 13, 372, 0, 1, 64, 28, 0, 1, 4)
3781 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ argument
3782 FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
3783 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ argument
3784 FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
3788 t, 13, 372, 0, 1, 64, 32, 0, 1, 4)
3792 t, 13, 372, 0, 1, 64, 36, 0, 1, 4)
3795 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ argument
3796 FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
3797 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ argument
3798 FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
3802 t, 13, 372, 0, 1, 64, 40, 0, 1, 4)
3806 t, 13, 372, 0, 1, 64, 44, 0, 1, 4)
3809 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ argument
3810 FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
3811 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ argument
3812 FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
3816 t, 13, 372, 0, 1, 64, 48, 0, 1, 4)
3820 t, 13, 372, 0, 1, 64, 52, 0, 1, 4)
3823 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ argument
3824 FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
3825 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ argument
3826 FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
3830 t, 13, 372, 0, 1, 64, 56, 0, 1, 4)
3834 t, 13, 372, 0, 1, 64, 60, 0, 1, 4)
3837 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ argument
3838 FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
3839 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ argument
3840 FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
3844 t, 13, 436, 0, 1, 52, 0, 0, 1, 4)
3847 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ argument
3848 FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
3849 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\ argument
3850 FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
3853 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ argument
3854 FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
3855 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\ argument
3856 FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
3859 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\ argument
3860 FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
3861 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\ argument
3862 FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
3865 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\ argument
3866 FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
3867 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\ argument
3868 FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
3871 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\ argument
3872 FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
3873 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\ argument
3874 FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
3877 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\ argument
3878 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
3879 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\ argument
3880 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
3883 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\ argument
3884 FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
3885 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\ argument
3886 FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
3889 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\ argument
3890 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
3891 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\ argument
3892 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
3895 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\ argument
3896 FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
3897 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ argument
3898 FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
3902 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)
3904 #define DSM_RAM_INIT_RAM_INIT BIT(1)
3905 #define DSM_RAM_INIT_RAM_INIT_SET(x)\ argument
3906 FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x)
3907 #define DSM_RAM_INIT_RAM_INIT_GET(x)\ argument
3908 FIELD_GET(DSM_RAM_INIT_RAM_INIT, x)
3911 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
3912 FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x)
3913 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
3914 FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x)
3918 0, 1, 20, 0, 1, 3528, 0, r, 67, 4)
3921 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\ argument
3922 FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x)
3923 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\ argument
3924 FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x)
3927 #define DSM_BUF_CFG_AGING_ENA_SET(x)\ argument
3928 FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x)
3929 #define DSM_BUF_CFG_AGING_ENA_GET(x)\ argument
3930 FIELD_GET(DSM_BUF_CFG_AGING_ENA, x)
3933 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\ argument
3934 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
3935 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\ argument
3936 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
3939 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\ argument
3940 FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
3941 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\ argument
3942 FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
3946 0, 1, 20, 0, 1, 3528, 1360, r, 67, 4)
3949 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\ argument
3950 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
3951 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\ argument
3952 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
3955 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\ argument
3956 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
3957 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\ argument
3958 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
3960 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM GENMASK(7, 1)
3961 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\ argument
3962 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
3963 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\ argument
3964 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
3967 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\ argument
3968 FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
3969 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\ argument
3970 FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
3974 0, 1, 20, 0, 1, 3528, 1628, r, 67, 4)
3976 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN BIT(1)
3977 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\ argument
3978 FIELD_PREP(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
3979 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\ argument
3980 FIELD_GET(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
3983 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\ argument
3984 FIELD_PREP(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
3985 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\ argument
3986 FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
3990 0, 1, 20, 0, 1, 3528, 2432, r, 67, 4)
3993 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\ argument
3994 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_VAL, x)
3995 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\ argument
3996 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_VAL, x)
3999 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\ argument
4000 FIELD_PREP(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
4001 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\ argument
4002 FIELD_GET(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
4004 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE BIT(1)
4005 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\ argument
4006 FIELD_PREP(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
4007 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\ argument
4008 FIELD_GET(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
4011 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\ argument
4012 FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
4013 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\ argument
4014 FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
4018 0, 1, 20, 0, 1, 3528, 2700, r, 65, 4)
4021 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\ argument
4022 FIELD_PREP(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
4023 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\ argument
4024 FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
4028 0, 1, 20, 0, 1, 3528, 2960, r, 65, 4)
4031 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\ argument
4032 FIELD_PREP(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
4033 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\ argument
4034 FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
4038 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4)
4041 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\ argument
4042 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x)
4043 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\ argument
4044 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x)
4047 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\ argument
4048 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
4049 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\ argument
4050 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
4053 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\ argument
4054 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
4055 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\ argument
4056 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
4058 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL GENMASK(4, 1)
4059 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\ argument
4060 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
4061 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\ argument
4062 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
4065 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\ argument
4066 FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
4067 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ argument
4068 FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
4072 0, 1, 149504, g, 138, 8, 0, r, 2, 4)
4075 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x)\ argument
4076 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x)
4077 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_GET(x)\ argument
4078 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x)
4081 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(x)\ argument
4082 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x)
4083 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_GET(x)\ argument
4084 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x)
4086 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL BIT(1)
4087 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(x)\ argument
4088 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x)
4089 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_GET(x)\ argument
4090 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x)
4093 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(x)\ argument
4094 FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x)
4095 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x)\ argument
4096 FIELD_GET(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x)
4100 0, 1, 122880, g, 2048, 4, 0, 0, 1, 4)
4104 0, 1, 150608, 0, 1, 780, 768, 0, 1, 4)
4107 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\ argument
4108 FIELD_PREP(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
4109 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\ argument
4110 FIELD_GET(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
4113 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\ argument
4114 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
4115 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\ argument
4116 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
4119 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\ argument
4120 FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
4121 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\ argument
4122 FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
4125 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\ argument
4126 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
4127 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\ argument
4128 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
4130 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN BIT(1)
4131 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\ argument
4132 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
4133 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\ argument
4134 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
4137 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\ argument
4138 FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
4139 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\ argument
4140 FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
4144 0, 1, 118696, 0, 1, 8, 0, r, 2, 4)
4147 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ argument
4148 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
4149 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\ argument
4150 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
4153 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\ argument
4154 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
4155 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\ argument
4156 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
4159 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\ argument
4160 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
4161 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\ argument
4162 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
4165 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\ argument
4166 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
4167 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\ argument
4168 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
4171 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\ argument
4172 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
4173 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\ argument
4174 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
4177 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\ argument
4178 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
4179 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\ argument
4180 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
4182 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(1)
4183 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\ argument
4184 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
4185 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\ argument
4186 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
4189 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\ argument
4190 FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
4191 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ argument
4192 FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
4196 0, 1, 118736, 0, 1, 4, 0, 0, 1, 4)
4198 #define EACL_RAM_INIT_RAM_INIT BIT(1)
4199 #define EACL_RAM_INIT_RAM_INIT_SET(x)\ argument
4200 FIELD_PREP(EACL_RAM_INIT_RAM_INIT, x)
4201 #define EACL_RAM_INIT_RAM_INIT_GET(x)\ argument
4202 FIELD_GET(EACL_RAM_INIT_RAM_INIT, x)
4205 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
4206 FIELD_PREP(EACL_RAM_INIT_RAM_CFG_HOOK, x)
4207 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
4208 FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x)
4212 0, 1, 8, 0, 1, 428, 0, 0, 1, 4)
4215 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ argument
4216 FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
4217 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ argument
4218 FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
4222 0, 1, 8, 0, 1, 428, 4, 0, 1, 4)
4225 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ argument
4226 FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x)
4227 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ argument
4228 FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x)
4232 0, 1, 8, 0, 1, 428, 8, 0, 1, 4)
4235 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ argument
4236 FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x)
4237 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ argument
4238 FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x)
4242 0, 1, 8, 0, 1, 428, 52, r, 8, 4)
4246 0, 1, 8, 0, 1, 428, 84, r, 8, 4)
4250 0, 1, 8, 0, 1, 428, 116, r, 8, 4)
4254 0, 1, 8, 0, 1, 428, 148, r, 8, 4)
4258 0, 1, 8, 0, 1, 428, 224, r, 8, 4)
4261 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\ argument
4262 FIELD_PREP(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
4263 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\ argument
4264 FIELD_GET(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
4267 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ argument
4268 FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
4269 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ argument
4270 FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
4273 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ argument
4274 FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x)
4275 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ argument
4276 FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x)
4278 #define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(4, 1)
4279 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ argument
4280 FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
4281 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ argument
4282 FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
4285 #define FDMA_CH_CFG_CH_MEM_SET(x)\ argument
4286 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
4287 #define FDMA_CH_CFG_CH_MEM_GET(x)\ argument
4288 FIELD_GET(FDMA_CH_CFG_CH_MEM, x)
4292 0, 1, 8, 0, 1, 428, 256, r, 8, 4)
4295 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\ argument
4296 FIELD_PREP(FDMA_CH_TRANSLATE_OFFSET, x)
4297 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\ argument
4298 FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x)
4302 0, 1, 8, 0, 1, 428, 364, 0, 1, 4)
4305 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\ argument
4306 FIELD_PREP(FDMA_XTR_CFG_XTR_FIFO_WM, x)
4307 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\ argument
4308 FIELD_GET(FDMA_XTR_CFG_XTR_FIFO_WM, x)
4311 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\ argument
4312 FIELD_PREP(FDMA_XTR_CFG_XTR_ARB_SAT, x)
4313 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\ argument
4314 FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x)
4318 0, 1, 8, 0, 1, 428, 376, r, 2, 4)
4321 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ argument
4322 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x)
4323 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ argument
4324 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x)
4327 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\ argument
4328 FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
4329 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\ argument
4330 FIELD_GET(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
4333 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ argument
4334 FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x)
4335 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ argument
4336 FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x)
4338 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY BIT(1)
4339 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\ argument
4340 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
4341 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\ argument
4342 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
4345 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\ argument
4346 FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_RST, x)
4347 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\ argument
4348 FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x)
4352 0, 1, 8, 0, 1, 428, 384, 0, 1, 4)
4355 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\ argument
4356 FIELD_PREP(FDMA_INTR_DCB_INTR_DCB, x)
4357 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\ argument
4358 FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x)
4362 0, 1, 8, 0, 1, 428, 388, 0, 1, 4)
4365 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\ argument
4366 FIELD_PREP(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
4367 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\ argument
4368 FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
4372 0, 1, 8, 0, 1, 428, 392, 0, 1, 4)
4375 #define FDMA_INTR_DB_INTR_DB_SET(x)\ argument
4376 FIELD_PREP(FDMA_INTR_DB_INTR_DB, x)
4377 #define FDMA_INTR_DB_INTR_DB_GET(x)\ argument
4378 FIELD_GET(FDMA_INTR_DB_INTR_DB, x)
4382 0, 1, 8, 0, 1, 428, 396, 0, 1, 4)
4385 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ argument
4386 FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
4387 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ argument
4388 FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
4392 0, 1, 8, 0, 1, 428, 400, 0, 1, 4)
4395 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\ argument
4396 FIELD_PREP(FDMA_INTR_ERR_INTR_PORT_ERR, x)
4397 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\ argument
4398 FIELD_GET(FDMA_INTR_ERR_INTR_PORT_ERR, x)
4401 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\ argument
4402 FIELD_PREP(FDMA_INTR_ERR_INTR_CH_ERR, x)
4403 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\ argument
4404 FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x)
4408 0, 1, 8, 0, 1, 428, 412, 0, 1, 4)
4411 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\ argument
4412 FIELD_PREP(FDMA_ERRORS_ERR_XTR_WR, x)
4413 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\ argument
4414 FIELD_GET(FDMA_ERRORS_ERR_XTR_WR, x)
4417 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\ argument
4418 FIELD_PREP(FDMA_ERRORS_ERR_XTR_OVF, x)
4419 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\ argument
4420 FIELD_GET(FDMA_ERRORS_ERR_XTR_OVF, x)
4423 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\ argument
4424 FIELD_PREP(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
4425 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\ argument
4426 FIELD_GET(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
4429 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\ argument
4430 FIELD_PREP(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
4431 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\ argument
4432 FIELD_GET(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
4435 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\ argument
4436 FIELD_PREP(FDMA_ERRORS_ERR_DCB_RD, x)
4437 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\ argument
4438 FIELD_GET(FDMA_ERRORS_ERR_DCB_RD, x)
4441 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\ argument
4442 FIELD_PREP(FDMA_ERRORS_ERR_INJ_RD, x)
4443 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\ argument
4444 FIELD_GET(FDMA_ERRORS_ERR_INJ_RD, x)
4447 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\ argument
4448 FIELD_PREP(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
4449 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\ argument
4450 FIELD_GET(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
4453 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\ argument
4454 FIELD_PREP(FDMA_ERRORS_ERR_CH_WR, x)
4455 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\ argument
4456 FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x)
4460 0, 1, 8, 0, 1, 428, 416, 0, 1, 4)
4462 #define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0)
4463 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\ argument
4464 FIELD_PREP(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
4465 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\ argument
4466 FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
4470 0, 1, 8, 0, 1, 428, 424, 0, 1, 4)
4473 #define FDMA_CTRL_NRESET_SET(x)\ argument
4474 FIELD_PREP(FDMA_CTRL_NRESET, x)
4475 #define FDMA_CTRL_NRESET_GET(x)\ argument
4476 FIELD_GET(FDMA_CTRL_NRESET, x)
4480 0, 1, 0, 0, 1, 424, 0, 0, 1, 4)
4483 #define GCB_CHIP_ID_REV_ID_SET(x)\ argument
4484 FIELD_PREP(GCB_CHIP_ID_REV_ID, x)
4485 #define GCB_CHIP_ID_REV_ID_GET(x)\ argument
4486 FIELD_GET(GCB_CHIP_ID_REV_ID, x)
4489 #define GCB_CHIP_ID_PART_ID_SET(x)\ argument
4490 FIELD_PREP(GCB_CHIP_ID_PART_ID, x)
4491 #define GCB_CHIP_ID_PART_ID_GET(x)\ argument
4492 FIELD_GET(GCB_CHIP_ID_PART_ID, x)
4494 #define GCB_CHIP_ID_MFG_ID GENMASK(11, 1)
4495 #define GCB_CHIP_ID_MFG_ID_SET(x)\ argument
4496 FIELD_PREP(GCB_CHIP_ID_MFG_ID, x)
4497 #define GCB_CHIP_ID_MFG_ID_GET(x)\ argument
4498 FIELD_GET(GCB_CHIP_ID_MFG_ID, x)
4501 #define GCB_CHIP_ID_ONE_SET(x)\ argument
4502 FIELD_PREP(GCB_CHIP_ID_ONE, x)
4503 #define GCB_CHIP_ID_ONE_GET(x)\ argument
4504 FIELD_GET(GCB_CHIP_ID_ONE, x)
4508 0, 1, 0, 0, 1, 424, 8, 0, 1, 4)
4511 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\ argument
4512 FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
4513 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\ argument
4514 FIELD_GET(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
4516 #define GCB_SOFT_RST_SOFT_SWC_RST BIT(1)
4517 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\ argument
4518 FIELD_PREP(GCB_SOFT_RST_SOFT_SWC_RST, x)
4519 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\ argument
4520 FIELD_GET(GCB_SOFT_RST_SOFT_SWC_RST, x)
4523 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\ argument
4524 FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x)
4525 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\ argument
4526 FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x)
4530 0, 1, 0, 0, 1, 424, 20, 0, 1, 4)
4532 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA BIT(1)
4533 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\ argument
4534 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
4535 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\ argument
4536 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
4539 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\ argument
4540 FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
4541 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\ argument
4542 FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
4546 0, 1, 0, 0, 1, 424, 24, r, 65, 4)
4549 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\ argument
4550 FIELD_PREP(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
4551 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\ argument
4552 FIELD_GET(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
4556 0, 1, 876, g, 3, 280, 20, 0, 1, 4)
4559 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\ argument
4560 FIELD_PREP(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
4561 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\ argument
4562 FIELD_GET(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
4565 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\ argument
4566 FIELD_PREP(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
4567 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\ argument
4568 FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
4572 0, 1, 0, g, 5040, 32, 0, 0, 1, 4)
4575 #define HSCH_CIR_CFG_CIR_RATE_SET(x)\ argument
4576 FIELD_PREP(HSCH_CIR_CFG_CIR_RATE, x)
4577 #define HSCH_CIR_CFG_CIR_RATE_GET(x)\ argument
4578 FIELD_GET(HSCH_CIR_CFG_CIR_RATE, x)
4581 #define HSCH_CIR_CFG_CIR_BURST_SET(x)\ argument
4582 FIELD_PREP(HSCH_CIR_CFG_CIR_BURST, x)
4583 #define HSCH_CIR_CFG_CIR_BURST_GET(x)\ argument
4584 FIELD_GET(HSCH_CIR_CFG_CIR_BURST, x)
4588 0, 1, 0, g, 5040, 32, 4, 0, 1, 4)
4591 #define HSCH_EIR_CFG_EIR_RATE_SET(x)\ argument
4592 FIELD_PREP(HSCH_EIR_CFG_EIR_RATE, x)
4593 #define HSCH_EIR_CFG_EIR_RATE_GET(x)\ argument
4594 FIELD_GET(HSCH_EIR_CFG_EIR_RATE, x)
4597 #define HSCH_EIR_CFG_EIR_BURST_SET(x)\ argument
4598 FIELD_PREP(HSCH_EIR_CFG_EIR_BURST, x)
4599 #define HSCH_EIR_CFG_EIR_BURST_GET(x)\ argument
4600 FIELD_GET(HSCH_EIR_CFG_EIR_BURST, x)
4604 0, 1, 0, g, 5040, 32, 8, 0, 1, 4)
4607 #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\ argument
4608 FIELD_PREP(HSCH_SE_CFG_SE_DWRR_CNT, x)
4609 #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\ argument
4610 FIELD_GET(HSCH_SE_CFG_SE_DWRR_CNT, x)
4613 #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\ argument
4614 FIELD_PREP(HSCH_SE_CFG_SE_AVB_ENA, x)
4615 #define HSCH_SE_CFG_SE_AVB_ENA_GET(x)\ argument
4616 FIELD_GET(HSCH_SE_CFG_SE_AVB_ENA, x)
4619 #define HSCH_SE_CFG_SE_FRM_MODE_SET(x)\ argument
4620 FIELD_PREP(HSCH_SE_CFG_SE_FRM_MODE, x)
4621 #define HSCH_SE_CFG_SE_FRM_MODE_GET(x)\ argument
4622 FIELD_GET(HSCH_SE_CFG_SE_FRM_MODE, x)
4624 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE GENMASK(2, 1)
4625 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x)\ argument
4626 FIELD_PREP(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x)
4627 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x)\ argument
4628 FIELD_GET(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x)
4631 #define HSCH_SE_CFG_SE_STOP_SET(x)\ argument
4632 FIELD_PREP(HSCH_SE_CFG_SE_STOP, x)
4633 #define HSCH_SE_CFG_SE_STOP_GET(x)\ argument
4634 FIELD_GET(HSCH_SE_CFG_SE_STOP, x)
4638 0, 1, 0, g, 5040, 32, 12, 0, 1, 4)
4641 #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\ argument
4642 FIELD_PREP(HSCH_SE_CONNECT_SE_LEAK_LINK, x)
4643 #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\ argument
4644 FIELD_GET(HSCH_SE_CONNECT_SE_LEAK_LINK, x)
4648 0, 1, 0, g, 5040, 32, 16, 0, 1, 4)
4651 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\ argument
4652 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x)
4653 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\ argument
4654 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x)
4657 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\ argument
4658 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x)
4659 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\ argument
4660 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x)
4663 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\ argument
4664 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x)
4665 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x)\ argument
4666 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x)
4668 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(1)
4669 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x)\ argument
4670 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x)
4671 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x)\ argument
4672 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x)
4675 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x)\ argument
4676 FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x)
4677 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\ argument
4678 FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x)
4682 0, 1, 162816, g, 72, 4, 0, 0, 1, 4)
4685 #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\ argument
4686 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_COST, x)
4687 #define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\ argument
4688 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_COST, x)
4691 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\ argument
4692 FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_BALANCE, x)
4693 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\ argument
4694 FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x)
4698 0, 1, 163104, 0, 1, 648, 284, 0, 1, 4)
4701 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\ argument
4702 FIELD_PREP(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x)
4703 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\ argument
4704 FIELD_GET(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x)
4707 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\ argument
4708 FIELD_PREP(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x)
4709 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x)\ argument
4710 FIELD_GET(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x)
4713 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x)\ argument
4714 FIELD_PREP(HSCH_HSCH_CFG_CFG_CSR_GRANT, x)
4715 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\ argument
4716 FIELD_GET(HSCH_HSCH_CFG_CFG_CSR_GRANT, x)
4720 0, 1, 163104, 0, 1, 648, 640, 0, 1, 4)
4723 #define HSCH_SYS_CLK_PER_100PS_SET(x)\ argument
4724 FIELD_PREP(HSCH_SYS_CLK_PER_100PS, x)
4725 #define HSCH_SYS_CLK_PER_100PS_GET(x)\ argument
4726 FIELD_GET(HSCH_SYS_CLK_PER_100PS, x)
4730 0, 1, 161664, g, 4, 32, 0, r, 4, 4)
4733 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\ argument
4734 FIELD_PREP(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x)
4735 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\ argument
4736 FIELD_GET(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x)
4740 0, 1, 161664, g, 4, 32, 16, r, 4, 4)
4742 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST GENMASK(16, 1)
4743 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\ argument
4744 FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x)
4745 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\ argument
4746 FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x)
4749 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\ argument
4750 FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x)
4751 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\ argument
4752 FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x)
4756 0, 1, 184000, 0, 1, 312, 4, 0, 1, 4)
4759 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\ argument
4760 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
4761 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\ argument
4762 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
4765 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\ argument
4766 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
4767 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\ argument
4768 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
4771 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\ argument
4772 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_DST, x)
4773 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\ argument
4774 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x)
4777 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\ argument
4778 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
4779 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\ argument
4780 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
4783 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\ argument
4784 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
4785 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\ argument
4786 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
4789 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\ argument
4790 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SE, x)
4791 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\ argument
4792 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x)
4795 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\ argument
4796 FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
4797 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\ argument
4798 FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
4802 0, 1, 184000, 0, 1, 312, 8, r, 70, 4)
4805 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\ argument
4806 FIELD_PREP(HSCH_PORT_MODE_DEQUEUE_DIS, x)
4807 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\ argument
4808 FIELD_GET(HSCH_PORT_MODE_DEQUEUE_DIS, x)
4811 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\ argument
4812 FIELD_PREP(HSCH_PORT_MODE_AGE_DIS, x)
4813 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\ argument
4814 FIELD_GET(HSCH_PORT_MODE_AGE_DIS, x)
4817 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\ argument
4818 FIELD_PREP(HSCH_PORT_MODE_TRUNC_ENA, x)
4819 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\ argument
4820 FIELD_GET(HSCH_PORT_MODE_TRUNC_ENA, x)
4822 #define HSCH_PORT_MODE_EIR_REMARK_ENA BIT(1)
4823 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\ argument
4824 FIELD_PREP(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
4825 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\ argument
4826 FIELD_GET(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
4829 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\ argument
4830 FIELD_PREP(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
4831 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\ argument
4832 FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
4836 0, 1, 184000, 0, 1, 312, 288, r, 5, 4)
4839 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\ argument
4840 FIELD_PREP(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
4841 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\ argument
4842 FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
4846 0, 1, 162368, 0, 1, 16, 8, 0, 1, 4)
4849 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\ argument
4850 FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x)
4851 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\ argument
4852 FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x)
4856 0, 1, 162384, 0, 1, 12, 8, 0, 1, 4)
4859 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\ argument
4860 FIELD_PREP(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
4861 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\ argument
4862 FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
4866 0, 1, 0, 0, 1, 72, 0, 0, 1, 4)
4869 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\ argument
4870 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
4871 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\ argument
4872 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
4875 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\ argument
4876 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
4877 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\ argument
4878 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
4881 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\ argument
4882 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
4883 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\ argument
4884 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
4886 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1)
4887 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\ argument
4888 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
4889 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\ argument
4890 FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
4893 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\ argument
4894 FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
4895 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\ argument
4896 FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
4900 0, 1, 0, 0, 1, 72, 4, 0, 1, 4)
4903 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\ argument
4904 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
4905 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\ argument
4906 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
4909 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\ argument
4910 FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
4911 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\ argument
4912 FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
4916 0, 1, 0, 0, 1, 72, 8, 0, 1, 4)
4920 0, 1, 0, 0, 1, 72, 12, 0, 1, 4)
4923 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\ argument
4924 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
4925 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\ argument
4926 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
4929 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\ argument
4930 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
4931 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\ argument
4932 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
4935 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\ argument
4936 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
4937 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\ argument
4938 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
4941 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\ argument
4942 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
4943 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\ argument
4944 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
4947 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\ argument
4948 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
4949 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\ argument
4950 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
4953 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\ argument
4954 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
4955 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\ argument
4956 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
4959 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\ argument
4960 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
4961 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\ argument
4962 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
4965 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\ argument
4966 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
4967 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\ argument
4968 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
4971 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\ argument
4972 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
4973 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\ argument
4974 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
4977 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\ argument
4978 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
4979 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\ argument
4980 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
4983 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\ argument
4984 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
4985 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\ argument
4986 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
4989 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\ argument
4990 FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
4991 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\ argument
4992 FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
4996 0, 1, 0, 0, 1, 72, 16, 0, 1, 4)
4999 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\ argument
5000 FIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
5001 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\ argument
5002 FIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
5006 0, 1, 0, 0, 1, 72, 20, 0, 1, 4)
5009 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\ argument
5010 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
5011 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\ argument
5012 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
5015 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\ argument
5016 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
5017 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\ argument
5018 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
5021 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\ argument
5022 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
5023 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\ argument
5024 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
5027 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\ argument
5028 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
5029 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\ argument
5030 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
5033 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\ argument
5034 FIELD_PREP(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
5035 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\ argument
5036 FIELD_GET(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
5039 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\ argument
5040 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
5041 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\ argument
5042 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
5045 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\ argument
5046 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
5047 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\ argument
5048 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
5051 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\ argument
5052 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
5053 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\ argument
5054 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
5057 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\ argument
5058 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
5059 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\ argument
5060 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
5063 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\ argument
5064 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
5065 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\ argument
5066 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
5069 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\ argument
5070 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
5071 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\ argument
5072 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
5075 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\ argument
5076 FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
5077 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\ argument
5078 FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
5081 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\ argument
5082 FIELD_PREP(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
5083 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\ argument
5084 FIELD_GET(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
5086 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA BIT(1)
5087 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\ argument
5088 FIELD_PREP(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
5089 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\ argument
5090 FIELD_GET(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
5093 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\ argument
5094 FIELD_PREP(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
5095 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\ argument
5096 FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
5100 0, 1, 0, 0, 1, 72, 24, 0, 1, 4)
5103 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\ argument
5104 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
5105 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\ argument
5106 FIELD_GET(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
5109 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\ argument
5110 FIELD_PREP(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
5111 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\ argument
5112 FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
5116 0, 1, 0, 0, 1, 72, 36, r, 4, 4)
5119 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\ argument
5120 FIELD_PREP(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
5121 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\ argument
5122 FIELD_GET(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
5125 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\ argument
5126 FIELD_PREP(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
5127 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\ argument
5128 FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
5132 0, 1, 0, 0, 1, 72, 52, 0, 1, 4)
5135 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\ argument
5136 FIELD_PREP(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
5137 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\ argument
5138 FIELD_GET(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
5141 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\ argument
5142 FIELD_PREP(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
5143 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\ argument
5144 FIELD_GET(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
5147 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\ argument
5148 FIELD_PREP(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
5149 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\ argument
5150 FIELD_GET(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
5153 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\ argument
5154 FIELD_PREP(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
5155 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\ argument
5156 FIELD_GET(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
5159 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\ argument
5160 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
5161 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\ argument
5162 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
5164 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT BIT(1)
5165 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\ argument
5166 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
5167 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\ argument
5168 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
5171 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\ argument
5172 FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
5173 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\ argument
5174 FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
5178 0, 1, 0, 0, 1, 72, 56, 0, 1, 4)
5181 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\ argument
5182 FIELD_PREP(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
5183 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\ argument
5184 FIELD_GET(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
5187 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\ argument
5188 FIELD_PREP(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
5189 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\ argument
5190 FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
5194 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4)
5197 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\ argument
5198 FIELD_PREP(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
5199 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\ argument
5200 FIELD_GET(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
5203 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\ argument
5204 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG, x)
5205 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\ argument
5206 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG, x)
5209 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\ argument
5210 FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
5211 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\ argument
5212 FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
5215 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\ argument
5216 FIELD_PREP(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
5217 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\ argument
5218 FIELD_GET(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
5221 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\ argument
5222 FIELD_PREP(PCEP_RCTRL_2_OUT_0_SNP, x)
5223 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\ argument
5224 FIELD_GET(PCEP_RCTRL_2_OUT_0_SNP, x)
5227 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\ argument
5228 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
5229 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\ argument
5230 FIELD_GET(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
5233 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\ argument
5234 FIELD_PREP(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
5235 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\ argument
5236 FIELD_GET(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
5239 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\ argument
5240 FIELD_PREP(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
5241 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\ argument
5242 FIELD_GET(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
5245 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\ argument
5246 FIELD_PREP(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
5247 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\ argument
5248 FIELD_GET(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
5251 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\ argument
5252 FIELD_PREP(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
5253 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\ argument
5254 FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
5258 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4)
5261 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\ argument
5262 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
5263 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\ argument
5264 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
5267 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\ argument
5268 FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
5269 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\ argument
5270 FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
5274 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4)
5278 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4)
5281 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\ argument
5282 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
5283 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\ argument
5284 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
5287 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\ argument
5288 FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
5289 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\ argument
5290 FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
5294 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4)
5298 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4)
5302 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4)
5304 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0)
5305 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\ argument
5306 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
5307 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\ argument
5308 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
5311 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\ argument
5312 FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
5313 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\ argument
5314 FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
5318 t, 12, 0, 0, 1, 56, 0, 0, 1, 4)
5321 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\ argument
5322 FIELD_PREP(PCS10G_BR_PCS_CFG_PCS_ENA, x)
5323 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\ argument
5324 FIELD_GET(PCS10G_BR_PCS_CFG_PCS_ENA, x)
5327 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ argument
5328 FIELD_PREP(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5329 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ argument
5330 FIELD_GET(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5333 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ argument
5334 FIELD_PREP(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
5335 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ argument
5336 FIELD_GET(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
5339 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ argument
5340 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
5341 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ argument
5342 FIELD_GET(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
5345 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ argument
5346 FIELD_PREP(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
5347 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ argument
5348 FIELD_GET(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
5351 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ argument
5352 FIELD_PREP(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
5353 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ argument
5354 FIELD_GET(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
5357 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ argument
5358 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
5359 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ argument
5360 FIELD_GET(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
5363 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ argument
5364 FIELD_PREP(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5365 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ argument
5366 FIELD_GET(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5369 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ argument
5370 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
5371 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ argument
5372 FIELD_GET(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
5375 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ argument
5376 FIELD_PREP(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5377 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ argument
5378 FIELD_GET(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5381 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ argument
5382 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
5383 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ argument
5384 FIELD_GET(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
5387 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ argument
5388 FIELD_PREP(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5389 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ argument
5390 FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5394 t, 12, 0, 0, 1, 56, 4, 0, 1, 4)
5397 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ argument
5398 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
5399 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ argument
5400 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
5403 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\ argument
5404 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
5405 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\ argument
5406 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
5409 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ argument
5410 FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
5411 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ argument
5412 FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
5416 t, 8, 0, 0, 1, 56, 0, 0, 1, 4)
5419 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\ argument
5420 FIELD_PREP(PCS25G_BR_PCS_CFG_PCS_ENA, x)
5421 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\ argument
5422 FIELD_GET(PCS25G_BR_PCS_CFG_PCS_ENA, x)
5425 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ argument
5426 FIELD_PREP(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5427 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ argument
5428 FIELD_GET(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5431 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ argument
5432 FIELD_PREP(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
5433 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ argument
5434 FIELD_GET(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
5437 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ argument
5438 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
5439 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ argument
5440 FIELD_GET(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
5443 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ argument
5444 FIELD_PREP(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
5445 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ argument
5446 FIELD_GET(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
5449 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ argument
5450 FIELD_PREP(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
5451 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ argument
5452 FIELD_GET(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
5455 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ argument
5456 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
5457 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ argument
5458 FIELD_GET(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
5461 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ argument
5462 FIELD_PREP(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5463 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ argument
5464 FIELD_GET(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5467 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ argument
5468 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
5469 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ argument
5470 FIELD_GET(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
5473 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ argument
5474 FIELD_PREP(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5475 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ argument
5476 FIELD_GET(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5479 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ argument
5480 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
5481 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ argument
5482 FIELD_GET(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
5485 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ argument
5486 FIELD_PREP(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5487 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ argument
5488 FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5492 t, 8, 0, 0, 1, 56, 4, 0, 1, 4)
5495 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ argument
5496 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
5497 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ argument
5498 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
5501 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\ argument
5502 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
5503 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\ argument
5504 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
5507 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ argument
5508 FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
5509 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ argument
5510 FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
5514 t, 13, 0, 0, 1, 56, 0, 0, 1, 4)
5517 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\ argument
5518 FIELD_PREP(PCS5G_BR_PCS_CFG_PCS_ENA, x)
5519 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\ argument
5520 FIELD_GET(PCS5G_BR_PCS_CFG_PCS_ENA, x)
5523 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\ argument
5524 FIELD_PREP(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5525 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\ argument
5526 FIELD_GET(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5529 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\ argument
5530 FIELD_PREP(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
5531 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\ argument
5532 FIELD_GET(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
5535 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\ argument
5536 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
5537 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\ argument
5538 FIELD_GET(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
5541 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\ argument
5542 FIELD_PREP(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
5543 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\ argument
5544 FIELD_GET(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
5547 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\ argument
5548 FIELD_PREP(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
5549 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\ argument
5550 FIELD_GET(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
5553 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\ argument
5554 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
5555 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\ argument
5556 FIELD_GET(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
5559 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\ argument
5560 FIELD_PREP(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5561 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\ argument
5562 FIELD_GET(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5565 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\ argument
5566 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
5567 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\ argument
5568 FIELD_GET(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
5571 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\ argument
5572 FIELD_PREP(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5573 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\ argument
5574 FIELD_GET(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5577 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\ argument
5578 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
5579 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\ argument
5580 FIELD_GET(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
5583 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\ argument
5584 FIELD_PREP(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5585 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ argument
5586 FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5590 t, 13, 0, 0, 1, 56, 4, 0, 1, 4)
5593 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ argument
5594 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
5595 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\ argument
5596 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
5599 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\ argument
5600 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
5601 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\ argument
5602 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
5605 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\ argument
5606 FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
5607 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ argument
5608 FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
5612 0, 1, 0, 0, 1, 24, 0, 0, 1, 4)
5615 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\ argument
5616 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
5617 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\ argument
5618 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
5620 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE BIT(1)
5621 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\ argument
5622 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
5623 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\ argument
5624 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
5627 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\ argument
5628 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
5629 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\ argument
5630 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
5633 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\ argument
5634 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
5635 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\ argument
5636 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
5639 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\ argument
5640 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
5641 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\ argument
5642 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
5645 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\ argument
5646 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
5647 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\ argument
5648 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
5651 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\ argument
5652 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
5653 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\ argument
5654 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
5657 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\ argument
5658 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
5659 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\ argument
5660 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
5663 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\ argument
5664 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
5665 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\ argument
5666 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
5669 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\ argument
5670 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
5671 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\ argument
5672 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
5675 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\ argument
5676 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
5677 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\ argument
5678 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
5681 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\ argument
5682 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
5683 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\ argument
5684 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
5687 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\ argument
5688 FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
5689 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\ argument
5690 FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
5694 0, 1, 0, 0, 1, 24, 4, 0, 1, 4)
5697 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\ argument
5698 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
5699 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\ argument
5700 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
5702 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE BIT(1)
5703 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\ argument
5704 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
5705 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\ argument
5706 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
5709 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\ argument
5710 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
5711 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\ argument
5712 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
5715 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\ argument
5716 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
5717 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\ argument
5718 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
5721 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\ argument
5722 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
5723 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\ argument
5724 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
5727 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\ argument
5728 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
5729 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\ argument
5730 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
5733 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\ argument
5734 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
5735 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\ argument
5736 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
5739 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\ argument
5740 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
5741 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\ argument
5742 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
5745 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\ argument
5746 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
5747 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\ argument
5748 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
5751 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\ argument
5752 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
5753 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\ argument
5754 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
5757 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\ argument
5758 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
5759 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\ argument
5760 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
5763 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\ argument
5764 FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
5765 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\ argument
5766 FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
5770 0, 1, 0, 0, 1, 24, 8, 0, 1, 4)
5773 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\ argument
5774 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
5775 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\ argument
5776 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
5778 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE BIT(1)
5779 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\ argument
5780 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
5781 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\ argument
5782 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
5785 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\ argument
5786 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
5787 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\ argument
5788 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
5791 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\ argument
5792 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
5793 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\ argument
5794 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
5797 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\ argument
5798 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
5799 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\ argument
5800 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
5803 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\ argument
5804 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
5805 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\ argument
5806 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
5809 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\ argument
5810 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
5811 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\ argument
5812 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
5815 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\ argument
5816 FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
5817 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\ argument
5818 FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
5822 0, 1, 0, 0, 1, 24, 12, 0, 1, 4)
5825 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\ argument
5826 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
5827 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\ argument
5828 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
5830 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1 BIT(1)
5831 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\ argument
5832 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
5833 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\ argument
5834 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
5837 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\ argument
5838 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
5839 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\ argument
5840 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
5843 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\ argument
5844 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
5845 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\ argument
5846 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
5849 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\ argument
5850 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
5851 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\ argument
5852 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
5855 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\ argument
5856 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
5857 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\ argument
5858 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
5861 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\ argument
5862 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
5863 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\ argument
5864 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
5867 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\ argument
5868 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
5869 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\ argument
5870 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
5873 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\ argument
5874 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
5875 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\ argument
5876 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
5879 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\ argument
5880 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
5881 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\ argument
5882 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
5885 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\ argument
5886 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
5887 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\ argument
5888 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
5891 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\ argument
5892 FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
5893 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\ argument
5894 FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
5898 0, 1, 72, g, 6, 8, 0, 0, 1, 4)
5901 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\ argument
5902 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
5903 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\ argument
5904 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
5907 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\ argument
5908 FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
5909 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\ argument
5910 FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
5913 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\ argument
5914 FIELD_PREP(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
5915 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\ argument
5916 FIELD_GET(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
5919 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\ argument
5920 FIELD_PREP(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
5921 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\ argument
5922 FIELD_GET(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
5925 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\ argument
5926 FIELD_PREP(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
5927 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\ argument
5928 FIELD_GET(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
5931 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\ argument
5932 FIELD_PREP(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
5933 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\ argument
5934 FIELD_GET(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
5936 #define PORT_CONF_USGMII_CFG_QUAD_MODE BIT(1)
5937 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\ argument
5938 FIELD_PREP(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
5939 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\ argument
5940 FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
5944 0, 1, 320, 0, 1, 16, 0, 0, 1, 4)
5947 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\ argument
5948 FIELD_PREP(PTP_PTP_PIN_INTR_INTR_PTP, x)
5949 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\ argument
5950 FIELD_GET(PTP_PTP_PIN_INTR_INTR_PTP, x)
5954 0, 1, 320, 0, 1, 16, 4, 0, 1, 4)
5957 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\ argument
5958 FIELD_PREP(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
5959 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\ argument
5960 FIELD_GET(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
5964 0, 1, 320, 0, 1, 16, 8, 0, 1, 4)
5967 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\ argument
5968 FIELD_PREP(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
5969 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\ argument
5970 FIELD_GET(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
5974 0, 1, 320, 0, 1, 16, 12, 0, 1, 4)
5977 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\ argument
5978 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x)
5979 #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\ argument
5980 FIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x)
5983 #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\ argument
5984 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_HOLD, x)
5985 #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\ argument
5986 FIELD_GET(PTP_PTP_DOM_CFG_PTP_HOLD, x)
5989 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\ argument
5990 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
5991 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\ argument
5992 FIELD_GET(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
5995 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\ argument
5996 FIELD_PREP(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
5997 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\ argument
5998 FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
6002 0, 1, 336, g, 3, 28, 0, r, 2, 4)
6006 0, 1, 336, g, 3, 28, 8, 0, 1, 4)
6009 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\ argument
6010 FIELD_PREP(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
6011 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\ argument
6012 FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
6016 0, 1, 336, g, 3, 28, 12, 0, 1, 4)
6019 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\ argument
6020 FIELD_PREP(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
6021 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\ argument
6022 FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
6026 0, 1, 336, g, 3, 28, 16, 0, 1, 4)
6030 0, 1, 336, g, 3, 28, 20, 0, 1, 4)
6033 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\ argument
6034 FIELD_PREP(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
6035 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\ argument
6036 FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
6040 0, 1, 336, g, 3, 28, 24, 0, 1, 4)
6044 0, 1, 0, g, 5, 64, 0, 0, 1, 4)
6047 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\ argument
6048 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
6049 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\ argument
6050 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
6053 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\ argument
6054 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
6055 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\ argument
6056 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
6059 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\ argument
6060 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
6061 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\ argument
6062 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
6065 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\ argument
6066 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
6067 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\ argument
6068 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
6071 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\ argument
6072 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
6073 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\ argument
6074 FIELD_GET(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
6077 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\ argument
6078 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
6079 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\ argument
6080 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
6083 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\ argument
6084 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
6085 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\ argument
6086 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
6089 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\ argument
6090 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
6091 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\ argument
6092 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
6095 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\ argument
6096 FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
6097 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\ argument
6098 FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
6102 0, 1, 0, g, 5, 64, 4, 0, 1, 4)
6105 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\ argument
6106 FIELD_PREP(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
6107 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\ argument
6108 FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
6112 0, 1, 0, g, 5, 64, 8, 0, 1, 4)
6116 0, 1, 0, g, 5, 64, 12, 0, 1, 4)
6119 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\ argument
6120 FIELD_PREP(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
6121 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\ argument
6122 FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
6126 0, 1, 0, g, 5, 64, 16, 0, 1, 4)
6129 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\ argument
6130 FIELD_PREP(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
6131 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\ argument
6132 FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
6136 0, 1, 0, g, 5, 64, 20, 0, 1, 4)
6140 0, 1, 0, g, 5, 64, 24, 0, 1, 4)
6143 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\ argument
6144 FIELD_PREP(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
6145 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\ argument
6146 FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
6150 0, 1, 0, g, 5, 64, 28, 0, 1, 4)
6153 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\ argument
6154 FIELD_PREP(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
6155 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\ argument
6156 FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
6160 0, 1, 0, g, 5, 64, 32, 0, 1, 4)
6163 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\ argument
6164 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
6165 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\ argument
6166 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
6169 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\ argument
6170 FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
6171 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\ argument
6172 FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
6176 0, 1, 420, g, 5, 8, 0, 0, 1, 4)
6179 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\ argument
6180 FIELD_PREP(PTP_PHAD_CTRL_PHAD_ENA, x)
6181 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\ argument
6182 FIELD_GET(PTP_PHAD_CTRL_PHAD_ENA, x)
6185 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\ argument
6186 FIELD_PREP(PTP_PHAD_CTRL_PHAD_FAILED, x)
6187 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\ argument
6188 FIELD_GET(PTP_PHAD_CTRL_PHAD_FAILED, x)
6191 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\ argument
6192 FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x)
6193 #define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\ argument
6194 FIELD_GET(PTP_PHAD_CTRL_REDUCED_RES, x)
6197 #define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\ argument
6198 FIELD_PREP(PTP_PHAD_CTRL_LOCK_ACC, x)
6199 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\ argument
6200 FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x)
6204 0, 1, 420, g, 5, 8, 4, 0, 1, 4)
6208 0, 1, 0, 0, 1, 340, 0, r, 70, 4)
6211 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\ argument
6212 FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
6213 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\ argument
6214 FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
6217 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\ argument
6218 FIELD_PREP(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
6219 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\ argument
6220 FIELD_GET(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
6223 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\ argument
6224 FIELD_PREP(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
6225 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\ argument
6226 FIELD_GET(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
6229 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ argument
6230 FIELD_PREP(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
6231 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ argument
6232 FIELD_GET(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
6235 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\ argument
6236 FIELD_PREP(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
6237 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\ argument
6238 FIELD_GET(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
6241 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\ argument
6242 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
6243 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\ argument
6244 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
6247 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\ argument
6248 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
6249 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\ argument
6250 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
6252 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS BIT(1)
6253 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\ argument
6254 FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
6255 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\ argument
6256 FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
6259 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\ argument
6260 FIELD_PREP(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
6261 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\ argument
6262 FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
6266 __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 284, r, 12, 4)
6269 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(x)\ argument
6270 FIELD_PREP(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x)
6271 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_GET(x)\ argument
6272 FIELD_GET(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x)
6276 0, 1, 0, g, 5120, 16, 0, 0, 1, 4)
6279 #define QRES_RES_CFG_WM_HIGH_SET(x)\ argument
6280 FIELD_PREP(QRES_RES_CFG_WM_HIGH, x)
6281 #define QRES_RES_CFG_WM_HIGH_GET(x)\ argument
6282 FIELD_GET(QRES_RES_CFG_WM_HIGH, x)
6286 0, 1, 0, g, 5120, 16, 4, 0, 1, 4)
6289 #define QRES_RES_STAT_MAXUSE_SET(x)\ argument
6290 FIELD_PREP(QRES_RES_STAT_MAXUSE, x)
6291 #define QRES_RES_STAT_MAXUSE_GET(x)\ argument
6292 FIELD_GET(QRES_RES_STAT_MAXUSE, x)
6296 0, 1, 0, g, 5120, 16, 8, 0, 1, 4)
6299 #define QRES_RES_STAT_CUR_INUSE_SET(x)\ argument
6300 FIELD_PREP(QRES_RES_STAT_CUR_INUSE, x)
6301 #define QRES_RES_STAT_CUR_INUSE_GET(x)\ argument
6302 FIELD_GET(QRES_RES_STAT_CUR_INUSE, x)
6306 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
6309 #define QS_XTR_GRP_CFG_MODE_SET(x)\ argument
6310 FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
6311 #define QS_XTR_GRP_CFG_MODE_GET(x)\ argument
6312 FIELD_GET(QS_XTR_GRP_CFG_MODE, x)
6314 #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)
6315 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\ argument
6316 FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
6317 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\ argument
6318 FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
6321 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ argument
6322 FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
6323 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ argument
6324 FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)
6328 0, 1, 0, 0, 1, 36, 8, r, 2, 4)
6332 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)
6334 #define QS_XTR_FLUSH_FLUSH GENMASK(1, 0)
6335 #define QS_XTR_FLUSH_FLUSH_SET(x)\ argument
6336 FIELD_PREP(QS_XTR_FLUSH_FLUSH, x)
6337 #define QS_XTR_FLUSH_FLUSH_GET(x)\ argument
6338 FIELD_GET(QS_XTR_FLUSH_FLUSH, x)
6342 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
6344 #define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0)
6345 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\ argument
6346 FIELD_PREP(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
6347 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\ argument
6348 FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
6352 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
6355 #define QS_INJ_GRP_CFG_MODE_SET(x)\ argument
6356 FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
6357 #define QS_INJ_GRP_CFG_MODE_GET(x)\ argument
6358 FIELD_GET(QS_INJ_GRP_CFG_MODE, x)
6361 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ argument
6362 FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
6363 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ argument
6364 FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)
6368 0, 1, 36, 0, 1, 40, 8, r, 2, 4)
6372 0, 1, 36, 0, 1, 40, 16, r, 2, 4)
6375 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ argument
6376 FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x)
6377 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ argument
6378 FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x)
6381 #define QS_INJ_CTRL_ABORT_SET(x)\ argument
6382 FIELD_PREP(QS_INJ_CTRL_ABORT, x)
6383 #define QS_INJ_CTRL_ABORT_GET(x)\ argument
6384 FIELD_GET(QS_INJ_CTRL_ABORT, x)
6387 #define QS_INJ_CTRL_EOF_SET(x)\ argument
6388 FIELD_PREP(QS_INJ_CTRL_EOF, x)
6389 #define QS_INJ_CTRL_EOF_GET(x)\ argument
6390 FIELD_GET(QS_INJ_CTRL_EOF, x)
6393 #define QS_INJ_CTRL_SOF_SET(x)\ argument
6394 FIELD_PREP(QS_INJ_CTRL_SOF, x)
6395 #define QS_INJ_CTRL_SOF_GET(x)\ argument
6396 FIELD_GET(QS_INJ_CTRL_SOF, x)
6399 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ argument
6400 FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x)
6401 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ argument
6402 FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x)
6406 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)
6409 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ argument
6410 FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x)
6411 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ argument
6412 FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x)
6415 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ argument
6416 FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x)
6417 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ argument
6418 FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x)
6420 #define QS_INJ_STATUS_INJ_IN_PROGRESS GENMASK(1, 0)
6421 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\ argument
6422 FIELD_PREP(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
6423 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\ argument
6424 FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
6428 0, 1, 544, 0, 1, 1128, 0, r, 70, 4)
6431 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\ argument
6432 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_START, x)
6433 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\ argument
6434 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_START, x)
6437 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ argument
6438 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_STOP, x)
6439 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ argument
6440 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_STOP, x)
6442 #define QSYS_PAUSE_CFG_PAUSE_ENA BIT(1)
6443 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ argument
6444 FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_ENA, x)
6445 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ argument
6446 FIELD_GET(QSYS_PAUSE_CFG_PAUSE_ENA, x)
6449 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\ argument
6450 FIELD_PREP(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
6451 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\ argument
6452 FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
6456 0, 1, 544, 0, 1, 1128, 284, r, 70, 4)
6459 #define QSYS_ATOP_ATOP_SET(x)\ argument
6460 FIELD_PREP(QSYS_ATOP_ATOP, x)
6461 #define QSYS_ATOP_ATOP_GET(x)\ argument
6462 FIELD_GET(QSYS_ATOP_ATOP, x)
6466 0, 1, 544, 0, 1, 1128, 564, r, 70, 4)
6468 #define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1)
6469 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\ argument
6470 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
6471 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\ argument
6472 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
6475 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\ argument
6476 FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
6477 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\ argument
6478 FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
6482 0, 1, 544, 0, 1, 1128, 844, 0, 1, 4)
6485 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\ argument
6486 FIELD_PREP(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
6487 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\ argument
6488 FIELD_GET(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
6492 0, 1, 2304, 0, 1, 40, 0, r, 7, 4)
6495 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\ argument
6496 FIELD_PREP(QSYS_CAL_AUTO_CAL_AUTO, x)
6497 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\ argument
6498 FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x)
6502 0, 1, 2304, 0, 1, 40, 36, 0, 1, 4)
6505 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\ argument
6506 FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x)
6507 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\ argument
6508 FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x)
6510 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE GENMASK(10, 1)
6511 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\ argument
6512 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
6513 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\ argument
6514 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
6517 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\ argument
6518 FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
6519 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\ argument
6520 FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
6524 0, 1, 2344, 0, 1, 4, 0, 0, 1, 4)
6526 #define QSYS_RAM_INIT_RAM_INIT BIT(1)
6527 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\ argument
6528 FIELD_PREP(QSYS_RAM_INIT_RAM_INIT, x)
6529 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\ argument
6530 FIELD_GET(QSYS_RAM_INIT_RAM_INIT, x)
6533 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
6534 FIELD_PREP(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
6535 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
6536 FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
6540 0, 1, 387264, 0, 1, 1232, 0, r, 3, 4)
6543 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\ argument
6544 FIELD_PREP(REW_OWN_UPSID_OWN_UPSID, x)
6545 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\ argument
6546 FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x)
6550 0, 1, 387264, 0, 1, 1232, 560, r, 70, 4)
6553 #define REW_RTAG_ETAG_CTRL_IPE_TBL_SET(x)\ argument
6554 FIELD_PREP(REW_RTAG_ETAG_CTRL_IPE_TBL, x)
6555 #define REW_RTAG_ETAG_CTRL_IPE_TBL_GET(x)\ argument
6556 FIELD_GET(REW_RTAG_ETAG_CTRL_IPE_TBL, x)
6558 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA GENMASK(2, 1)
6559 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(x)\ argument
6560 FIELD_PREP(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x)
6561 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_GET(x)\ argument
6562 FIELD_GET(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x)
6565 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_SET(x)\ argument
6566 FIELD_PREP(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x)
6567 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_GET(x)\ argument
6568 FIELD_GET(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x)
6572 0, 1, 387264, 0, 1, 1232, 852, 0, 1, 4)
6575 #define REW_ES0_CTRL_ES0_BY_RT_FWD_SET(x)\ argument
6576 FIELD_PREP(REW_ES0_CTRL_ES0_BY_RT_FWD, x)
6577 #define REW_ES0_CTRL_ES0_BY_RT_FWD_GET(x)\ argument
6578 FIELD_GET(REW_ES0_CTRL_ES0_BY_RT_FWD, x)
6581 #define REW_ES0_CTRL_ES0_BY_RLEG_SET(x)\ argument
6582 FIELD_PREP(REW_ES0_CTRL_ES0_BY_RLEG, x)
6583 #define REW_ES0_CTRL_ES0_BY_RLEG_GET(x)\ argument
6584 FIELD_GET(REW_ES0_CTRL_ES0_BY_RLEG, x)
6587 #define REW_ES0_CTRL_ES0_DPORT_ENA_SET(x)\ argument
6588 FIELD_PREP(REW_ES0_CTRL_ES0_DPORT_ENA, x)
6589 #define REW_ES0_CTRL_ES0_DPORT_ENA_GET(x)\ argument
6590 FIELD_GET(REW_ES0_CTRL_ES0_DPORT_ENA, x)
6593 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_SET(x)\ argument
6594 FIELD_PREP(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x)
6595 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_GET(x)\ argument
6596 FIELD_GET(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x)
6598 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA BIT(1)
6599 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_SET(x)\ argument
6600 FIELD_PREP(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x)
6601 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_GET(x)\ argument
6602 FIELD_GET(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x)
6605 #define REW_ES0_CTRL_ES0_LU_ENA_SET(x)\ argument
6606 FIELD_PREP(REW_ES0_CTRL_ES0_LU_ENA, x)
6607 #define REW_ES0_CTRL_ES0_LU_ENA_GET(x)\ argument
6608 FIELD_GET(REW_ES0_CTRL_ES0_LU_ENA, x)
6612 0, 1, 360448, g, 70, 256, 0, 0, 1, 4)
6615 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\ argument
6616 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_PCP, x)
6617 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\ argument
6618 FIELD_GET(REW_PORT_VLAN_CFG_PORT_PCP, x)
6621 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\ argument
6622 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_DEI, x)
6623 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\ argument
6624 FIELD_GET(REW_PORT_VLAN_CFG_PORT_DEI, x)
6627 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ argument
6628 FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x)
6629 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ argument
6630 FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x)
6634 0, 1, 360448, g, 70, 256, 4, r, 8, 4)
6637 #define REW_PCP_MAP_DE0_PCP_DE0_SET(x)\ argument
6638 FIELD_PREP(REW_PCP_MAP_DE0_PCP_DE0, x)
6639 #define REW_PCP_MAP_DE0_PCP_DE0_GET(x)\ argument
6640 FIELD_GET(REW_PCP_MAP_DE0_PCP_DE0, x)
6644 0, 1, 360448, g, 70, 256, 36, r, 8, 4)
6647 #define REW_PCP_MAP_DE1_PCP_DE1_SET(x)\ argument
6648 FIELD_PREP(REW_PCP_MAP_DE1_PCP_DE1, x)
6649 #define REW_PCP_MAP_DE1_PCP_DE1_GET(x)\ argument
6650 FIELD_GET(REW_PCP_MAP_DE1_PCP_DE1, x)
6654 0, 1, 360448, g, 70, 256, 68, r, 8, 4)
6657 #define REW_DEI_MAP_DE0_DEI_DE0_SET(x)\ argument
6658 FIELD_PREP(REW_DEI_MAP_DE0_DEI_DE0, x)
6659 #define REW_DEI_MAP_DE0_DEI_DE0_GET(x)\ argument
6660 FIELD_GET(REW_DEI_MAP_DE0_DEI_DE0, x)
6664 0, 1, 360448, g, 70, 256, 100, r, 8, 4)
6667 #define REW_DEI_MAP_DE1_DEI_DE1_SET(x)\ argument
6668 FIELD_PREP(REW_DEI_MAP_DE1_DEI_DE1, x)
6669 #define REW_DEI_MAP_DE1_DEI_DE1_GET(x)\ argument
6670 FIELD_GET(REW_DEI_MAP_DE1_DEI_DE1, x)
6674 0, 1, 360448, g, 70, 256, 132, 0, 1, 4)
6677 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\ argument
6678 FIELD_PREP(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
6679 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\ argument
6680 FIELD_GET(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
6683 #define REW_TAG_CTRL_TAG_CFG_SET(x)\ argument
6684 FIELD_PREP(REW_TAG_CTRL_TAG_CFG, x)
6685 #define REW_TAG_CTRL_TAG_CFG_GET(x)\ argument
6686 FIELD_GET(REW_TAG_CTRL_TAG_CFG, x)
6689 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\ argument
6690 FIELD_PREP(REW_TAG_CTRL_TAG_TPID_CFG, x)
6691 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\ argument
6692 FIELD_GET(REW_TAG_CTRL_TAG_TPID_CFG, x)
6695 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\ argument
6696 FIELD_PREP(REW_TAG_CTRL_TAG_VID_CFG, x)
6697 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\ argument
6698 FIELD_GET(REW_TAG_CTRL_TAG_VID_CFG, x)
6701 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\ argument
6702 FIELD_PREP(REW_TAG_CTRL_TAG_PCP_CFG, x)
6703 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\ argument
6704 FIELD_GET(REW_TAG_CTRL_TAG_PCP_CFG, x)
6707 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\ argument
6708 FIELD_PREP(REW_TAG_CTRL_TAG_DEI_CFG, x)
6709 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\ argument
6710 FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x)
6714 0, 1, 360448, g, 70, 256, 136, 0, 1, 4)
6716 #define REW_DSCP_MAP_DSCP_UPDATE_ENA BIT(1)
6717 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x)\ argument
6718 FIELD_PREP(REW_DSCP_MAP_DSCP_UPDATE_ENA, x)
6719 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_GET(x)\ argument
6720 FIELD_GET(REW_DSCP_MAP_DSCP_UPDATE_ENA, x)
6723 #define REW_DSCP_MAP_DSCP_REMAP_ENA_SET(x)\ argument
6724 FIELD_PREP(REW_DSCP_MAP_DSCP_REMAP_ENA, x)
6725 #define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x)\ argument
6726 FIELD_GET(REW_DSCP_MAP_DSCP_REMAP_ENA, x)
6730 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4)
6733 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ argument
6734 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
6735 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\ argument
6736 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
6739 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\ argument
6740 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
6741 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\ argument
6742 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
6745 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\ argument
6746 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
6747 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\ argument
6748 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
6751 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ argument
6752 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
6753 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ argument
6754 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
6756 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1)
6757 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ argument
6758 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
6759 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ argument
6760 FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
6763 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\ argument
6764 FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
6765 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ argument
6766 FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
6770 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4)
6773 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ argument
6774 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
6775 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ argument
6776 FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
6780 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4)
6783 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\ argument
6784 FIELD_PREP(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
6785 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\ argument
6786 FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
6790 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4)
6794 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4)
6798 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4)
6801 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\ argument
6802 FIELD_PREP(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
6803 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\ argument
6804 FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
6808 0, 1, 378368, 0, 1, 40, 24, r, 4, 4)
6811 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\ argument
6812 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
6813 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\ argument
6814 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
6816 #define REW_PTP_GEN_STAMP_FMT_RT_FMT GENMASK(1, 0)
6817 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\ argument
6818 FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
6819 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\ argument
6820 FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
6824 0, 1, 378696, 0, 1, 4, 0, 0, 1, 4)
6826 #define REW_RAM_INIT_RAM_INIT BIT(1)
6827 #define REW_RAM_INIT_RAM_INIT_SET(x)\ argument
6828 FIELD_PREP(REW_RAM_INIT_RAM_INIT, x)
6829 #define REW_RAM_INIT_RAM_INIT_GET(x)\ argument
6830 FIELD_GET(REW_RAM_INIT_RAM_INIT, x)
6833 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
6834 FIELD_PREP(REW_RAM_INIT_RAM_CFG_HOOK, x)
6835 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
6836 FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x)
6840 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
6843 #define VCAP_ES0_CTRL_UPDATE_CMD_SET(x)\ argument
6844 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CMD, x)
6845 #define VCAP_ES0_CTRL_UPDATE_CMD_GET(x)\ argument
6846 FIELD_GET(VCAP_ES0_CTRL_UPDATE_CMD, x)
6849 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_SET(x)\ argument
6850 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x)
6851 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_GET(x)\ argument
6852 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x)
6855 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_SET(x)\ argument
6856 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x)
6857 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_GET(x)\ argument
6858 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x)
6861 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_SET(x)\ argument
6862 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x)
6863 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_GET(x)\ argument
6864 FIELD_GET(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x)
6867 #define VCAP_ES0_CTRL_UPDATE_ADDR_SET(x)\ argument
6868 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ADDR, x)
6869 #define VCAP_ES0_CTRL_UPDATE_ADDR_GET(x)\ argument
6870 FIELD_GET(VCAP_ES0_CTRL_UPDATE_ADDR, x)
6873 #define VCAP_ES0_CTRL_UPDATE_SHOT_SET(x)\ argument
6874 FIELD_PREP(VCAP_ES0_CTRL_UPDATE_SHOT, x)
6875 #define VCAP_ES0_CTRL_UPDATE_SHOT_GET(x)\ argument
6876 FIELD_GET(VCAP_ES0_CTRL_UPDATE_SHOT, x)
6878 #define VCAP_ES0_CTRL_CLEAR_CACHE BIT(1)
6879 #define VCAP_ES0_CTRL_CLEAR_CACHE_SET(x)\ argument
6880 FIELD_PREP(VCAP_ES0_CTRL_CLEAR_CACHE, x)
6881 #define VCAP_ES0_CTRL_CLEAR_CACHE_GET(x)\ argument
6882 FIELD_GET(VCAP_ES0_CTRL_CLEAR_CACHE, x)
6885 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_SET(x)\ argument
6886 FIELD_PREP(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x)
6887 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_GET(x)\ argument
6888 FIELD_GET(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x)
6892 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
6895 #define VCAP_ES0_CFG_MV_NUM_POS_SET(x)\ argument
6896 FIELD_PREP(VCAP_ES0_CFG_MV_NUM_POS, x)
6897 #define VCAP_ES0_CFG_MV_NUM_POS_GET(x)\ argument
6898 FIELD_GET(VCAP_ES0_CFG_MV_NUM_POS, x)
6901 #define VCAP_ES0_CFG_MV_SIZE_SET(x)\ argument
6902 FIELD_PREP(VCAP_ES0_CFG_MV_SIZE, x)
6903 #define VCAP_ES0_CFG_MV_SIZE_GET(x)\ argument
6904 FIELD_GET(VCAP_ES0_CFG_MV_SIZE, x)
6908 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
6912 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
6916 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
6920 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
6924 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
6928 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
6932 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
6935 #define VCAP_ES0_IDX_CORE_IDX_SET(x)\ argument
6936 FIELD_PREP(VCAP_ES0_IDX_CORE_IDX, x)
6937 #define VCAP_ES0_IDX_CORE_IDX_GET(x)\ argument
6938 FIELD_GET(VCAP_ES0_IDX_CORE_IDX, x)
6942 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
6945 #define VCAP_ES0_MAP_CORE_MAP_SET(x)\ argument
6946 FIELD_PREP(VCAP_ES0_MAP_CORE_MAP, x)
6947 #define VCAP_ES0_MAP_CORE_MAP_GET(x)\ argument
6948 FIELD_GET(VCAP_ES0_MAP_CORE_MAP, x)
6952 0, 1, 920, 0, 1, 4, 0, 0, 1, 4)
6955 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ argument
6956 FIELD_PREP(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
6957 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ argument
6958 FIELD_GET(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
6962 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
6966 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
6970 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
6974 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
6978 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
6982 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
6986 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
6990 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
6994 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
6998 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
7002 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
7005 #define VCAP_ES2_CTRL_UPDATE_CMD_SET(x)\ argument
7006 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CMD, x)
7007 #define VCAP_ES2_CTRL_UPDATE_CMD_GET(x)\ argument
7008 FIELD_GET(VCAP_ES2_CTRL_UPDATE_CMD, x)
7011 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_SET(x)\ argument
7012 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x)
7013 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_GET(x)\ argument
7014 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x)
7017 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_SET(x)\ argument
7018 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x)
7019 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_GET(x)\ argument
7020 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x)
7023 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_SET(x)\ argument
7024 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x)
7025 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_GET(x)\ argument
7026 FIELD_GET(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x)
7029 #define VCAP_ES2_CTRL_UPDATE_ADDR_SET(x)\ argument
7030 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ADDR, x)
7031 #define VCAP_ES2_CTRL_UPDATE_ADDR_GET(x)\ argument
7032 FIELD_GET(VCAP_ES2_CTRL_UPDATE_ADDR, x)
7035 #define VCAP_ES2_CTRL_UPDATE_SHOT_SET(x)\ argument
7036 FIELD_PREP(VCAP_ES2_CTRL_UPDATE_SHOT, x)
7037 #define VCAP_ES2_CTRL_UPDATE_SHOT_GET(x)\ argument
7038 FIELD_GET(VCAP_ES2_CTRL_UPDATE_SHOT, x)
7040 #define VCAP_ES2_CTRL_CLEAR_CACHE BIT(1)
7041 #define VCAP_ES2_CTRL_CLEAR_CACHE_SET(x)\ argument
7042 FIELD_PREP(VCAP_ES2_CTRL_CLEAR_CACHE, x)
7043 #define VCAP_ES2_CTRL_CLEAR_CACHE_GET(x)\ argument
7044 FIELD_GET(VCAP_ES2_CTRL_CLEAR_CACHE, x)
7047 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_SET(x)\ argument
7048 FIELD_PREP(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x)
7049 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x)\ argument
7050 FIELD_GET(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x)
7054 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
7057 #define VCAP_ES2_CFG_MV_NUM_POS_SET(x)\ argument
7058 FIELD_PREP(VCAP_ES2_CFG_MV_NUM_POS, x)
7059 #define VCAP_ES2_CFG_MV_NUM_POS_GET(x)\ argument
7060 FIELD_GET(VCAP_ES2_CFG_MV_NUM_POS, x)
7063 #define VCAP_ES2_CFG_MV_SIZE_SET(x)\ argument
7064 FIELD_PREP(VCAP_ES2_CFG_MV_SIZE, x)
7065 #define VCAP_ES2_CFG_MV_SIZE_GET(x)\ argument
7066 FIELD_GET(VCAP_ES2_CFG_MV_SIZE, x)
7070 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
7074 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
7078 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
7082 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
7086 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
7090 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
7094 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
7097 #define VCAP_ES2_IDX_CORE_IDX_SET(x)\ argument
7098 FIELD_PREP(VCAP_ES2_IDX_CORE_IDX, x)
7099 #define VCAP_ES2_IDX_CORE_IDX_GET(x)\ argument
7100 FIELD_GET(VCAP_ES2_IDX_CORE_IDX, x)
7104 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
7107 #define VCAP_ES2_MAP_CORE_MAP_SET(x)\ argument
7108 FIELD_PREP(VCAP_ES2_MAP_CORE_MAP, x)
7109 #define VCAP_ES2_MAP_CORE_MAP_GET(x)\ argument
7110 FIELD_GET(VCAP_ES2_MAP_CORE_MAP, x)
7114 0, 1, 920, 0, 1, 4, 0, 0, 1, 4)
7117 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ argument
7118 FIELD_PREP(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
7119 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ argument
7120 FIELD_GET(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
7124 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
7128 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
7132 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
7136 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
7140 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
7144 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
7148 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
7152 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7156 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
7160 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
7164 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
7167 #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\ argument
7168 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CMD, x)
7169 #define VCAP_SUPER_CTRL_UPDATE_CMD_GET(x)\ argument
7170 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CMD, x)
7173 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_SET(x)\ argument
7174 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x)
7175 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_GET(x)\ argument
7176 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x)
7179 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_SET(x)\ argument
7180 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x)
7181 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_GET(x)\ argument
7182 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x)
7185 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_SET(x)\ argument
7186 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x)
7187 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_GET(x)\ argument
7188 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x)
7191 #define VCAP_SUPER_CTRL_UPDATE_ADDR_SET(x)\ argument
7192 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ADDR, x)
7193 #define VCAP_SUPER_CTRL_UPDATE_ADDR_GET(x)\ argument
7194 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ADDR, x)
7197 #define VCAP_SUPER_CTRL_UPDATE_SHOT_SET(x)\ argument
7198 FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_SHOT, x)
7199 #define VCAP_SUPER_CTRL_UPDATE_SHOT_GET(x)\ argument
7200 FIELD_GET(VCAP_SUPER_CTRL_UPDATE_SHOT, x)
7202 #define VCAP_SUPER_CTRL_CLEAR_CACHE BIT(1)
7203 #define VCAP_SUPER_CTRL_CLEAR_CACHE_SET(x)\ argument
7204 FIELD_PREP(VCAP_SUPER_CTRL_CLEAR_CACHE, x)
7205 #define VCAP_SUPER_CTRL_CLEAR_CACHE_GET(x)\ argument
7206 FIELD_GET(VCAP_SUPER_CTRL_CLEAR_CACHE, x)
7209 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_SET(x)\ argument
7210 FIELD_PREP(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x)
7211 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\ argument
7212 FIELD_GET(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x)
7216 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
7219 #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\ argument
7220 FIELD_PREP(VCAP_SUPER_CFG_MV_NUM_POS, x)
7221 #define VCAP_SUPER_CFG_MV_NUM_POS_GET(x)\ argument
7222 FIELD_GET(VCAP_SUPER_CFG_MV_NUM_POS, x)
7225 #define VCAP_SUPER_CFG_MV_SIZE_SET(x)\ argument
7226 FIELD_PREP(VCAP_SUPER_CFG_MV_SIZE, x)
7227 #define VCAP_SUPER_CFG_MV_SIZE_GET(x)\ argument
7228 FIELD_GET(VCAP_SUPER_CFG_MV_SIZE, x)
7232 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
7236 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
7240 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
7244 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
7248 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
7252 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
7256 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
7259 #define VCAP_SUPER_IDX_CORE_IDX_SET(x)\ argument
7260 FIELD_PREP(VCAP_SUPER_IDX_CORE_IDX, x)
7261 #define VCAP_SUPER_IDX_CORE_IDX_GET(x)\ argument
7262 FIELD_GET(VCAP_SUPER_IDX_CORE_IDX, x)
7266 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
7269 #define VCAP_SUPER_MAP_CORE_MAP_SET(x)\ argument
7270 FIELD_PREP(VCAP_SUPER_MAP_CORE_MAP, x)
7271 #define VCAP_SUPER_MAP_CORE_MAP_GET(x)\ argument
7272 FIELD_GET(VCAP_SUPER_MAP_CORE_MAP, x)
7276 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
7280 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
7284 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
7288 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
7292 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
7296 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
7300 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
7304 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7308 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
7312 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
7316 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4)
7318 #define VCAP_SUPER_RAM_INIT_RAM_INIT BIT(1)
7319 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\ argument
7320 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
7321 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\ argument
7322 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
7325 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
7326 FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
7327 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
7328 FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
7332 0, 1, 279176, 0, 1, 4, 0, 0, 1, 4)
7334 #define VOP_RAM_INIT_RAM_INIT BIT(1)
7335 #define VOP_RAM_INIT_RAM_INIT_SET(x)\ argument
7336 FIELD_PREP(VOP_RAM_INIT_RAM_INIT, x)
7337 #define VOP_RAM_INIT_RAM_INIT_GET(x)\ argument
7338 FIELD_GET(VOP_RAM_INIT_RAM_INIT, x)
7341 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\ argument
7342 FIELD_PREP(VOP_RAM_INIT_RAM_CFG_HOOK, x)
7343 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\ argument
7344 FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x)
7348 0, 1, 6768, 0, 1, 872, 860, 0, 1, 4)
7351 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\ argument
7352 FIELD_PREP(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
7353 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\ argument
7354 FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
7357 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\ argument
7358 FIELD_PREP(XQS_STAT_CFG_STAT_VIEW, x)
7359 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\ argument
7360 FIELD_GET(XQS_STAT_CFG_STAT_VIEW, x)
7363 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\ argument
7364 FIELD_PREP(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
7365 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\ argument
7366 FIELD_GET(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
7369 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\ argument
7370 FIELD_PREP(XQS_STAT_CFG_STAT_WRAP_DIS, x)
7371 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\ argument
7372 FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x)
7376 0, 1, 7936, g, 4, 48, 0, 0, 1, 4)
7379 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\ argument
7380 FIELD_PREP(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
7381 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\ argument
7382 FIELD_GET(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
7386 0, 1, 7936, g, 4, 48, 4, 0, 1, 4)
7389 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\ argument
7390 FIELD_PREP(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
7391 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\ argument
7392 FIELD_GET(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
7396 0, 1, 7936, g, 4, 48, 8, 0, 1, 4)
7399 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\ argument
7400 FIELD_PREP(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
7401 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\ argument
7402 FIELD_GET(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
7406 0, 1, 7936, g, 4, 48, 12, 0, 1, 4)
7409 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\ argument
7410 FIELD_PREP(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
7411 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\ argument
7412 FIELD_GET(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
7416 0, 1, 0, g, 1024, 4, 0, 0, 1, 4)