65 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\  argument
67 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\  argument
71 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
73 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
81 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\  argument
83 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\  argument
91 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x)\  argument
93 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x)\  argument
97 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x)\  argument
99 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x)\  argument
103 #define ANA_AC_PROBE_CFG_PROBE_VID_SET(x)\  argument
105 #define ANA_AC_PROBE_CFG_PROBE_VID_GET(x)\  argument
109 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x)\  argument
111 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x)\  argument
115 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x)\  argument
117 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x)\  argument
121 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x)\  argument
123 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x)\  argument
139 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x)\  argument
141 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x)\  argument
157 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\  argument
159 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\  argument
175 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\  argument
177 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\  argument
185 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\  argument
187 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\  argument
191 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\  argument
193 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\  argument
197 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\  argument
199 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\  argument
207 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\  argument
209 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\  argument
213 #define ANA_AC_TSN_SF_PORT_NUM_SET(x)\  argument
215 #define ANA_AC_TSN_SF_PORT_NUM_GET(x)\  argument
223 #define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\  argument
225 #define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\  argument
229 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\  argument
231 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_GET(x)\  argument
235 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_SET(x)\  argument
237 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_GET(x)\  argument
241 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_SET(x)\  argument
243 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x)\  argument
251 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\  argument
253 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_GET(x)\  argument
257 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_SET(x)\  argument
259 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\  argument
263 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\  argument
265 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\  argument
269 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\  argument
271 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\  argument
279 #define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\  argument
281 #define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\  argument
285 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\  argument
287 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\  argument
295 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\  argument
297 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_GET(x)\  argument
301 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(x)\  argument
303 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\  argument
319 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\  argument
321 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_GET(x)\  argument
325 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_SET(x)\  argument
327 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_GET(x)\  argument
331 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_SET(x)\  argument
333 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_GET(x)\  argument
337 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_SET(x)\  argument
339 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_GET(x)\  argument
343 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_SET(x)\  argument
345 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_GET(x)\  argument
349 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_SET(x)\  argument
351 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_GET(x)\  argument
355 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_SET(x)\  argument
357 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_GET(x)\  argument
361 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_SET(x)\  argument
363 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_GET(x)\  argument
367 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_SET(x)\  argument
369 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\  argument
385 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\  argument
387 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_GET(x)\  argument
391 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(x)\  argument
393 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\  argument
417 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\  argument
419 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_GET(x)\  argument
423 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_SET(x)\  argument
425 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_GET(x)\  argument
429 #define ANA_AC_SG_STATUS_REG_3_IPS_SET(x)\  argument
431 #define ANA_AC_SG_STATUS_REG_3_IPS_GET(x)\  argument
435 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_SET(x)\  argument
437 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_GET(x)\  argument
441 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_SET(x)\  argument
443 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\  argument
455 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\  argument
457 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\  argument
465 #define ANA_AC_STAT_RESET_RESET_SET(x)\  argument
467 #define ANA_AC_STAT_RESET_RESET_GET(x)\  argument
475 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\  argument
477 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\  argument
481 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\  argument
483 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\  argument
487 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\  argument
489 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\  argument
501 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x)\  argument
503 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x)\  argument
511 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x)\  argument
513 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x)\  argument
521 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x)\  argument
523 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x)\  argument
531 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\  argument
533 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_GET(x)\  argument
537 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_SET(x)\  argument
539 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_GET(x)\  argument
543 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_SET(x)\  argument
545 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_GET(x)\  argument
549 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_SET(x)\  argument
551 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_GET(x)\  argument
555 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_SET(x)\  argument
557 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_GET(x)\  argument
561 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_SET(x)\  argument
563 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_GET(x)\  argument
567 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_SET(x)\  argument
569 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_GET(x)\  argument
573 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_SET(x)\  argument
575 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_GET(x)\  argument
579 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_SET(x)\  argument
581 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_GET(x)\  argument
585 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_SET(x)\  argument
587 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_GET(x)\  argument
591 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_SET(x)\  argument
593 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_GET(x)\  argument
597 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_SET(x)\  argument
599 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_GET(x)\  argument
603 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_SET(x)\  argument
605 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_GET(x)\  argument
609 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(x)\  argument
611 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\  argument
619 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\  argument
621 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_GET(x)\  argument
625 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_SET(x)\  argument
627 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_GET(x)\  argument
631 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_SET(x)\  argument
633 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_GET(x)\  argument
637 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_SET(x)\  argument
639 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_GET(x)\  argument
643 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_SET(x)\  argument
645 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\  argument
653 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\  argument
655 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_GET(x)\  argument
659 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_SET(x)\  argument
661 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\  argument
669 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\  argument
671 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_GET(x)\  argument
675 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_SET(x)\  argument
677 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_GET(x)\  argument
681 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_SET(x)\  argument
683 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\  argument
691 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\  argument
693 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\  argument
701 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\  argument
703 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_GET(x)\  argument
707 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_SET(x)\  argument
709 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_GET(x)\  argument
713 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(x)\  argument
715 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_GET(x)\  argument
719 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(x)\  argument
721 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(x)\  argument
725 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(x)\  argument
727 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(x)\  argument
731 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(x)\  argument
733 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_GET(x)\  argument
737 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(x)\  argument
739 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_GET(x)\  argument
743 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(x)\  argument
745 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\  argument
761 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\  argument
763 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_GET(x)\  argument
767 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_SET(x)\  argument
769 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_GET(x)\  argument
773 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_SET(x)\  argument
775 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_GET(x)\  argument
779 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_SET(x)\  argument
781 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_GET(x)\  argument
785 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_SET(x)\  argument
787 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_GET(x)\  argument
791 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_SET(x)\  argument
793 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_GET(x)\  argument
797 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_SET(x)\  argument
799 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_GET(x)\  argument
803 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\  argument
805 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\  argument
809 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\  argument
811 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\  argument
815 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_SET(x)\  argument
817 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_GET(x)\  argument
821 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\  argument
823 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\  argument
827 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\  argument
829 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\  argument
833 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\  argument
835 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\  argument
839 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\  argument
841 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\  argument
845 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\  argument
847 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\  argument
851 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_SET(x)\  argument
853 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_GET(x)\  argument
857 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_SET(x)\  argument
859 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_GET(x)\  argument
863 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\  argument
865 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\  argument
873 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\  argument
875 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\  argument
883 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\  argument
885 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\  argument
889 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\  argument
891 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\  argument
895 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\  argument
897 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\  argument
901 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\  argument
903 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\  argument
911 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\  argument
913 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\  argument
917 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\  argument
919 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\  argument
923 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\  argument
925 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\  argument
929 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\  argument
931 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\  argument
939 #define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\  argument
941 #define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\  argument
949 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\  argument
951 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\  argument
959 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\  argument
961 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_GET(x)\  argument
965 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(x)\  argument
967 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\  argument
975 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\  argument
977 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\  argument
985 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\  argument
987 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\  argument
995 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\  argument
997 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_GET(x)\  argument
1001 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_SET(x)\  argument
1003 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\  argument
1007 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\  argument
1009 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\  argument
1017 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\  argument
1019 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\  argument
1027 #define ANA_AC_SDLB_THRES_THRES_SET(x)\  argument
1029 #define ANA_AC_SDLB_THRES_THRES_GET(x)\  argument
1033 #define ANA_AC_SDLB_THRES_THRES_HYS_SET(x)\  argument
1035 #define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\  argument
1043 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\  argument
1045 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\  argument
1049 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\  argument
1051 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\  argument
1059 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\  argument
1061 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_GET(x)\  argument
1065 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_SET(x)\  argument
1067 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_GET(x)\  argument
1071 #define ANA_AC_SDLB_INH_CTRL_INH_LB_SET(x)\  argument
1073 #define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\  argument
1081 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\  argument
1083 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\  argument
1091 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\  argument
1093 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_GET(x)\  argument
1097 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_SET(x)\  argument
1099 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_GET(x)\  argument
1103 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_SET(x)\  argument
1105 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\  argument
1113 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\  argument
1115 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_GET(x)\  argument
1119 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_SET(x)\  argument
1121 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_GET(x)\  argument
1125 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_SET(x)\  argument
1127 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_GET(x)\  argument
1131 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_SET(x)\  argument
1133 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_GET(x)\  argument
1137 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_SET(x)\  argument
1139 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_GET(x)\  argument
1143 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_SET(x)\  argument
1145 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_GET(x)\  argument
1149 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_SET(x)\  argument
1151 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_GET(x)\  argument
1155 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_SET(x)\  argument
1157 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\  argument
1165 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\  argument
1167 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\  argument
1171 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\  argument
1173 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\  argument
1177 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\  argument
1179 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\  argument
1187 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\  argument
1189 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\  argument
1193 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\  argument
1195 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\  argument
1199 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\  argument
1201 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\  argument
1205 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\  argument
1207 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\  argument
1211 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\  argument
1213 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\  argument
1217 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\  argument
1219 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\  argument
1223 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\  argument
1225 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\  argument
1229 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\  argument
1231 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\  argument
1235 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\  argument
1237 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\  argument
1241 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\  argument
1243 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\  argument
1247 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\  argument
1249 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\  argument
1257 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\  argument
1259 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\  argument
1263 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\  argument
1265 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\  argument
1273 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\  argument
1275 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\  argument
1279 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\  argument
1281 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\  argument
1285 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\  argument
1287 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\  argument
1291 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\  argument
1293 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\  argument
1297 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\  argument
1299 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\  argument
1303 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\  argument
1305 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\  argument
1309 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\  argument
1311 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\  argument
1315 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\  argument
1317 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\  argument
1321 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\  argument
1323 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\  argument
1327 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\  argument
1329 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\  argument
1333 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\  argument
1335 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\  argument
1343 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\  argument
1345 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\  argument
1353 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\  argument
1355 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_GET(x)\  argument
1359 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(x)\  argument
1361 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\  argument
1369 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\  argument
1371 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_GET(x)\  argument
1375 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_SET(x)\  argument
1377 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_GET(x)\  argument
1381 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(x)\  argument
1383 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_GET(x)\  argument
1387 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_SET(x)\  argument
1389 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_GET(x)\  argument
1393 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_SET(x)\  argument
1395 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_GET(x)\  argument
1399 #define ANA_CL_QOS_CFG_KEEP_ENA_SET(x)\  argument
1401 #define ANA_CL_QOS_CFG_KEEP_ENA_GET(x)\  argument
1405 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(x)\  argument
1407 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_GET(x)\  argument
1411 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(x)\  argument
1413 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_GET(x)\  argument
1417 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(x)\  argument
1419 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_GET(x)\  argument
1423 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(x)\  argument
1425 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_GET(x)\  argument
1429 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(x)\  argument
1431 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_GET(x)\  argument
1435 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(x)\  argument
1437 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\  argument
1449 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x)\  argument
1451 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_GET(x)\  argument
1455 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_SET(x)\  argument
1457 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x)\  argument
1465 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x)\  argument
1467 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_GET(x)\  argument
1471 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(x)\  argument
1473 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_GET(x)\  argument
1477 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_SET(x)\  argument
1479 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_GET(x)\  argument
1483 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_SET(x)\  argument
1485 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_GET(x)\  argument
1489 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_SET(x)\  argument
1491 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_GET(x)\  argument
1495 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(x)\  argument
1497 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_GET(x)\  argument
1501 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(x)\  argument
1503 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x)\  argument
1511 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\  argument
1513 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\  argument
1521 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\  argument
1523 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_GET(x)\  argument
1527 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(x)\  argument
1529 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_GET(x)\  argument
1533 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_SET(x)\  argument
1535 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_GET(x)\  argument
1539 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_SET(x)\  argument
1541 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_GET(x)\  argument
1545 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\  argument
1547 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\  argument
1555 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x)\  argument
1557 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x)\  argument
1565 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x)\  argument
1567 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_GET(x)\  argument
1571 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_SET(x)\  argument
1573 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_GET(x)\  argument
1577 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_SET(x)\  argument
1579 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_GET(x)\  argument
1583 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(x)\  argument
1585 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_GET(x)\  argument
1589 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_SET(x)\  argument
1591 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_GET(x)\  argument
1595 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_SET(x)\  argument
1597 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_GET(x)\  argument
1601 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(x)\  argument
1603 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_GET(x)\  argument
1607 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_SET(x)\  argument
1609 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_GET(x)\  argument
1613 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_SET(x)\  argument
1615 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_GET(x)\  argument
1619 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_SET(x)\  argument
1621 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_GET(x)\  argument
1625 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_SET(x)\  argument
1627 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_GET(x)\  argument
1631 #define ANA_L2_FWD_CFG_FWD_ENA_SET(x)\  argument
1633 #define ANA_L2_FWD_CFG_FWD_ENA_GET(x)\  argument
1649 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\  argument
1651 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\  argument
1659 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\  argument
1661 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\  argument
1669 #define ANA_L2_DLB_CFG_DLB_IDX_SET(x)\  argument
1671 #define ANA_L2_DLB_CFG_DLB_IDX_GET(x)\  argument
1679 #define ANA_L2_TSN_CFG_TSN_SFID_SET(x)\  argument
1681 #define ANA_L2_TSN_CFG_TSN_SFID_GET(x)\  argument
1689 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\  argument
1691 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\  argument
1699 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\  argument
1701 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\  argument
1705 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\  argument
1707 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\  argument
1711 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\  argument
1713 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\  argument
1717 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\  argument
1719 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\  argument
1723 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\  argument
1725 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\  argument
1729 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\  argument
1731 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\  argument
1735 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\  argument
1737 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\  argument
1741 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\  argument
1743 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\  argument
1747 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\  argument
1749 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\  argument
1765 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\  argument
1767 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\  argument
2131 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\  argument
2133 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\  argument
2141 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
2143 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
2151 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
2153 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
2161 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
2163 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
2171 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
2173 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
2181 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\  argument
2183 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\  argument
2191 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
2193 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
2201 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
2203 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
2215 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\  argument
2217 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\  argument
2225 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\  argument
2227 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\  argument
2231 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\  argument
2233 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\  argument
2237 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\  argument
2239 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\  argument
2243 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\  argument
2245 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\  argument
2249 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\  argument
2251 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\  argument
2255 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\  argument
2257 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\  argument
2261 #define ASM_PORT_CFG_PAD_ENA_SET(x)\  argument
2263 #define ASM_PORT_CFG_PAD_ENA_GET(x)\  argument
2267 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\  argument
2269 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\  argument
2273 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\  argument
2275 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\  argument
2279 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\  argument
2281 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\  argument
2285 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\  argument
2287 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\  argument
2295 #define ASM_RAM_INIT_RAM_INIT_SET(x)\  argument
2297 #define ASM_RAM_INIT_RAM_INIT_GET(x)\  argument
2301 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
2303 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
2311 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\  argument
2313 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\  argument
2317 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\  argument
2319 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\  argument
2323 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\  argument
2325 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\  argument
2329 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\  argument
2331 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\  argument
2335 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\  argument
2337 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\  argument
2341 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\  argument
2343 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\  argument
2351 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\  argument
2353 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\  argument
2357 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\  argument
2359 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\  argument
2363 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\  argument
2365 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\  argument
2369 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\  argument
2371 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\  argument
2375 #define CPU_PROC_CTRL_VINITHI_SET(x)\  argument
2377 #define CPU_PROC_CTRL_VINITHI_GET(x)\  argument
2381 #define CPU_PROC_CTRL_CFGTE_SET(x)\  argument
2383 #define CPU_PROC_CTRL_CFGTE_GET(x)\  argument
2387 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\  argument
2389 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\  argument
2393 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\  argument
2395 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\  argument
2399 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\  argument
2401 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\  argument
2405 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\  argument
2407 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\  argument
2411 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\  argument
2413 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\  argument
2417 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\  argument
2419 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\  argument
2423 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\  argument
2425 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\  argument
2433 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
2435 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
2439 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
2441 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
2449 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
2451 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
2455 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
2457 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
2465 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\  argument
2467 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\  argument
2475 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\  argument
2477 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\  argument
2481 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\  argument
2483 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\  argument
2491 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
2493 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
2497 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
2499 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
2503 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
2505 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
2509 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
2511 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
2515 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
2517 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
2521 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
2523 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
2527 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
2529 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
2537 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\  argument
2539 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\  argument
2543 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\  argument
2545 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\  argument
2549 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\  argument
2551 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\  argument
2555 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\  argument
2557 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\  argument
2561 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\  argument
2563 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\  argument
2571 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
2573 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
2577 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
2579 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
2583 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
2585 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
2589 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
2591 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
2595 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
2597 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
2601 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
2603 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
2607 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
2609 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
2613 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
2615 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
2619 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
2621 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
2629 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\  argument
2631 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\  argument
2639 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
2641 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
2645 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
2647 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
2655 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
2657 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
2661 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
2663 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
2671 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
2673 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
2677 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
2679 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
2683 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
2685 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
2689 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
2691 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
2695 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
2697 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
2701 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
2703 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
2707 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
2709 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
2717 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
2719 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
2723 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
2725 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
2729 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
2731 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
2735 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
2737 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
2741 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
2743 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
2747 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
2749 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
2753 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
2755 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
2759 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
2761 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
2765 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
2767 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
2775 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\  argument
2777 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\  argument
2785 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\  argument
2787 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\  argument
2791 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\  argument
2793 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\  argument
2797 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\  argument
2799 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\  argument
2807 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
2809 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
2813 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
2815 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
2819 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\  argument
2821 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\  argument
2825 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\  argument
2827 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\  argument
2831 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
2833 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
2837 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
2839 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
2843 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
2845 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
2849 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
2851 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
2859 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
2861 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
2865 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
2867 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
2875 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\  argument
2877 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\  argument
2881 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\  argument
2883 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\  argument
2887 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\  argument
2889 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\  argument
2897 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
2899 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
2907 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\  argument
2909 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\  argument
2913 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\  argument
2915 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\  argument
2919 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\  argument
2921 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\  argument
2925 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\  argument
2927 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\  argument
2935 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\  argument
2937 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\  argument
2941 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\  argument
2943 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\  argument
2951 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\  argument
2953 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\  argument
2961 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\  argument
2963 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\  argument
2967 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\  argument
2969 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\  argument
2973 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\  argument
2975 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\  argument
2979 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\  argument
2981 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\  argument
2989 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\  argument
2991 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\  argument
2995 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\  argument
2997 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\  argument
3001 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\  argument
3003 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\  argument
3007 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\  argument
3009 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\  argument
3013 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\  argument
3015 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\  argument
3023 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\  argument
3025 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\  argument
3029 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
3031 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
3035 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\  argument
3037 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\  argument
3045 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\  argument
3047 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\  argument
3051 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\  argument
3053 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\  argument
3057 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\  argument
3059 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\  argument
3067 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\  argument
3069 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\  argument
3073 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\  argument
3075 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\  argument
3079 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\  argument
3081 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\  argument
3089 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\  argument
3091 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\  argument
3095 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\  argument
3097 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\  argument
3101 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\  argument
3103 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\  argument
3107 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\  argument
3109 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\  argument
3117 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\  argument
3119 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\  argument
3123 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\  argument
3125 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\  argument
3129 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\  argument
3131 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\  argument
3139 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\  argument
3141 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\  argument
3145 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\  argument
3147 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\  argument
3151 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\  argument
3153 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\  argument
3157 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\  argument
3159 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\  argument
3167 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\  argument
3169 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\  argument
3173 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\  argument
3175 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\  argument
3179 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\  argument
3181 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\  argument
3185 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\  argument
3187 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\  argument
3195 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\  argument
3197 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\  argument
3201 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\  argument
3203 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\  argument
3211 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\  argument
3213 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\  argument
3217 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\  argument
3219 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\  argument
3223 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\  argument
3225 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\  argument
3229 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\  argument
3231 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\  argument
3235 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\  argument
3237 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\  argument
3241 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\  argument
3243 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\  argument
3247 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\  argument
3249 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\  argument
3253 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\  argument
3255 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\  argument
3259 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\  argument
3261 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\  argument
3265 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\  argument
3267 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\  argument
3271 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\  argument
3273 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\  argument
3277 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\  argument
3279 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\  argument
3283 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\  argument
3285 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\  argument
3293 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\  argument
3295 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\  argument
3299 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\  argument
3301 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\  argument
3305 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\  argument
3307 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\  argument
3311 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\  argument
3313 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\  argument
3317 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\  argument
3319 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\  argument
3323 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\  argument
3325 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\  argument
3329 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\  argument
3331 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\  argument
3335 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\  argument
3337 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\  argument
3345 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
3347 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
3351 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
3353 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
3361 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
3363 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
3367 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
3369 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
3377 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
3379 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
3383 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
3385 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
3389 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
3391 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
3395 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
3397 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
3401 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
3403 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
3407 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
3409 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
3413 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
3415 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
3739 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\  argument
3741 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\  argument
3753 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
3755 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
3767 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
3769 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
3781 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\  argument
3783 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\  argument
3795 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
3797 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
3809 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
3811 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
3823 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
3825 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
3837 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
3839 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
3847 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
3849 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
3853 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
3855 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
3859 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
3861 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
3865 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
3867 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
3871 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
3873 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
3877 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
3879 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
3883 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
3885 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
3889 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
3891 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
3895 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
3897 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
3905 #define DSM_RAM_INIT_RAM_INIT_SET(x)\  argument
3907 #define DSM_RAM_INIT_RAM_INIT_GET(x)\  argument
3911 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
3913 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
3921 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\  argument
3923 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\  argument
3927 #define DSM_BUF_CFG_AGING_ENA_SET(x)\  argument
3929 #define DSM_BUF_CFG_AGING_ENA_GET(x)\  argument
3933 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\  argument
3935 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\  argument
3939 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\  argument
3941 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\  argument
3949 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\  argument
3951 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\  argument
3955 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\  argument
3957 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\  argument
3961 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\  argument
3963 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\  argument
3967 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\  argument
3969 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\  argument
3977 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\  argument
3979 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\  argument
3983 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\  argument
3985 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\  argument
3993 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\  argument
3995 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\  argument
3999 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\  argument
4001 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\  argument
4005 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\  argument
4007 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\  argument
4011 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\  argument
4013 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\  argument
4021 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\  argument
4023 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\  argument
4031 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\  argument
4033 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\  argument
4041 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\  argument
4043 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\  argument
4047 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\  argument
4049 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\  argument
4053 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\  argument
4055 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\  argument
4059 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\  argument
4061 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\  argument
4065 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\  argument
4067 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\  argument
4075 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x)\  argument
4077 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_GET(x)\  argument
4081 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(x)\  argument
4083 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_GET(x)\  argument
4087 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(x)\  argument
4089 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_GET(x)\  argument
4093 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(x)\  argument
4095 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x)\  argument
4107 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\  argument
4109 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\  argument
4113 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\  argument
4115 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\  argument
4119 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\  argument
4121 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\  argument
4125 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\  argument
4127 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\  argument
4131 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\  argument
4133 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\  argument
4137 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\  argument
4139 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\  argument
4147 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\  argument
4149 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\  argument
4153 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\  argument
4155 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\  argument
4159 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\  argument
4161 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\  argument
4165 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\  argument
4167 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\  argument
4171 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\  argument
4173 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\  argument
4177 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\  argument
4179 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\  argument
4183 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\  argument
4185 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\  argument
4189 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\  argument
4191 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\  argument
4199 #define EACL_RAM_INIT_RAM_INIT_SET(x)\  argument
4201 #define EACL_RAM_INIT_RAM_INIT_GET(x)\  argument
4205 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
4207 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
4215 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\  argument
4217 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\  argument
4225 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\  argument
4227 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\  argument
4235 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\  argument
4237 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\  argument
4261 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\  argument
4263 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\  argument
4267 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\  argument
4269 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\  argument
4273 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\  argument
4275 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\  argument
4279 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\  argument
4281 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\  argument
4285 #define FDMA_CH_CFG_CH_MEM_SET(x)\  argument
4287 #define FDMA_CH_CFG_CH_MEM_GET(x)\  argument
4295 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\  argument
4297 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\  argument
4305 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\  argument
4307 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\  argument
4311 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\  argument
4313 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\  argument
4321 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\  argument
4323 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\  argument
4327 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\  argument
4329 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\  argument
4333 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\  argument
4335 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\  argument
4339 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\  argument
4341 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\  argument
4345 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\  argument
4347 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\  argument
4355 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\  argument
4357 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\  argument
4365 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\  argument
4367 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\  argument
4375 #define FDMA_INTR_DB_INTR_DB_SET(x)\  argument
4377 #define FDMA_INTR_DB_INTR_DB_GET(x)\  argument
4385 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\  argument
4387 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\  argument
4395 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\  argument
4397 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\  argument
4401 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\  argument
4403 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\  argument
4411 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\  argument
4413 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\  argument
4417 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\  argument
4419 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\  argument
4423 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\  argument
4425 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\  argument
4429 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\  argument
4431 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\  argument
4435 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\  argument
4437 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\  argument
4441 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\  argument
4443 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\  argument
4447 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\  argument
4449 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\  argument
4453 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\  argument
4455 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\  argument
4463 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\  argument
4465 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\  argument
4473 #define FDMA_CTRL_NRESET_SET(x)\  argument
4475 #define FDMA_CTRL_NRESET_GET(x)\  argument
4483 #define GCB_CHIP_ID_REV_ID_SET(x)\  argument
4485 #define GCB_CHIP_ID_REV_ID_GET(x)\  argument
4489 #define GCB_CHIP_ID_PART_ID_SET(x)\  argument
4491 #define GCB_CHIP_ID_PART_ID_GET(x)\  argument
4495 #define GCB_CHIP_ID_MFG_ID_SET(x)\  argument
4497 #define GCB_CHIP_ID_MFG_ID_GET(x)\  argument
4501 #define GCB_CHIP_ID_ONE_SET(x)\  argument
4503 #define GCB_CHIP_ID_ONE_GET(x)\  argument
4511 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\  argument
4513 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\  argument
4517 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\  argument
4519 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\  argument
4523 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\  argument
4525 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\  argument
4533 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\  argument
4535 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\  argument
4539 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\  argument
4541 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\  argument
4549 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\  argument
4551 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\  argument
4559 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\  argument
4561 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\  argument
4565 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\  argument
4567 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\  argument
4575 #define HSCH_CIR_CFG_CIR_RATE_SET(x)\  argument
4577 #define HSCH_CIR_CFG_CIR_RATE_GET(x)\  argument
4581 #define HSCH_CIR_CFG_CIR_BURST_SET(x)\  argument
4583 #define HSCH_CIR_CFG_CIR_BURST_GET(x)\  argument
4591 #define HSCH_EIR_CFG_EIR_RATE_SET(x)\  argument
4593 #define HSCH_EIR_CFG_EIR_RATE_GET(x)\  argument
4597 #define HSCH_EIR_CFG_EIR_BURST_SET(x)\  argument
4599 #define HSCH_EIR_CFG_EIR_BURST_GET(x)\  argument
4607 #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\  argument
4609 #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\  argument
4613 #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\  argument
4615 #define HSCH_SE_CFG_SE_AVB_ENA_GET(x)\  argument
4619 #define HSCH_SE_CFG_SE_FRM_MODE_SET(x)\  argument
4621 #define HSCH_SE_CFG_SE_FRM_MODE_GET(x)\  argument
4625 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x)\  argument
4627 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x)\  argument
4631 #define HSCH_SE_CFG_SE_STOP_SET(x)\  argument
4633 #define HSCH_SE_CFG_SE_STOP_GET(x)\  argument
4641 #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\  argument
4643 #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\  argument
4651 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\  argument
4653 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\  argument
4657 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\  argument
4659 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\  argument
4663 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\  argument
4665 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x)\  argument
4669 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x)\  argument
4671 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x)\  argument
4675 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x)\  argument
4677 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\  argument
4685 #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\  argument
4687 #define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\  argument
4691 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\  argument
4693 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\  argument
4701 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\  argument
4703 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\  argument
4707 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\  argument
4709 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x)\  argument
4713 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x)\  argument
4715 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\  argument
4723 #define HSCH_SYS_CLK_PER_100PS_SET(x)\  argument
4725 #define HSCH_SYS_CLK_PER_100PS_GET(x)\  argument
4733 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\  argument
4735 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\  argument
4743 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\  argument
4745 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\  argument
4749 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\  argument
4751 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\  argument
4759 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\  argument
4761 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\  argument
4765 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\  argument
4767 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\  argument
4771 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\  argument
4773 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\  argument
4777 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\  argument
4779 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\  argument
4783 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\  argument
4785 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\  argument
4789 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\  argument
4791 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\  argument
4795 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\  argument
4797 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\  argument
4805 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\  argument
4807 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\  argument
4811 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\  argument
4813 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\  argument
4817 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\  argument
4819 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\  argument
4823 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\  argument
4825 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\  argument
4829 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\  argument
4831 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\  argument
4839 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\  argument
4841 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\  argument
4849 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\  argument
4851 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\  argument
4859 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\  argument
4861 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\  argument
4869 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\  argument
4871 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\  argument
4875 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\  argument
4877 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\  argument
4881 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\  argument
4883 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\  argument
4887 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\  argument
4889 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\  argument
4893 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\  argument
4895 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\  argument
4903 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\  argument
4905 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\  argument
4909 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\  argument
4911 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\  argument
4923 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\  argument
4925 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\  argument
4929 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\  argument
4931 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\  argument
4935 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\  argument
4937 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\  argument
4941 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\  argument
4943 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\  argument
4947 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\  argument
4949 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\  argument
4953 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\  argument
4955 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\  argument
4959 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\  argument
4961 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\  argument
4965 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\  argument
4967 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\  argument
4971 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\  argument
4973 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\  argument
4977 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\  argument
4979 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\  argument
4983 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\  argument
4985 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\  argument
4989 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\  argument
4991 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\  argument
4999 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\  argument
5001 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\  argument
5009 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\  argument
5011 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\  argument
5015 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\  argument
5017 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\  argument
5021 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\  argument
5023 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\  argument
5027 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\  argument
5029 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\  argument
5033 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\  argument
5035 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\  argument
5039 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\  argument
5041 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\  argument
5045 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\  argument
5047 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\  argument
5051 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\  argument
5053 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\  argument
5057 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\  argument
5059 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\  argument
5063 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\  argument
5065 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\  argument
5069 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\  argument
5071 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\  argument
5075 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\  argument
5077 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\  argument
5081 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\  argument
5083 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\  argument
5087 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\  argument
5089 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\  argument
5093 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\  argument
5095 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\  argument
5103 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\  argument
5105 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\  argument
5109 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\  argument
5111 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\  argument
5119 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\  argument
5121 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\  argument
5125 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\  argument
5127 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\  argument
5135 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\  argument
5137 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\  argument
5141 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\  argument
5143 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\  argument
5147 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\  argument
5149 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\  argument
5153 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\  argument
5155 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\  argument
5159 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\  argument
5161 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\  argument
5165 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\  argument
5167 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\  argument
5171 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\  argument
5173 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\  argument
5181 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\  argument
5183 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\  argument
5187 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\  argument
5189 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\  argument
5197 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\  argument
5199 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\  argument
5203 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\  argument
5205 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\  argument
5209 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\  argument
5211 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\  argument
5215 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\  argument
5217 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\  argument
5221 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\  argument
5223 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\  argument
5227 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\  argument
5229 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\  argument
5233 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\  argument
5235 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\  argument
5239 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\  argument
5241 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\  argument
5245 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\  argument
5247 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\  argument
5251 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\  argument
5253 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\  argument
5261 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\  argument
5263 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\  argument
5267 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\  argument
5269 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\  argument
5281 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\  argument
5283 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\  argument
5287 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\  argument
5289 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\  argument
5305 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\  argument
5307 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\  argument
5311 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\  argument
5313 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\  argument
5321 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
5323 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
5327 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
5329 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
5333 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
5335 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
5339 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
5341 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
5345 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
5347 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
5351 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
5353 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
5357 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
5359 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
5363 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
5365 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
5369 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
5371 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
5375 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
5377 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
5381 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
5383 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
5387 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
5389 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
5397 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
5399 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
5403 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
5405 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
5409 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
5411 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
5419 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
5421 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
5425 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
5427 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
5431 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
5433 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
5437 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
5439 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
5443 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
5445 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
5449 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
5451 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
5455 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
5457 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
5461 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
5463 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
5467 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
5469 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
5473 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
5475 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
5479 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
5481 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
5485 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
5487 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
5495 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
5497 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
5501 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
5503 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
5507 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
5509 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
5517 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
5519 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
5523 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
5525 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
5529 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
5531 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
5535 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
5537 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
5541 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
5543 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
5547 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
5549 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
5553 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
5555 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
5559 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
5561 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
5565 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
5567 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
5571 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
5573 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
5577 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
5579 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
5583 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
5585 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
5593 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
5595 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
5599 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
5601 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
5605 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
5607 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
5615 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\  argument
5617 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\  argument
5621 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\  argument
5623 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\  argument
5627 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\  argument
5629 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\  argument
5633 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\  argument
5635 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\  argument
5639 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\  argument
5641 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\  argument
5645 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\  argument
5647 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\  argument
5651 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\  argument
5653 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\  argument
5657 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\  argument
5659 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\  argument
5663 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\  argument
5665 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\  argument
5669 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\  argument
5671 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\  argument
5675 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\  argument
5677 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\  argument
5681 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\  argument
5683 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\  argument
5687 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\  argument
5689 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\  argument
5697 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\  argument
5699 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\  argument
5703 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\  argument
5705 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\  argument
5709 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\  argument
5711 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\  argument
5715 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\  argument
5717 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\  argument
5721 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\  argument
5723 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\  argument
5727 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\  argument
5729 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\  argument
5733 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\  argument
5735 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\  argument
5739 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\  argument
5741 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\  argument
5745 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\  argument
5747 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\  argument
5751 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\  argument
5753 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\  argument
5757 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\  argument
5759 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\  argument
5763 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\  argument
5765 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\  argument
5773 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\  argument
5775 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\  argument
5779 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\  argument
5781 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\  argument
5785 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\  argument
5787 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\  argument
5791 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\  argument
5793 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\  argument
5797 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\  argument
5799 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\  argument
5803 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\  argument
5805 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\  argument
5809 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\  argument
5811 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\  argument
5815 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\  argument
5817 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\  argument
5825 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\  argument
5827 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\  argument
5831 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\  argument
5833 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\  argument
5837 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\  argument
5839 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\  argument
5843 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\  argument
5845 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\  argument
5849 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\  argument
5851 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\  argument
5855 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\  argument
5857 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\  argument
5861 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\  argument
5863 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\  argument
5867 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\  argument
5869 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\  argument
5873 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\  argument
5875 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\  argument
5879 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\  argument
5881 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\  argument
5885 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\  argument
5887 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\  argument
5891 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\  argument
5893 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\  argument
5901 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\  argument
5903 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\  argument
5907 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\  argument
5909 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\  argument
5913 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\  argument
5915 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\  argument
5919 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\  argument
5921 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\  argument
5925 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\  argument
5927 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\  argument
5931 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\  argument
5933 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\  argument
5937 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\  argument
5939 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\  argument
5947 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\  argument
5949 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\  argument
5957 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\  argument
5959 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\  argument
5967 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\  argument
5969 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\  argument
5977 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\  argument
5979 #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\  argument
5983 #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\  argument
5985 #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\  argument
5989 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\  argument
5991 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\  argument
5995 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\  argument
5997 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\  argument
6009 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\  argument
6011 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\  argument
6019 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\  argument
6021 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\  argument
6033 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\  argument
6035 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\  argument
6047 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\  argument
6049 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\  argument
6053 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\  argument
6055 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\  argument
6059 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\  argument
6061 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\  argument
6065 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\  argument
6067 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\  argument
6071 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\  argument
6073 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\  argument
6077 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\  argument
6079 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\  argument
6083 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\  argument
6085 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\  argument
6089 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\  argument
6091 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\  argument
6095 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\  argument
6097 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\  argument
6105 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\  argument
6107 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\  argument
6119 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\  argument
6121 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\  argument
6129 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\  argument
6131 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\  argument
6143 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\  argument
6145 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\  argument
6153 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\  argument
6155 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\  argument
6163 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\  argument
6165 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\  argument
6169 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\  argument
6171 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\  argument
6179 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\  argument
6181 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\  argument
6185 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\  argument
6187 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\  argument
6191 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\  argument
6193 #define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\  argument
6197 #define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\  argument
6199 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\  argument
6211 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\  argument
6213 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\  argument
6217 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\  argument
6219 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\  argument
6223 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\  argument
6225 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\  argument
6229 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\  argument
6231 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\  argument
6235 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\  argument
6237 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\  argument
6241 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\  argument
6243 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\  argument
6247 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\  argument
6249 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\  argument
6253 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\  argument
6255 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\  argument
6259 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\  argument
6261 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\  argument
6269 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(x)\  argument
6271 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_GET(x)\  argument
6279 #define QRES_RES_CFG_WM_HIGH_SET(x)\  argument
6281 #define QRES_RES_CFG_WM_HIGH_GET(x)\  argument
6289 #define QRES_RES_STAT_MAXUSE_SET(x)\  argument
6291 #define QRES_RES_STAT_MAXUSE_GET(x)\  argument
6299 #define QRES_RES_STAT_CUR_INUSE_SET(x)\  argument
6301 #define QRES_RES_STAT_CUR_INUSE_GET(x)\  argument
6309 #define QS_XTR_GRP_CFG_MODE_SET(x)\  argument
6311 #define QS_XTR_GRP_CFG_MODE_GET(x)\  argument
6315 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\  argument
6317 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\  argument
6321 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\  argument
6323 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\  argument
6335 #define QS_XTR_FLUSH_FLUSH_SET(x)\  argument
6337 #define QS_XTR_FLUSH_FLUSH_GET(x)\  argument
6345 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\  argument
6347 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\  argument
6355 #define QS_INJ_GRP_CFG_MODE_SET(x)\  argument
6357 #define QS_INJ_GRP_CFG_MODE_GET(x)\  argument
6361 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\  argument
6363 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\  argument
6375 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\  argument
6377 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\  argument
6381 #define QS_INJ_CTRL_ABORT_SET(x)\  argument
6383 #define QS_INJ_CTRL_ABORT_GET(x)\  argument
6387 #define QS_INJ_CTRL_EOF_SET(x)\  argument
6389 #define QS_INJ_CTRL_EOF_GET(x)\  argument
6393 #define QS_INJ_CTRL_SOF_SET(x)\  argument
6395 #define QS_INJ_CTRL_SOF_GET(x)\  argument
6399 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\  argument
6401 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\  argument
6409 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\  argument
6411 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\  argument
6415 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\  argument
6417 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\  argument
6421 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\  argument
6423 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\  argument
6431 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\  argument
6433 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\  argument
6437 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\  argument
6439 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\  argument
6443 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\  argument
6445 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\  argument
6449 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\  argument
6451 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\  argument
6459 #define QSYS_ATOP_ATOP_SET(x)\  argument
6461 #define QSYS_ATOP_ATOP_GET(x)\  argument
6469 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\  argument
6471 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\  argument
6475 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\  argument
6477 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\  argument
6485 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\  argument
6487 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\  argument
6495 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\  argument
6497 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\  argument
6505 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\  argument
6507 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\  argument
6511 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\  argument
6513 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\  argument
6517 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\  argument
6519 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\  argument
6527 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\  argument
6529 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\  argument
6533 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
6535 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
6543 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\  argument
6545 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\  argument
6553 #define REW_RTAG_ETAG_CTRL_IPE_TBL_SET(x)\  argument
6555 #define REW_RTAG_ETAG_CTRL_IPE_TBL_GET(x)\  argument
6559 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(x)\  argument
6561 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_GET(x)\  argument
6565 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_SET(x)\  argument
6567 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_GET(x)\  argument
6575 #define REW_ES0_CTRL_ES0_BY_RT_FWD_SET(x)\  argument
6577 #define REW_ES0_CTRL_ES0_BY_RT_FWD_GET(x)\  argument
6581 #define REW_ES0_CTRL_ES0_BY_RLEG_SET(x)\  argument
6583 #define REW_ES0_CTRL_ES0_BY_RLEG_GET(x)\  argument
6587 #define REW_ES0_CTRL_ES0_DPORT_ENA_SET(x)\  argument
6589 #define REW_ES0_CTRL_ES0_DPORT_ENA_GET(x)\  argument
6593 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_SET(x)\  argument
6595 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_GET(x)\  argument
6599 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_SET(x)\  argument
6601 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_GET(x)\  argument
6605 #define REW_ES0_CTRL_ES0_LU_ENA_SET(x)\  argument
6607 #define REW_ES0_CTRL_ES0_LU_ENA_GET(x)\  argument
6615 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\  argument
6617 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\  argument
6621 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\  argument
6623 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\  argument
6627 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\  argument
6629 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\  argument
6637 #define REW_PCP_MAP_DE0_PCP_DE0_SET(x)\  argument
6639 #define REW_PCP_MAP_DE0_PCP_DE0_GET(x)\  argument
6647 #define REW_PCP_MAP_DE1_PCP_DE1_SET(x)\  argument
6649 #define REW_PCP_MAP_DE1_PCP_DE1_GET(x)\  argument
6657 #define REW_DEI_MAP_DE0_DEI_DE0_SET(x)\  argument
6659 #define REW_DEI_MAP_DE0_DEI_DE0_GET(x)\  argument
6667 #define REW_DEI_MAP_DE1_DEI_DE1_SET(x)\  argument
6669 #define REW_DEI_MAP_DE1_DEI_DE1_GET(x)\  argument
6677 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\  argument
6679 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\  argument
6683 #define REW_TAG_CTRL_TAG_CFG_SET(x)\  argument
6685 #define REW_TAG_CTRL_TAG_CFG_GET(x)\  argument
6689 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\  argument
6691 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\  argument
6695 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\  argument
6697 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\  argument
6701 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\  argument
6703 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\  argument
6707 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\  argument
6709 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\  argument
6717 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x)\  argument
6719 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_GET(x)\  argument
6723 #define REW_DSCP_MAP_DSCP_REMAP_ENA_SET(x)\  argument
6725 #define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x)\  argument
6733 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\  argument
6735 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\  argument
6739 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\  argument
6741 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\  argument
6745 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\  argument
6747 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\  argument
6751 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\  argument
6753 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\  argument
6757 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\  argument
6759 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\  argument
6763 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\  argument
6765 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\  argument
6773 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\  argument
6775 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\  argument
6783 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\  argument
6785 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\  argument
6801 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\  argument
6803 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\  argument
6811 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\  argument
6813 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\  argument
6817 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\  argument
6819 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\  argument
6827 #define REW_RAM_INIT_RAM_INIT_SET(x)\  argument
6829 #define REW_RAM_INIT_RAM_INIT_GET(x)\  argument
6833 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
6835 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
6843 #define VCAP_ES0_CTRL_UPDATE_CMD_SET(x)\  argument
6845 #define VCAP_ES0_CTRL_UPDATE_CMD_GET(x)\  argument
6849 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_SET(x)\  argument
6851 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_GET(x)\  argument
6855 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_SET(x)\  argument
6857 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_GET(x)\  argument
6861 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_SET(x)\  argument
6863 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_GET(x)\  argument
6867 #define VCAP_ES0_CTRL_UPDATE_ADDR_SET(x)\  argument
6869 #define VCAP_ES0_CTRL_UPDATE_ADDR_GET(x)\  argument
6873 #define VCAP_ES0_CTRL_UPDATE_SHOT_SET(x)\  argument
6875 #define VCAP_ES0_CTRL_UPDATE_SHOT_GET(x)\  argument
6879 #define VCAP_ES0_CTRL_CLEAR_CACHE_SET(x)\  argument
6881 #define VCAP_ES0_CTRL_CLEAR_CACHE_GET(x)\  argument
6885 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_SET(x)\  argument
6887 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_GET(x)\  argument
6895 #define VCAP_ES0_CFG_MV_NUM_POS_SET(x)\  argument
6897 #define VCAP_ES0_CFG_MV_NUM_POS_GET(x)\  argument
6901 #define VCAP_ES0_CFG_MV_SIZE_SET(x)\  argument
6903 #define VCAP_ES0_CFG_MV_SIZE_GET(x)\  argument
6935 #define VCAP_ES0_IDX_CORE_IDX_SET(x)\  argument
6937 #define VCAP_ES0_IDX_CORE_IDX_GET(x)\  argument
6945 #define VCAP_ES0_MAP_CORE_MAP_SET(x)\  argument
6947 #define VCAP_ES0_MAP_CORE_MAP_GET(x)\  argument
6955 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\  argument
6957 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\  argument
7005 #define VCAP_ES2_CTRL_UPDATE_CMD_SET(x)\  argument
7007 #define VCAP_ES2_CTRL_UPDATE_CMD_GET(x)\  argument
7011 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_SET(x)\  argument
7013 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_GET(x)\  argument
7017 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_SET(x)\  argument
7019 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_GET(x)\  argument
7023 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_SET(x)\  argument
7025 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_GET(x)\  argument
7029 #define VCAP_ES2_CTRL_UPDATE_ADDR_SET(x)\  argument
7031 #define VCAP_ES2_CTRL_UPDATE_ADDR_GET(x)\  argument
7035 #define VCAP_ES2_CTRL_UPDATE_SHOT_SET(x)\  argument
7037 #define VCAP_ES2_CTRL_UPDATE_SHOT_GET(x)\  argument
7041 #define VCAP_ES2_CTRL_CLEAR_CACHE_SET(x)\  argument
7043 #define VCAP_ES2_CTRL_CLEAR_CACHE_GET(x)\  argument
7047 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_SET(x)\  argument
7049 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x)\  argument
7057 #define VCAP_ES2_CFG_MV_NUM_POS_SET(x)\  argument
7059 #define VCAP_ES2_CFG_MV_NUM_POS_GET(x)\  argument
7063 #define VCAP_ES2_CFG_MV_SIZE_SET(x)\  argument
7065 #define VCAP_ES2_CFG_MV_SIZE_GET(x)\  argument
7097 #define VCAP_ES2_IDX_CORE_IDX_SET(x)\  argument
7099 #define VCAP_ES2_IDX_CORE_IDX_GET(x)\  argument
7107 #define VCAP_ES2_MAP_CORE_MAP_SET(x)\  argument
7109 #define VCAP_ES2_MAP_CORE_MAP_GET(x)\  argument
7117 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\  argument
7119 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\  argument
7167 #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\  argument
7169 #define VCAP_SUPER_CTRL_UPDATE_CMD_GET(x)\  argument
7173 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_SET(x)\  argument
7175 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_GET(x)\  argument
7179 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_SET(x)\  argument
7181 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_GET(x)\  argument
7185 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_SET(x)\  argument
7187 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_GET(x)\  argument
7191 #define VCAP_SUPER_CTRL_UPDATE_ADDR_SET(x)\  argument
7193 #define VCAP_SUPER_CTRL_UPDATE_ADDR_GET(x)\  argument
7197 #define VCAP_SUPER_CTRL_UPDATE_SHOT_SET(x)\  argument
7199 #define VCAP_SUPER_CTRL_UPDATE_SHOT_GET(x)\  argument
7203 #define VCAP_SUPER_CTRL_CLEAR_CACHE_SET(x)\  argument
7205 #define VCAP_SUPER_CTRL_CLEAR_CACHE_GET(x)\  argument
7209 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_SET(x)\  argument
7211 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\  argument
7219 #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\  argument
7221 #define VCAP_SUPER_CFG_MV_NUM_POS_GET(x)\  argument
7225 #define VCAP_SUPER_CFG_MV_SIZE_SET(x)\  argument
7227 #define VCAP_SUPER_CFG_MV_SIZE_GET(x)\  argument
7259 #define VCAP_SUPER_IDX_CORE_IDX_SET(x)\  argument
7261 #define VCAP_SUPER_IDX_CORE_IDX_GET(x)\  argument
7269 #define VCAP_SUPER_MAP_CORE_MAP_SET(x)\  argument
7271 #define VCAP_SUPER_MAP_CORE_MAP_GET(x)\  argument
7319 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\  argument
7321 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\  argument
7325 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
7327 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
7335 #define VOP_RAM_INIT_RAM_INIT_SET(x)\  argument
7337 #define VOP_RAM_INIT_RAM_INIT_GET(x)\  argument
7341 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
7343 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
7351 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\  argument
7353 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\  argument
7357 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\  argument
7359 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\  argument
7363 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\  argument
7365 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\  argument
7369 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\  argument
7371 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\  argument
7379 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\  argument
7381 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\  argument
7389 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\  argument
7391 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\  argument
7399 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\  argument
7401 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\  argument
7409 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\  argument
7411 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\  argument