59 	spx5_wr(((u64)fdma->dma) & GENMASK(31, 0), sparx5,  in sparx5_fdma_rx_activate()
61 	spx5_wr(((u64)fdma->dma) >> 32, sparx5,  in sparx5_fdma_rx_activate()
65 	spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) |  in sparx5_fdma_rx_activate()
85 	spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_ACTIVATE);  in sparx5_fdma_rx_activate()
110 	spx5_wr(((u64)fdma->dma) & GENMASK(31, 0), sparx5,  in sparx5_fdma_tx_activate()
112 	spx5_wr(((u64)fdma->dma) >> 32, sparx5,  in sparx5_fdma_tx_activate()
116 	spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(fdma->n_dbs) |  in sparx5_fdma_tx_activate()
126 	spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_ACTIVATE);  in sparx5_fdma_tx_activate()
139 	spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_RELOAD);  in sparx5_fdma_reload()
333 		spx5_wr(0, sparx5, FDMA_INTR_DB_ENA);  in sparx5_fdma_handler()
334 		spx5_wr(db, sparx5, FDMA_INTR_DB);  in sparx5_fdma_handler()
343 		spx5_wr(err, sparx5, FDMA_INTR_ERR);  in sparx5_fdma_handler()
344 		spx5_wr(err_type, sparx5, FDMA_ERRORS);  in sparx5_fdma_handler()
356 	spx5_wr(QS_XTR_GRP_CFG_MODE_SET(2) |  in sparx5_fdma_injection_mode()
360 	spx5_wr(QS_INJ_GRP_CFG_MODE_SET(2) |  in sparx5_fdma_injection_mode()
367 		spx5_wr(ASM_PORT_CFG_PAD_ENA_SET(1) |  in sparx5_fdma_injection_mode()
414 	spx5_wr(FDMA_CTRL_NRESET_SET(0), sparx5, FDMA_CTRL);  in sparx5_fdma_start()
415 	spx5_wr(FDMA_CTRL_NRESET_SET(1), sparx5, FDMA_CTRL);  in sparx5_fdma_start()