Lines Matching defs:x

38 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\  argument
40 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ argument
47 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ argument
49 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ argument
53 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\ argument
55 #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\ argument
62 #define ANA_ADVLEARN_VLAN_CHK_SET(x)\ argument
64 #define ANA_ADVLEARN_VLAN_CHK_GET(x)\ argument
74 #define ANA_ANAINTR_INTR_SET(x)\ argument
76 #define ANA_ANAINTR_INTR_GET(x)\ argument
80 #define ANA_ANAINTR_INTR_ENA_SET(x)\ argument
82 #define ANA_ANAINTR_INTR_ENA_GET(x)\ argument
89 #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\ argument
91 #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\ argument
98 #define ANA_MIRRORPORTS_MIRRORPORTS_SET(x)\ argument
100 #define ANA_MIRRORPORTS_MIRRORPORTS_GET(x)\ argument
107 #define ANA_EMIRRORPORTS_EMIRRORPORTS_SET(x)\ argument
109 #define ANA_EMIRRORPORTS_EMIRRORPORTS_GET(x)\ argument
116 #define ANA_FLOODING_FLD_UNICAST_SET(x)\ argument
118 #define ANA_FLOODING_FLD_UNICAST_GET(x)\ argument
122 #define ANA_FLOODING_FLD_BROADCAST_SET(x)\ argument
124 #define ANA_FLOODING_FLD_BROADCAST_GET(x)\ argument
128 #define ANA_FLOODING_FLD_MULTICAST_SET(x)\ argument
130 #define ANA_FLOODING_FLD_MULTICAST_GET(x)\ argument
137 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\ argument
139 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\ argument
143 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\ argument
145 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\ argument
149 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\ argument
151 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\ argument
155 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\ argument
157 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\ argument
164 #define ANA_PGID_PGID_SET(x)\ argument
166 #define ANA_PGID_PGID_GET(x)\ argument
173 #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\ argument
175 #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\ argument
188 #define ANA_MACACCESS_CHANGE2SW_SET(x)\ argument
190 #define ANA_MACACCESS_CHANGE2SW_GET(x)\ argument
194 #define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\ argument
196 #define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\ argument
200 #define ANA_MACACCESS_VALID_SET(x)\ argument
202 #define ANA_MACACCESS_VALID_GET(x)\ argument
206 #define ANA_MACACCESS_ENTRYTYPE_SET(x)\ argument
208 #define ANA_MACACCESS_ENTRYTYPE_GET(x)\ argument
212 #define ANA_MACACCESS_DEST_IDX_SET(x)\ argument
214 #define ANA_MACACCESS_DEST_IDX_GET(x)\ argument
218 #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\ argument
220 #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\ argument
227 #define ANA_MACTINDX_BUCKET_SET(x)\ argument
229 #define ANA_MACTINDX_BUCKET_GET(x)\ argument
233 #define ANA_MACTINDX_M_INDEX_SET(x)\ argument
235 #define ANA_MACTINDX_M_INDEX_GET(x)\ argument
242 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\ argument
244 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\ argument
251 #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\ argument
253 #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\ argument
260 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\ argument
262 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\ argument
266 #define ANA_VLANTIDX_V_INDEX_SET(x)\ argument
268 #define ANA_VLANTIDX_V_INDEX_GET(x)\ argument
275 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\ argument
277 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\ argument
281 #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\ argument
283 #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\ argument
287 #define ANA_VLAN_CFG_VLAN_PCP_SET(x)\ argument
289 #define ANA_VLAN_CFG_VLAN_PCP_GET(x)\ argument
293 #define ANA_VLAN_CFG_VLAN_DEI_SET(x)\ argument
295 #define ANA_VLAN_CFG_VLAN_DEI_GET(x)\ argument
299 #define ANA_VLAN_CFG_VLAN_VID_SET(x)\ argument
301 #define ANA_VLAN_CFG_VLAN_VID_GET(x)\ argument
308 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\ argument
310 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\ argument
314 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\ argument
316 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\ argument
320 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\ argument
322 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\ argument
326 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\ argument
328 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\ argument
335 #define ANA_QOS_CFG_DP_DEFAULT_VAL_SET(x)\ argument
337 #define ANA_QOS_CFG_DP_DEFAULT_VAL_GET(x)\ argument
341 #define ANA_QOS_CFG_QOS_DEFAULT_VAL_SET(x)\ argument
343 #define ANA_QOS_CFG_QOS_DEFAULT_VAL_GET(x)\ argument
347 #define ANA_QOS_CFG_QOS_DSCP_ENA_SET(x)\ argument
349 #define ANA_QOS_CFG_QOS_DSCP_ENA_GET(x)\ argument
353 #define ANA_QOS_CFG_QOS_PCP_ENA_SET(x)\ argument
355 #define ANA_QOS_CFG_QOS_PCP_ENA_GET(x)\ argument
359 #define ANA_QOS_CFG_DSCP_REWR_CFG_SET(x)\ argument
361 #define ANA_QOS_CFG_DSCP_REWR_CFG_GET(x)\ argument
368 #define ANA_VCAP_CFG_S1_ENA_SET(x)\ argument
370 #define ANA_VCAP_CFG_S1_ENA_GET(x)\ argument
377 #define ANA_VCAP_S1_CFG_KEY_RT_CFG_SET(x)\ argument
379 #define ANA_VCAP_S1_CFG_KEY_RT_CFG_GET(x)\ argument
383 #define ANA_VCAP_S1_CFG_KEY_IP6_CFG_SET(x)\ argument
385 #define ANA_VCAP_S1_CFG_KEY_IP6_CFG_GET(x)\ argument
389 #define ANA_VCAP_S1_CFG_KEY_IP4_CFG_SET(x)\ argument
391 #define ANA_VCAP_S1_CFG_KEY_IP4_CFG_GET(x)\ argument
395 #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_SET(x)\ argument
397 #define ANA_VCAP_S1_CFG_KEY_OTHER_CFG_GET(x)\ argument
404 #define ANA_VCAP_S2_CFG_ISDX_ENA_SET(x)\ argument
406 #define ANA_VCAP_S2_CFG_ISDX_ENA_GET(x)\ argument
410 #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_SET(x)\ argument
412 #define ANA_VCAP_S2_CFG_UDP_PAYLOAD_ENA_GET(x)\ argument
416 #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_SET(x)\ argument
418 #define ANA_VCAP_S2_CFG_ETYPE_PAYLOAD_ENA_GET(x)\ argument
422 #define ANA_VCAP_S2_CFG_ENA_SET(x)\ argument
424 #define ANA_VCAP_S2_CFG_ENA_GET(x)\ argument
428 #define ANA_VCAP_S2_CFG_SNAP_DIS_SET(x)\ argument
430 #define ANA_VCAP_S2_CFG_SNAP_DIS_GET(x)\ argument
434 #define ANA_VCAP_S2_CFG_ARP_DIS_SET(x)\ argument
436 #define ANA_VCAP_S2_CFG_ARP_DIS_GET(x)\ argument
440 #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_SET(x)\ argument
442 #define ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_GET(x)\ argument
446 #define ANA_VCAP_S2_CFG_IP_OTHER_DIS_SET(x)\ argument
448 #define ANA_VCAP_S2_CFG_IP_OTHER_DIS_GET(x)\ argument
452 #define ANA_VCAP_S2_CFG_IP6_CFG_SET(x)\ argument
454 #define ANA_VCAP_S2_CFG_IP6_CFG_GET(x)\ argument
458 #define ANA_VCAP_S2_CFG_OAM_DIS_SET(x)\ argument
460 #define ANA_VCAP_S2_CFG_OAM_DIS_GET(x)\ argument
467 #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_SET(x)\ argument
469 #define ANA_PCP_DEI_CFG_DP_PCP_DEI_VAL_GET(x)\ argument
473 #define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_SET(x)\ argument
475 #define ANA_PCP_DEI_CFG_QOS_PCP_DEI_VAL_GET(x)\ argument
482 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x)\ argument
484 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x)\ argument
488 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x)\ argument
490 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x)\ argument
494 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x)\ argument
496 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x)\ argument
500 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\ argument
502 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\ argument
512 #define ANA_PORT_CFG_SRC_MIRROR_ENA_SET(x)\ argument
514 #define ANA_PORT_CFG_SRC_MIRROR_ENA_GET(x)\ argument
518 #define ANA_PORT_CFG_LEARNAUTO_SET(x)\ argument
520 #define ANA_PORT_CFG_LEARNAUTO_GET(x)\ argument
524 #define ANA_PORT_CFG_LEARN_ENA_SET(x)\ argument
526 #define ANA_PORT_CFG_LEARN_ENA_GET(x)\ argument
530 #define ANA_PORT_CFG_RECV_ENA_SET(x)\ argument
532 #define ANA_PORT_CFG_RECV_ENA_GET(x)\ argument
536 #define ANA_PORT_CFG_PORTID_VAL_SET(x)\ argument
538 #define ANA_PORT_CFG_PORTID_VAL_GET(x)\ argument
545 #define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_SET(x)\ argument
547 #define ANA_DSCP_REWR_CFG_DSCP_QOS_REWR_VAL_GET(x)\ argument
554 #define ANA_POL_CFG_PORT_POL_ENA_SET(x)\ argument
556 #define ANA_POL_CFG_PORT_POL_ENA_GET(x)\ argument
560 #define ANA_POL_CFG_POL_ORDER_SET(x)\ argument
562 #define ANA_POL_CFG_POL_ORDER_GET(x)\ argument
569 #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\ argument
571 #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\ argument
578 #define ANA_AGGR_CFG_AC_RND_ENA_SET(x)\ argument
580 #define ANA_AGGR_CFG_AC_RND_ENA_GET(x)\ argument
584 #define ANA_AGGR_CFG_AC_DMAC_ENA_SET(x)\ argument
586 #define ANA_AGGR_CFG_AC_DMAC_ENA_GET(x)\ argument
590 #define ANA_AGGR_CFG_AC_SMAC_ENA_SET(x)\ argument
592 #define ANA_AGGR_CFG_AC_SMAC_ENA_GET(x)\ argument
596 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_SET(x)\ argument
598 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_GET(x)\ argument
602 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_SET(x)\ argument
604 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_GET(x)\ argument
608 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_SET(x)\ argument
610 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_GET(x)\ argument
614 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_SET(x)\ argument
616 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_GET(x)\ argument
623 #define ANA_DSCP_CFG_DP_DSCP_VAL_SET(x)\ argument
625 #define ANA_DSCP_CFG_DP_DSCP_VAL_GET(x)\ argument
629 #define ANA_DSCP_CFG_QOS_DSCP_VAL_SET(x)\ argument
631 #define ANA_DSCP_CFG_QOS_DSCP_VAL_GET(x)\ argument
635 #define ANA_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\ argument
637 #define ANA_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\ argument
641 #define ANA_DSCP_CFG_DSCP_REWR_ENA_SET(x)\ argument
643 #define ANA_DSCP_CFG_DSCP_REWR_ENA_GET(x)\ argument
650 #define ANA_POL_PIR_CFG_PIR_RATE_SET(x)\ argument
652 #define ANA_POL_PIR_CFG_PIR_RATE_GET(x)\ argument
656 #define ANA_POL_PIR_CFG_PIR_BURST_SET(x)\ argument
658 #define ANA_POL_PIR_CFG_PIR_BURST_GET(x)\ argument
665 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_SET(x)\ argument
667 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_GET(x)\ argument
671 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_SET(x)\ argument
673 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_GET(x)\ argument
677 #define ANA_POL_MODE_IPG_SIZE_SET(x)\ argument
679 #define ANA_POL_MODE_IPG_SIZE_GET(x)\ argument
683 #define ANA_POL_MODE_FRM_MODE_SET(x)\ argument
685 #define ANA_POL_MODE_FRM_MODE_GET(x)\ argument
689 #define ANA_POL_MODE_OVERSHOOT_ENA_SET(x)\ argument
691 #define ANA_POL_MODE_OVERSHOOT_ENA_GET(x)\ argument
698 #define ANA_POL_PIR_STATE_PIR_LVL_SET(x)\ argument
700 #define ANA_POL_PIR_STATE_PIR_LVL_GET(x)\ argument
707 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\ argument
709 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\ argument
716 #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\ argument
718 #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\ argument
722 #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\ argument
724 #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\ argument
728 #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\ argument
730 #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\ argument
734 #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\ argument
736 #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\ argument
740 #define DEV_CLOCK_CFG_PORT_RST_SET(x)\ argument
742 #define DEV_CLOCK_CFG_PORT_RST_GET(x)\ argument
746 #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\ argument
748 #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\ argument
755 #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\ argument
757 #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\ argument
761 #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\ argument
763 #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\ argument
770 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ argument
772 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ argument
779 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ argument
781 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ argument
788 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_SET(x)\ argument
790 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_GET(x)\ argument
794 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ argument
796 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ argument
803 #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\ argument
805 #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\ argument
809 #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\ argument
811 #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\ argument
815 #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\ argument
817 #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\ argument
824 #define DEV_MAC_HDX_CFG_SEED_SET(x)\ argument
826 #define DEV_MAC_HDX_CFG_SEED_GET(x)\ argument
830 #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\ argument
832 #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\ argument
845 #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\ argument
847 #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\ argument
854 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ argument
856 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ argument
860 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\ argument
862 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\ argument
869 #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\ argument
871 #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\ argument
878 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ argument
880 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ argument
884 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ argument
886 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ argument
890 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\ argument
892 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\ argument
896 #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\ argument
898 #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\ argument
905 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\ argument
907 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\ argument
911 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ argument
913 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ argument
920 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ argument
922 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ argument
926 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ argument
928 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ argument
935 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ argument
937 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ argument
944 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ argument
946 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ argument
953 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ argument
955 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ argument
962 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ argument
964 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ argument
971 #define FDMA_CH_DB_DISCARD_DB_DISCARD_SET(x)\ argument
973 #define FDMA_CH_DB_DISCARD_DB_DISCARD_GET(x)\ argument
989 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ argument
991 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ argument
995 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ argument
997 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ argument
1001 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ argument
1003 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ argument
1007 #define FDMA_CH_CFG_CH_MEM_SET(x)\ argument
1009 #define FDMA_CH_CFG_CH_MEM_GET(x)\ argument
1016 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ argument
1018 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\ argument
1022 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\ argument
1024 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\ argument
1034 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ argument
1036 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ argument
1049 #define PTP_PIN_INTR_INTR_PTP_SET(x)\ argument
1051 #define PTP_PIN_INTR_INTR_PTP_GET(x)\ argument
1058 #define PTP_PIN_INTR_ENA_INTR_ENA_SET(x)\ argument
1060 #define PTP_PIN_INTR_ENA_INTR_ENA_GET(x)\ argument
1067 #define PTP_DOM_CFG_ENA_SET(x)\ argument
1069 #define PTP_DOM_CFG_ENA_GET(x)\ argument
1073 #define PTP_DOM_CFG_CLKCFG_DIS_SET(x)\ argument
1075 #define PTP_DOM_CFG_CLKCFG_DIS_GET(x)\ argument
1085 #define PTP_PIN_CFG_PIN_ACTION_SET(x)\ argument
1087 #define PTP_PIN_CFG_PIN_ACTION_GET(x)\ argument
1091 #define PTP_PIN_CFG_PIN_SYNC_SET(x)\ argument
1093 #define PTP_PIN_CFG_PIN_SYNC_GET(x)\ argument
1097 #define PTP_PIN_CFG_PIN_SELECT_SET(x)\ argument
1099 #define PTP_PIN_CFG_PIN_SELECT_GET(x)\ argument
1103 #define PTP_PIN_CFG_PIN_DOM_SET(x)\ argument
1105 #define PTP_PIN_CFG_PIN_DOM_GET(x)\ argument
1112 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x)\ argument
1114 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x)\ argument
1124 #define PTP_TOD_NSEC_TOD_NSEC_SET(x)\ argument
1126 #define PTP_TOD_NSEC_TOD_NSEC_GET(x)\ argument
1133 #define PTP_WF_HIGH_PERIOD_PIN_WFH(x) ((x) & GENMASK(29, 0)) argument
1135 #define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x) ((x) & GENMASK(29, 0)) argument
1141 #define PTP_WF_LOW_PERIOD_PIN_WFL(x) ((x) & GENMASK(29, 0)) argument
1143 #define PTP_WF_LOW_PERIOD_PIN_WFL_X(x) ((x) & GENMASK(29, 0)) argument
1149 #define PTP_TWOSTEP_CTRL_NXT_SET(x)\ argument
1151 #define PTP_TWOSTEP_CTRL_NXT_GET(x)\ argument
1155 #define PTP_TWOSTEP_CTRL_VLD_SET(x)\ argument
1157 #define PTP_TWOSTEP_CTRL_VLD_GET(x)\ argument
1161 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ argument
1163 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ argument
1167 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ argument
1169 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ argument
1173 #define PTP_TWOSTEP_CTRL_OVFL_SET(x)\ argument
1175 #define PTP_TWOSTEP_CTRL_OVFL_GET(x)\ argument
1182 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ argument
1184 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ argument
1191 #define QS_XTR_GRP_CFG_MODE_SET(x)\ argument
1193 #define QS_XTR_GRP_CFG_MODE_GET(x)\ argument
1197 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ argument
1199 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ argument
1215 #define QS_INJ_GRP_CFG_MODE_SET(x)\ argument
1217 #define QS_INJ_GRP_CFG_MODE_GET(x)\ argument
1221 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ argument
1223 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ argument
1233 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ argument
1235 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ argument
1239 #define QS_INJ_CTRL_EOF_SET(x)\ argument
1241 #define QS_INJ_CTRL_EOF_GET(x)\ argument
1245 #define QS_INJ_CTRL_SOF_SET(x)\ argument
1247 #define QS_INJ_CTRL_SOF_GET(x)\ argument
1251 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ argument
1253 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ argument
1260 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ argument
1262 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ argument
1266 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ argument
1268 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ argument
1275 #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\ argument
1277 #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\ argument
1284 #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\ argument
1286 #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\ argument
1290 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\ argument
1292 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\ argument
1296 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ argument
1298 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ argument
1302 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\ argument
1304 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\ argument
1308 #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\ argument
1310 #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\ argument
1317 #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\ argument
1319 #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\ argument
1332 #define QSYS_CIR_CFG_CIR_RATE_SET(x)\ argument
1334 #define QSYS_CIR_CFG_CIR_RATE_GET(x)\ argument
1338 #define QSYS_CIR_CFG_CIR_BURST_SET(x)\ argument
1340 #define QSYS_CIR_CFG_CIR_BURST_GET(x)\ argument
1347 #define QSYS_SE_CFG_SE_DWRR_CNT_SET(x)\ argument
1349 #define QSYS_SE_CFG_SE_DWRR_CNT_GET(x)\ argument
1353 #define QSYS_SE_CFG_SE_RR_ENA_SET(x)\ argument
1355 #define QSYS_SE_CFG_SE_RR_ENA_GET(x)\ argument
1359 #define QSYS_SE_CFG_SE_AVB_ENA_SET(x)\ argument
1361 #define QSYS_SE_CFG_SE_AVB_ENA_GET(x)\ argument
1365 #define QSYS_SE_CFG_SE_FRM_MODE_SET(x)\ argument
1367 #define QSYS_SE_CFG_SE_FRM_MODE_GET(x)\ argument
1373 #define QSYS_SE_DWRR_CFG_DWRR_COST_SET(x)\ argument
1375 #define QSYS_SE_DWRR_CFG_DWRR_COST_GET(x)\ argument
1382 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_SET(x)\ argument
1384 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_GET(x)\ argument
1388 #define QSYS_TAS_CFG_CTRL_LIST_NUM_SET(x)\ argument
1390 #define QSYS_TAS_CFG_CTRL_LIST_NUM_GET(x)\ argument
1394 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_SET(x)\ argument
1396 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_GET(x)\ argument
1400 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(x)\ argument
1402 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_GET(x)\ argument
1409 #define QSYS_TAS_GS_CTRL_HSCH_POS_SET(x)\ argument
1411 #define QSYS_TAS_GS_CTRL_HSCH_POS_GET(x)\ argument
1418 #define QSYS_TAS_STM_CFG_REVISIT_DLY_SET(x)\ argument
1420 #define QSYS_TAS_STM_CFG_REVISIT_DLY_GET(x)\ argument
1427 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_SET(x)\ argument
1429 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_GET(x)\ argument
1433 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_SET(x)\ argument
1435 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_GET(x)\ argument
1442 #define QSYS_TAS_BT_NSEC_NSEC_SET(x)\ argument
1444 #define QSYS_TAS_BT_NSEC_NSEC_GET(x)\ argument
1454 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_SET(x)\ argument
1456 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_GET(x)\ argument
1466 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_SET(x)\ argument
1468 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_GET(x)\ argument
1475 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_SET(x)\ argument
1477 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_GET(x)\ argument
1484 #define QSYS_TAS_LST_LIST_STATE_SET(x)\ argument
1486 #define QSYS_TAS_LST_LIST_STATE_GET(x)\ argument
1493 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_SET(x)\ argument
1495 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_GET(x)\ argument
1499 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_SET(x)\ argument
1501 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_GET(x)\ argument
1505 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_SET(x)\ argument
1507 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_GET(x)\ argument
1514 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_SET(x)\ argument
1516 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_GET(x)\ argument
1520 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_SET(x)\ argument
1522 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_GET(x)\ argument
1532 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_SET(x)\ argument
1534 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_GET(x)\ argument
1541 #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\ argument
1543 #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\ argument
1547 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\ argument
1549 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ argument
1556 #define REW_TAG_CFG_TAG_CFG_SET(x)\ argument
1558 #define REW_TAG_CFG_TAG_CFG_GET(x)\ argument
1562 #define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\ argument
1564 #define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\ argument
1568 #define REW_TAG_CFG_TAG_PCP_CFG_SET(x)\ argument
1570 #define REW_TAG_CFG_TAG_PCP_CFG_GET(x)\ argument
1574 #define REW_TAG_CFG_TAG_DEI_CFG_SET(x)\ argument
1576 #define REW_TAG_CFG_TAG_DEI_CFG_GET(x)\ argument
1583 #define REW_PORT_CFG_ES0_EN_SET(x)\ argument
1585 #define REW_PORT_CFG_ES0_EN_GET(x)\ argument
1589 #define REW_PORT_CFG_NO_REWRITE_SET(x)\ argument
1591 #define REW_PORT_CFG_NO_REWRITE_GET(x)\ argument
1598 #define REW_DSCP_CFG_DSCP_REWR_CFG_SET(x)\ argument
1600 #define REW_DSCP_CFG_DSCP_REWR_CFG_GET(x)\ argument
1607 #define REW_PCP_DEI_CFG_DEI_QOS_VAL_SET(x)\ argument
1609 #define REW_PCP_DEI_CFG_DEI_QOS_VAL_GET(x)\ argument
1613 #define REW_PCP_DEI_CFG_PCP_QOS_VAL_SET(x)\ argument
1615 #define REW_PCP_DEI_CFG_PCP_QOS_VAL_GET(x)\ argument
1622 #define REW_STAT_CFG_STAT_MODE_SET(x)\ argument
1624 #define REW_STAT_CFG_STAT_MODE_GET(x)\ argument
1631 #define SYS_RESET_CFG_CORE_ENA_SET(x)\ argument
1633 #define SYS_RESET_CFG_CORE_ENA_GET(x)\ argument
1640 #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\ argument
1642 #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\ argument
1646 #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\ argument
1648 #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\ argument
1655 #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\ argument
1657 #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\ argument
1664 #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\ argument
1666 #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\ argument
1673 #define SYS_STAT_CFG_STAT_VIEW_SET(x)\ argument
1675 #define SYS_STAT_CFG_STAT_VIEW_GET(x)\ argument
1682 #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\ argument
1684 #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\ argument
1688 #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ argument
1690 #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ argument
1694 #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ argument
1696 #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ argument
1709 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\ argument
1711 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\ argument
1715 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\ argument
1717 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\ argument
1721 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\ argument
1723 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\ argument
1727 #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\ argument
1729 #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\ argument
1733 #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\ argument
1735 #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\ argument
1739 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\ argument
1741 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\ argument
1751 #define SYS_RAM_INIT_RAM_INIT_SET(x)\ argument
1753 #define SYS_RAM_INIT_RAM_INIT_GET(x)\ argument
1760 #define VCAP_UPDATE_CTRL_UPDATE_CMD_SET(x)\ argument
1762 #define VCAP_UPDATE_CTRL_UPDATE_CMD_GET(x)\ argument
1766 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_SET(x)\ argument
1768 #define VCAP_UPDATE_CTRL_UPDATE_ENTRY_DIS_GET(x)\ argument
1772 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_SET(x)\ argument
1774 #define VCAP_UPDATE_CTRL_UPDATE_ACTION_DIS_GET(x)\ argument
1778 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_SET(x)\ argument
1780 #define VCAP_UPDATE_CTRL_UPDATE_CNT_DIS_GET(x)\ argument
1784 #define VCAP_UPDATE_CTRL_UPDATE_ADDR_SET(x)\ argument
1786 #define VCAP_UPDATE_CTRL_UPDATE_ADDR_GET(x)\ argument
1790 #define VCAP_UPDATE_CTRL_UPDATE_SHOT_SET(x)\ argument
1792 #define VCAP_UPDATE_CTRL_UPDATE_SHOT_GET(x)\ argument
1796 #define VCAP_UPDATE_CTRL_CLEAR_CACHE_SET(x)\ argument
1798 #define VCAP_UPDATE_CTRL_CLEAR_CACHE_GET(x)\ argument
1802 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_SET(x)\ argument
1804 #define VCAP_UPDATE_CTRL_MV_TRAFFIC_IGN_GET(x)\ argument
1811 #define VCAP_MV_CFG_MV_NUM_POS_SET(x)\ argument
1813 #define VCAP_MV_CFG_MV_NUM_POS_GET(x)\ argument
1817 #define VCAP_MV_CFG_MV_SIZE_SET(x)\ argument
1819 #define VCAP_MV_CFG_MV_SIZE_GET(x)\ argument
1844 #define VCAP_CORE_IDX_CORE_IDX_SET(x)\ argument
1846 #define VCAP_CORE_IDX_CORE_IDX_GET(x)\ argument
1853 #define VCAP_CORE_MAP_CORE_MAP_SET(x)\ argument
1855 #define VCAP_CORE_MAP_CORE_MAP_GET(x)\ argument