Lines Matching +full:0 +full:xff0f0000
16 #define ID_REV (0x00)
17 #define ID_REV_ID_MASK_ (0xFFFF0000)
18 #define ID_REV_ID_LAN7430_ (0x74300000)
19 #define ID_REV_ID_LAN7431_ (0x74310000)
20 #define ID_REV_ID_LAN743X_ (0x74300000)
21 #define ID_REV_ID_A011_ (0xA0110000) // PCI11010
22 #define ID_REV_ID_A041_ (0xA0410000) // PCI11414
23 #define ID_REV_ID_A0X1_ (0xA0010000)
25 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \
26 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))
27 #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
28 #define ID_REV_CHIP_REV_A0_ (0x00000000)
29 #define ID_REV_CHIP_REV_B0_ (0x00000010)
30 #define ID_REV_CHIP_REV_PCI11X1X_B0_ (0x000000B0)
32 #define FPGA_REV (0x04)
33 #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)
34 #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF)
37 #define STRAP_READ (0x0C)
45 #define STRAP_READ_ADV_PM_DISABLE_ BIT(0)
47 #define HW_CFG (0x010)
53 #define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0)
57 #define PMT_CTL (0x014)
70 #define PMT_CTL_WUPS_MASK_ (0x00000003)
72 #define DP_SEL (0x024)
74 #define DP_SEL_MASK_ (0x0000001F)
75 #define DP_SEL_RFE_RAM (0x00000001)
80 #define DP_CMD (0x028)
81 #define DP_CMD_WRITE_ (0x00000001)
83 #define DP_ADDR (0x02C)
85 #define DP_DATA_0 (0x030)
87 #define E2P_CMD (0x040)
89 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
90 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
91 #define E2P_CMD_EPC_CMD_READ_ (0x00000000)
93 #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF)
95 #define E2P_DATA (0x044)
98 #define ETH_CTRL_REG_ADDR_BASE (0x0000)
99 #define ETH_SYS_REG_ADDR_BASE (0x4000)
100 #define CONFIG_REG_ADDR_BASE (0x0000)
101 #define ETH_EEPROM_REG_ADDR_BASE (0x0E00)
102 #define ETH_OTP_REG_ADDR_BASE (0x1000)
103 #define GEN_SYS_CONFIG_LOAD_STARTED_REG (0x0078)
108 #define SYS_LOCK_REG (0x00A0)
115 #define SYS_LOCK_REG_USB_SS_LOCK_ BIT(0)
121 #define HS_E2P_CMD (HS_EEPROM_REG_ADDR_BASE + 0x0000)
124 #define HS_E2P_CMD_EPC_CMD_READ_ (0x0)
126 #define HS_E2P_CMD_EPC_ADDR_MASK_ GENMASK(15, 0)
127 #define HS_E2P_DATA (HS_EEPROM_REG_ADDR_BASE + 0x0004)
128 #define HS_E2P_DATA_MASK_ GENMASK(7, 0)
129 #define HS_E2P_CFG (HS_EEPROM_REG_ADDR_BASE + 0x0008)
133 #define HS_E2P_CFG_TEST_EEPR_TO_BYP_ BIT(0)
134 #define HS_E2P_PAD_CTL (HS_EEPROM_REG_ADDR_BASE + 0x000C)
136 #define GPIO_CFG0 (0x050)
138 #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit))
140 #define GPIO_CFG1 (0x054)
142 #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit))
144 #define GPIO_CFG2 (0x058)
145 #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit))
147 #define GPIO_CFG3 (0x05C)
149 #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit))
151 #define FCT_RX_CTL (0xAC)
156 #define FCT_TX_CTL (0xC4)
161 #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2))
162 #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00)
166 #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F)
168 ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_)
170 #define MAC_CR (0x100)
179 #define MAC_CR_RST_ BIT(0)
181 #define MAC_RX (0x104)
183 #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000)
185 #define MAC_RX_RXEN_ BIT(0)
187 #define MAC_TX (0x108)
189 #define MAC_TX_TXEN_ BIT(0)
191 #define MAC_FLOW (0x10C)
194 #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF)
196 #define MAC_RX_ADDRH (0x118)
198 #define MAC_RX_ADDRL (0x11C)
200 #define MAC_MII_ACC (0x120)
202 #define MAC_MII_ACC_MDC_CYCLE_MASK_ (0x00070000)
203 #define MAC_MII_ACC_MDC_CYCLE_2_5MHZ_ (0)
209 #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800)
211 #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0)
212 #define MAC_MII_ACC_MII_READ_ (0x00000000)
213 #define MAC_MII_ACC_MII_WRITE_ (0x00000002)
214 #define MAC_MII_ACC_MII_BUSY_ BIT(0)
217 #define MAC_MII_ACC_MIIMMD_MASK_ (0x000007C0)
219 #define MAC_MII_ACC_MIICMD_MASK_ (0x00000006)
220 #define MAC_MII_ACC_MIICMD_ADDR_ (0x00000000)
221 #define MAC_MII_ACC_MIICMD_WRITE_ (0x00000002)
222 #define MAC_MII_ACC_MIICMD_READ_ (0x00000004)
223 #define MAC_MII_ACC_MIICMD_READ_INC_ (0x00000006)
225 #define MAC_MII_DATA (0x124)
227 #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130)
229 #define MAC_WUCSR (0x140)
242 #define MAC_WUCSR_BCST_EN_ BIT(0)
244 #define MAC_WK_SRC (0x144)
257 #define MAC_MP_SO_HI (0x148)
258 #define MAC_MP_SO_LO (0x14C)
260 #define MAC_WUF_CFG0 (0x150)
265 #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000)
266 #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000)
268 #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF)
270 #define MAC_WUF_MASK0_0 (0x200)
271 #define MAC_WUF_MASK0_1 (0x204)
272 #define MAC_WUF_MASK0_2 (0x208)
273 #define MAC_WUF_MASK0_3 (0x20C)
278 #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index)))
279 #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index)))
280 #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index)))
281 #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index)))
283 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
284 #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x)))
287 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
288 #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x)))
290 #define RFE_CTL (0x508)
299 #define RFE_RSS_CFG (0x554)
309 #define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0)
312 #define RFE_RSS_CFG_RSS_ENABLE_ BIT(0)
314 #define RFE_HASH_KEY(index) (0x558 + (index << 2))
316 #define RFE_INDX(index) (0x580 + (index << 2))
318 #define MAC_WUCSR2 (0x600)
324 #define SGMII_ACC (0x720)
330 #define SGMII_ACC_SGMII_ADDR_SHIFT_ (0)
331 #define SGMII_ACC_SGMII_ADDR_MASK_ GENMASK(15, 0)
332 #define SGMII_DATA (0x724)
333 #define SGMII_DATA_SHIFT_ (0)
334 #define SGMII_DATA_MASK_ GENMASK(15, 0)
335 #define SGMII_CTL (0x728)
340 #define MISC_CTL_0 (0x920)
344 #define SR_VSMMD_PCS_ID1 0x0004
345 #define SR_VSMMD_PCS_ID2 0x0005
346 #define SR_VSMMD_STS 0x0008
347 #define SR_VSMMD_CTRL 0x0009
349 #define VR_MII_DIG_CTRL1 0x8000
360 #define VR_MII_DIG_CTRL1_PHY_MODE_CTRL_ BIT(0)
361 #define VR_MII_AN_CTRL 0x8001
365 #define VR_MII_AN_CTRL_1000BASE_X_ (0)
370 #define VR_MII_AN_CTRL_MII_AN_INTR_EN_ BIT(0)
371 #define VR_MII_AN_INTR_STS 0x8002
376 #define VR_MII_AN_INTR_STS_10_MBPS_ (0)
378 #define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_ BIT(0)
380 #define VR_MII_LINK_TIMER_CTRL 0x800A
381 #define VR_MII_DIG_STS 0x8010
384 #define VR_MII_GEN2_4_MPLL_CTRL0 0x8078
387 #define VR_MII_GEN2_4_MPLL_CTRL1 0x8079
388 #define VR_MII_MPLL_CTRL1_MPLL_MULTIPLIER_ GENMASK(6, 0)
395 #define VR_MII_GEN2_4_MISC_CTRL1 0x809A
398 #define VR_MII_CTRL1_TX_RATE_0_MASK_ GENMASK(1, 0)
399 #define VR_MII_MPLL_BAUD_CLK (0)
403 #define INT_STS (0x780)
405 #define INT_BIT_ALL_RX_ (0x0F000000)
407 #define INT_BIT_ALL_TX_ (0x000F0000)
411 #define INT_BIT_MAS_ BIT(0)
413 #define INT_SET (0x784)
415 #define INT_EN_SET (0x788)
417 #define INT_EN_CLR (0x78C)
419 #define INT_STS_R2C (0x790)
421 #define INT_VEC_EN_SET (0x794)
422 #define INT_VEC_EN_CLR (0x798)
423 #define INT_VEC_EN_AUTO_CLR (0x79C)
424 #define INT_VEC_EN_(vector_index) BIT(0 + vector_index)
426 #define INT_VEC_MAP0 (0x7A0)
430 #define INT_VEC_MAP1 (0x7A4)
434 #define INT_VEC_MAP2 (0x7A8)
436 #define INT_MOD_MAP0 (0x7B0)
438 #define INT_MOD_MAP1 (0x7B4)
440 #define INT_MOD_MAP2 (0x7B8)
442 #define INT_MOD_CFG0 (0x7C0)
443 #define INT_MOD_CFG1 (0x7C4)
444 #define INT_MOD_CFG2 (0x7C8)
445 #define INT_MOD_CFG3 (0x7CC)
446 #define INT_MOD_CFG4 (0x7D0)
447 #define INT_MOD_CFG5 (0x7D4)
448 #define INT_MOD_CFG6 (0x7D8)
449 #define INT_MOD_CFG7 (0x7DC)
450 #define INT_MOD_CFG8 (0x7E0)
451 #define INT_MOD_CFG9 (0x7E4)
453 #define PTP_CMD_CTL (0x0A00)
461 #define PTP_CMD_CTL_PTP_RESET_ BIT(0)
462 #define PTP_GENERAL_CONFIG (0x0A04)
464 (0x7 << (1 + ((channel) << 2)))
465 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
473 (((value) & 0x7) << (1 + ((channel) << 2)))
476 #define HS_PTP_GENERAL_CONFIG (0x0A04)
478 (0xf << (4 + ((channel) << 2)))
479 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0)
496 (((value) & 0xf) << (4 + ((channel) << 2)))
500 #define PTP_INT_STS (0x0A08)
513 #define PTP_INT_TIMER_INT_A_ BIT(0)
514 #define PTP_INT_EN_SET (0x0A0C)
518 #define PTP_INT_EN_CLR (0x0A10)
524 #define PTP_INT_BIT_TIMER_A_ BIT(0)
526 #define PTP_CLOCK_SEC (0x0A14)
527 #define PTP_CLOCK_NS (0x0A18)
528 #define PTP_CLOCK_SUBNS (0x0A1C)
529 #define PTP_CLOCK_RATE_ADJ (0x0A20)
531 #define PTP_CLOCK_STEP_ADJ (0x0A2C)
533 #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF)
534 #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4))
535 #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4))
536 #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4))
537 #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4))
538 #define PTP_LTC_SET_SEC_HI (0x0A50)
539 #define PTP_LTC_SET_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)
540 #define PTP_VERSION (0x0A54)
544 #define PTP_VERSION_RX_LO_MASK_ GENMASK(7, 0)
545 #define PTP_IO_SEL (0x0A58)
548 #define PTP_LATENCY (0x0A5C)
551 (((u32)(rx_latency)) & 0x0000FFFF)
552 #define PTP_CAP_INFO (0x0A60)
553 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4)
554 #define PTP_RX_TS_CFG (0x0A68)
555 #define PTP_RX_TS_CFG_EVENT_MSGS_ GENMASK(3, 0)
557 #define PTP_TX_MOD (0x0AA4)
558 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000)
560 #define PTP_TX_MOD2 (0x0AA8)
561 #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001)
563 #define PTP_TX_EGRESS_SEC (0x0AAC)
564 #define PTP_TX_EGRESS_NS (0x0AB0)
565 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000)
566 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000)
567 #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000)
568 #define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF)
570 #define PTP_TX_MSG_HEADER (0x0AB4)
571 #define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000)
572 #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000)
574 #define PTP_TX_CAP_INFO (0x0AB8)
575 #define PTP_TX_CAP_INFO_TX_CH_MASK_ GENMASK(1, 0)
576 #define PTP_TX_DOMAIN (0x0ABC)
579 #define PTP_TX_DOMAIN_RANGE_MASK_ GENMASK(7, 0)
580 #define PTP_TX_SDOID (0x0AC0)
583 #define PTP_TX_SDOID_11_0_MASK_ GENMASK(7, 0)
584 #define PTP_IO_CAP_CONFIG (0x0AC4)
588 #define PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel) BIT(0 + (channel))
589 #define PTP_IO_RE_LTC_SEC_CAP_X (0x0AC8)
590 #define PTP_IO_RE_LTC_NS_CAP_X (0x0ACC)
591 #define PTP_IO_FE_LTC_SEC_CAP_X (0x0AD0)
592 #define PTP_IO_FE_LTC_NS_CAP_X (0x0AD4)
593 #define PTP_IO_EVENT_OUTPUT_CFG (0x0AD8)
595 #define PTP_IO_EVENT_OUTPUT_CFG_EN_(channel) BIT(0 + (channel))
596 #define PTP_IO_PIN_CFG (0x0ADC)
597 #define PTP_IO_PIN_CFG_OBUF_TYPE_(channel) BIT(0 + (channel))
598 #define PTP_LTC_RD_SEC_HI (0x0AF0)
599 #define PTP_LTC_RD_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0)
600 #define PTP_LTC_RD_SEC_LO (0x0AF4)
601 #define PTP_LTC_RD_NS (0x0AF8)
602 #define PTP_LTC_RD_NS_29_0_MASK_ GENMASK(29, 0)
603 #define PTP_LTC_RD_SUBNS (0x0AFC)
604 #define PTP_RX_USER_MAC_HI (0x0B00)
605 #define PTP_RX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)
606 #define PTP_RX_USER_MAC_LO (0x0B04)
607 #define PTP_RX_USER_IP_ADDR_0 (0x0B20)
608 #define PTP_RX_USER_IP_ADDR_1 (0x0B24)
609 #define PTP_RX_USER_IP_ADDR_2 (0x0B28)
610 #define PTP_RX_USER_IP_ADDR_3 (0x0B2C)
611 #define PTP_RX_USER_IP_MASK_0 (0x0B30)
612 #define PTP_RX_USER_IP_MASK_1 (0x0B34)
613 #define PTP_RX_USER_IP_MASK_2 (0x0B38)
614 #define PTP_RX_USER_IP_MASK_3 (0x0B3C)
615 #define PTP_TX_USER_MAC_HI (0x0B40)
616 #define PTP_TX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0)
617 #define PTP_TX_USER_MAC_LO (0x0B44)
618 #define PTP_TX_USER_IP_ADDR_0 (0x0B60)
619 #define PTP_TX_USER_IP_ADDR_1 (0x0B64)
620 #define PTP_TX_USER_IP_ADDR_2 (0x0B68)
621 #define PTP_TX_USER_IP_ADDR_3 (0x0B6C)
622 #define PTP_TX_USER_IP_MASK_0 (0x0B70)
623 #define PTP_TX_USER_IP_MASK_1 (0x0B74)
624 #define PTP_TX_USER_IP_MASK_2 (0x0B78)
625 #define PTP_TX_USER_IP_MASK_3 (0x0B7C)
627 #define DMAC_CFG (0xC00)
629 #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000)
630 #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070)
633 #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000)
634 #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001)
636 #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003)
638 #define DMAC_COAL_CFG (0xC04)
639 #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000)
646 #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00)
649 #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF)
653 #define DMAC_OBFF_CFG (0xC08)
654 #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00)
657 #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF)
661 #define DMAC_CMD (0xC0C)
668 #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel))
670 #define DMAC_INT_STS (0xC10)
671 #define DMAC_INT_EN_SET (0xC14)
672 #define DMAC_INT_EN_CLR (0xC18)
674 #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel))
676 #define RX_CFG_A(channel) (0xC40 + ((channel) << 6))
678 #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000)
681 #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000)
684 #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00)
689 #define RX_CFG_B(channel) (0xC44 + ((channel) << 6))
692 #define RX_CFG_B_TS_NONE_ 0
693 #define RX_CFG_B_TS_MASK_ (0xCFFFFFFF)
694 #define RX_CFG_B_RX_PAD_MASK_ (0x03000000)
695 #define RX_CFG_B_RX_PAD_0_ (0x00000000)
696 #define RX_CFG_B_RX_PAD_2_ (0x02000000)
697 #define RX_CFG_B_RDMABL_512_ (0x00040000)
698 #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF)
700 #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6))
702 #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6))
704 #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6))
706 #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6))
708 #define RX_HEAD(channel) (0xC58 + ((channel) << 6))
710 #define RX_TAIL(channel) (0xC5C + ((channel) << 6))
714 #define RX_CFG_C(channel) (0xC64 + ((channel) << 6))
718 #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007)
720 #define TX_CFG_A(channel) (0xD40 + ((channel) << 6))
722 #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000)
723 #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000)
726 #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00)
730 #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F)
734 #define TX_CFG_B(channel) (0xD44 + ((channel) << 6))
735 #define TX_CFG_B_TDMABL_512_ (0x00040000)
736 #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF)
738 #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6))
740 #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6))
742 #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6))
744 #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6))
746 #define TX_HEAD(channel) (0xD58 + ((channel) << 6))
748 #define TX_TAIL(channel) (0xD5C + ((channel) << 6))
753 #define TX_CFG_C(channel) (0xD64 + ((channel) << 6))
758 #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007)
760 #define OTP_PWR_DN (0x1000)
761 #define OTP_PWR_DN_PWRDN_N_ BIT(0)
763 #define OTP_ADDR_HIGH (0x1004)
764 #define OTP_ADDR_LOW (0x1008)
766 #define OTP_PRGM_DATA (0x1010)
768 #define OTP_PRGM_MODE (0x1014)
769 #define OTP_PRGM_MODE_BYTE_ BIT(0)
771 #define OTP_READ_DATA (0x1018)
773 #define OTP_FUNC_CMD (0x1020)
774 #define OTP_FUNC_CMD_READ_ BIT(0)
776 #define OTP_TST_CMD (0x1024)
779 #define OTP_CMD_GO (0x1028)
780 #define OTP_CMD_GO_GO_ BIT(0)
782 #define OTP_STATUS (0x1030)
783 #define OTP_STATUS_BUSY_ BIT(0)
788 #define HS_OTP_PWR_DN (HS_OTP_BLOCK_BASE + 0x0)
789 #define HS_OTP_ADDR_HIGH (HS_OTP_BLOCK_BASE + 0x4)
790 #define HS_OTP_ADDR_LOW (HS_OTP_BLOCK_BASE + 0x8)
791 #define HS_OTP_PRGM_DATA (HS_OTP_BLOCK_BASE + 0x10)
792 #define HS_OTP_PRGM_MODE (HS_OTP_BLOCK_BASE + 0x14)
793 #define HS_OTP_READ_DATA (HS_OTP_BLOCK_BASE + 0x18)
794 #define HS_OTP_FUNC_CMD (HS_OTP_BLOCK_BASE + 0x20)
795 #define HS_OTP_TST_CMD (HS_OTP_BLOCK_BASE + 0x24)
796 #define HS_OTP_CMD_GO (HS_OTP_BLOCK_BASE + 0x28)
797 #define HS_OTP_STATUS (HS_OTP_BLOCK_BASE + 0x30)
800 #define STAT_RX_FCS_ERRORS (0x1200)
801 #define STAT_RX_ALIGNMENT_ERRORS (0x1204)
802 #define STAT_RX_FRAGMENT_ERRORS (0x1208)
803 #define STAT_RX_JABBER_ERRORS (0x120C)
804 #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210)
805 #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214)
806 #define STAT_RX_DROPPED_FRAMES (0x1218)
807 #define STAT_RX_UNICAST_BYTE_COUNT (0x121C)
808 #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220)
809 #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224)
810 #define STAT_RX_UNICAST_FRAMES (0x1228)
811 #define STAT_RX_BROADCAST_FRAMES (0x122C)
812 #define STAT_RX_MULTICAST_FRAMES (0x1230)
813 #define STAT_RX_PAUSE_FRAMES (0x1234)
814 #define STAT_RX_64_BYTE_FRAMES (0x1238)
815 #define STAT_RX_65_127_BYTE_FRAMES (0x123C)
816 #define STAT_RX_128_255_BYTE_FRAMES (0x1240)
817 #define STAT_RX_256_511_BYTES_FRAMES (0x1244)
818 #define STAT_RX_512_1023_BYTE_FRAMES (0x1248)
819 #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C)
820 #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250)
821 #define STAT_RX_TOTAL_FRAMES (0x1254)
822 #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258)
823 #define STAT_EEE_RX_LPI_TIME (0x125C)
824 #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C)
826 #define STAT_TX_FCS_ERRORS (0x1280)
827 #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284)
828 #define STAT_TX_CARRIER_ERRORS (0x1288)
829 #define STAT_TX_BAD_BYTE_COUNT (0x128C)
830 #define STAT_TX_SINGLE_COLLISIONS (0x1290)
831 #define STAT_TX_MULTIPLE_COLLISIONS (0x1294)
832 #define STAT_TX_EXCESSIVE_COLLISION (0x1298)
833 #define STAT_TX_LATE_COLLISIONS (0x129C)
834 #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0)
835 #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4)
836 #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8)
837 #define STAT_TX_UNICAST_FRAMES (0x12AC)
838 #define STAT_TX_BROADCAST_FRAMES (0x12B0)
839 #define STAT_TX_MULTICAST_FRAMES (0x12B4)
840 #define STAT_TX_PAUSE_FRAMES (0x12B8)
841 #define STAT_TX_64_BYTE_FRAMES (0x12BC)
842 #define STAT_TX_65_127_BYTE_FRAMES (0x12C0)
843 #define STAT_TX_128_255_BYTE_FRAMES (0x12C4)
844 #define STAT_TX_256_511_BYTES_FRAMES (0x12C8)
845 #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC)
846 #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0)
847 #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4)
848 #define STAT_TX_TOTAL_FRAMES (0x12D8)
849 #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC)
850 #define STAT_EEE_TX_LPI_TIME (0x12E0)
851 #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC)
878 #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430)
879 #define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431)
880 #define PCI_DEVICE_ID_SMSC_A011 (0xA011)
881 #define PCI_DEVICE_ID_SMSC_A041 (0xA041)
883 #define PCI_CONFIG_LENGTH (0x1000)
886 #define CSR_LENGTH (0x2000)
888 #define LAN743X_CSR_FLAG_IS_A0 BIT(0)
902 #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0)
957 #define GPIO_QUEUE_STARTED (0)
962 #define TX_FRAME_FLAG_IN_PROGRESS BIT(0)
964 #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0)
1033 POWER_DOWN = 0,
1083 #define LAN743X_ADAPTER_FLAG_OTP BIT(0)
1093 #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index)
1098 #define MAC_MII_WRITE 0
1100 #define PHY_FLAG_OPENED BIT(0)
1104 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF))
1106 #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0))
1108 #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF))
1116 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0))
1117 #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0)
1118 #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0)
1120 #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1)
1123 #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000)
1124 #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000)
1125 #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000)
1126 #define TX_DESC_DATA0_FS_ (0x20000000)
1127 #define TX_DESC_DATA0_LS_ (0x10000000)
1128 #define TX_DESC_DATA0_EXT_ (0x08000000)
1129 #define TX_DESC_DATA0_IOC_ (0x04000000)
1130 #define TX_DESC_DATA0_ICE_ (0x00400000)
1131 #define TX_DESC_DATA0_IPE_ (0x00200000)
1132 #define TX_DESC_DATA0_TPE_ (0x00100000)
1133 #define TX_DESC_DATA0_FCS_ (0x00020000)
1134 #define TX_DESC_DATA0_TSE_ (0x00010000)
1135 #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF)
1136 #define TX_DESC_DATA0_EXT_LSO_ (0x00200000)
1137 #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF)
1138 #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000)
1147 #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
1161 #define RX_DESC_DATA0_OWN_ (0x00008000)
1163 #define RX_DESC_DATA0_FS_ (0x80000000)
1164 #define RX_DESC_DATA0_LS_ (0x40000000)
1165 #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000)
1168 #define RX_DESC_DATA0_EXT_ (0x00004000)
1169 #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF)
1170 #define RX_DESC_DATA1_STATUS_ICE_ (0x00020000)
1171 #define RX_DESC_DATA1_STATUS_TCE_ (0x00010000)
1172 #define RX_DESC_DATA1_STATUS_ICSM_ (0x00000001)
1173 #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF)
1175 #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2))
1176 #error NET_IP_ALIGN must be 0 or 2
1188 #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0)
1199 #define RX_PROCESS_RESULT_NOTHING_TO_DO (0)