60 static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val,  in regmap_encx24j600_sfr_read()  argument
64 	u8 banked_reg = reg & ADDR_MASK;  in regmap_encx24j600_sfr_read()
65 	u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);  in regmap_encx24j600_sfr_read()
71 	if (reg < 0x80) {  in regmap_encx24j600_sfr_read()
81 		switch (reg) {  in regmap_encx24j600_sfr_read()
104 		tx_buf[i++] = reg;  in regmap_encx24j600_sfr_read()
112 					u8 reg, u8 *val, size_t len,  in regmap_encx24j600_sfr_update()  argument
115 	u8 banked_reg = reg & ADDR_MASK;  in regmap_encx24j600_sfr_update()
116 	u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT);  in regmap_encx24j600_sfr_update()
120 				     { .tx_buf = &reg, .len = sizeof(reg), },  in regmap_encx24j600_sfr_update()
123 	if (reg < 0x80) {  in regmap_encx24j600_sfr_update()
135 		switch (reg) {  in regmap_encx24j600_sfr_update()
160 		t[1].tx_buf = &reg;  in regmap_encx24j600_sfr_update()
168 static int regmap_encx24j600_sfr_write(void *context, u8 reg, u8 *val,  in regmap_encx24j600_sfr_write()  argument
173 	return regmap_encx24j600_sfr_update(ctx, reg, val, len, WCRU, WCRCODE);  in regmap_encx24j600_sfr_write()
177 					  u8 reg, u8 val)  in regmap_encx24j600_sfr_set_bits()  argument
179 	return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFSU, BFSCODE);  in regmap_encx24j600_sfr_set_bits()
183 					  u8 reg, u8 val)  in regmap_encx24j600_sfr_clr_bits()  argument
185 	return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFCU, BFCCODE);  in regmap_encx24j600_sfr_clr_bits()
188 static int regmap_encx24j600_reg_update_bits(void *context, unsigned int reg,  in regmap_encx24j600_reg_update_bits()  argument
198 	if ((reg >= 0x40 && reg < 0x6c) || reg >= 0x80)  in regmap_encx24j600_reg_update_bits()
202 		ret = regmap_encx24j600_sfr_set_bits(ctx, reg, set_mask);  in regmap_encx24j600_reg_update_bits()
207 		ret = regmap_encx24j600_sfr_set_bits(ctx, reg + 1, set_mask);  in regmap_encx24j600_reg_update_bits()
210 		ret = regmap_encx24j600_sfr_clr_bits(ctx, reg, clr_mask);  in regmap_encx24j600_reg_update_bits()
215 		ret = regmap_encx24j600_sfr_clr_bits(ctx, reg + 1, clr_mask);  in regmap_encx24j600_reg_update_bits()
220 int regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data,  in regmap_encx24j600_spi_write()  argument
225 	if (reg < 0xc0)  in regmap_encx24j600_spi_write()
226 		return encx24j600_cmdn(ctx, reg, data, count);  in regmap_encx24j600_spi_write()
229 	return spi_write(ctx->spi, &reg, 1);  in regmap_encx24j600_spi_write()
233 int regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count)  in regmap_encx24j600_spi_read()  argument
237 	if (reg == RBSEL && count > 1)  in regmap_encx24j600_spi_read()
240 	return spi_write_then_read(ctx->spi, &reg, sizeof(reg), data, count);  in regmap_encx24j600_spi_read()
248 	u8 reg = dout[0];  in regmap_encx24j600_write()  local
252 	if (reg > 0xa0)  in regmap_encx24j600_write()
253 		return regmap_encx24j600_spi_write(context, reg, dout, len);  in regmap_encx24j600_write()
258 	return regmap_encx24j600_sfr_write(context, reg, dout, len);  in regmap_encx24j600_write()
265 	u8 reg = *(const u8 *)reg_buf;  in regmap_encx24j600_read()  local
268 		pr_err("%s: reg=%02x reg_size=%zu\n", __func__, reg, reg_size);  in regmap_encx24j600_read()
272 	if (reg > 0xa0)  in regmap_encx24j600_read()
273 		return regmap_encx24j600_spi_read(context, reg, val, val_size);  in regmap_encx24j600_read()
276 		pr_err("%s: reg=%02x val_size=%zu\n", __func__, reg, val_size);  in regmap_encx24j600_read()
280 	return regmap_encx24j600_sfr_read(context, reg, val, val_size);  in regmap_encx24j600_read()
283 static bool encx24j600_regmap_readable(struct device *dev, unsigned int reg)  in encx24j600_regmap_readable()  argument
285 	if ((reg < 0x36) ||  in encx24j600_regmap_readable()
286 	    ((reg >= 0x40) && (reg < 0x4c)) ||  in encx24j600_regmap_readable()
287 	    ((reg >= 0x52) && (reg < 0x56)) ||  in encx24j600_regmap_readable()
288 	    ((reg >= 0x60) && (reg < 0x66)) ||  in encx24j600_regmap_readable()
289 	    ((reg >= 0x68) && (reg < 0x80)) ||  in encx24j600_regmap_readable()
290 	    ((reg >= 0x86) && (reg < 0x92)) ||  in encx24j600_regmap_readable()
291 	    (reg == 0xc8))  in encx24j600_regmap_readable()
297 static bool encx24j600_regmap_writeable(struct device *dev, unsigned int reg)  in encx24j600_regmap_writeable()  argument
299 	if ((reg < 0x12) ||  in encx24j600_regmap_writeable()
300 	    ((reg >= 0x14) && (reg < 0x1a)) ||  in encx24j600_regmap_writeable()
301 	    ((reg >= 0x1c) && (reg < 0x36)) ||  in encx24j600_regmap_writeable()
302 	    ((reg >= 0x40) && (reg < 0x4c)) ||  in encx24j600_regmap_writeable()
303 	    ((reg >= 0x52) && (reg < 0x56)) ||  in encx24j600_regmap_writeable()
304 	    ((reg >= 0x60) && (reg < 0x68)) ||  in encx24j600_regmap_writeable()
305 	    ((reg >= 0x6c) && (reg < 0x80)) ||  in encx24j600_regmap_writeable()
306 	    ((reg >= 0x86) && (reg < 0x92)) ||  in encx24j600_regmap_writeable()
307 	    ((reg >= 0xc0) && (reg < 0xc8)) ||  in encx24j600_regmap_writeable()
308 	    ((reg >= 0xca) && (reg < 0xf0)))  in encx24j600_regmap_writeable()
314 static bool encx24j600_regmap_volatile(struct device *dev, unsigned int reg)  in encx24j600_regmap_volatile()  argument
316 	switch (reg) {  in encx24j600_regmap_volatile()
335 static bool encx24j600_regmap_precious(struct device *dev, unsigned int reg)  in encx24j600_regmap_precious()  argument
338 	if (((reg >= 0xc0) && (reg < 0xc8)) ||  in encx24j600_regmap_precious()
339 	    ((reg >= 0xca) && (reg < 0xf0)))  in encx24j600_regmap_precious()
345 static int regmap_encx24j600_phy_reg_read(void *context, unsigned int reg,  in regmap_encx24j600_phy_reg_read()  argument
352 	reg = MIREGADR_VAL | (reg & PHREG_MASK);  in regmap_encx24j600_phy_reg_read()
353 	ret = regmap_write(ctx->regmap, MIREGADR, reg);  in regmap_encx24j600_phy_reg_read()
377 		pr_err("%s: error %d reading reg %02x\n", __func__, ret,  in regmap_encx24j600_phy_reg_read()
378 		       reg & PHREG_MASK);  in regmap_encx24j600_phy_reg_read()
383 static int regmap_encx24j600_phy_reg_write(void *context, unsigned int reg,  in regmap_encx24j600_phy_reg_write()  argument
390 	reg = MIREGADR_VAL | (reg & PHREG_MASK);  in regmap_encx24j600_phy_reg_write()
391 	ret = regmap_write(ctx->regmap, MIREGADR, reg);  in regmap_encx24j600_phy_reg_write()
406 		pr_err("%s: error %d writing reg %02x=%04x\n", __func__, ret,  in regmap_encx24j600_phy_reg_write()
407 		       reg & PHREG_MASK, val);  in regmap_encx24j600_phy_reg_write()
412 static bool encx24j600_phymap_readable(struct device *dev, unsigned int reg)  in encx24j600_phymap_readable()  argument
414 	switch (reg) {  in encx24j600_phymap_readable()
429 static bool encx24j600_phymap_writeable(struct device *dev, unsigned int reg)  in encx24j600_phymap_writeable()  argument
431 	switch (reg) {  in encx24j600_phymap_writeable()
446 static bool encx24j600_phymap_volatile(struct device *dev, unsigned int reg)  in encx24j600_phymap_volatile()  argument
448 	switch (reg) {  in encx24j600_phymap_volatile()
462 	.name = "reg",