Lines Matching +full:0 +full:x262
16 #define MIN_FW_MAJOR_VERSION 0
23 #define PCI_DEVICE_ID_META_FBNIC_ASIC 0x0013
29 #define FBNIC_TWD_L2_HLEN_MASK DESC_GENMASK(5, 0)
33 FBNIC_TWD_L3_TYPE_OTHER = 0,
43 FBNIC_TWD_L4_TYPE_OTHER = 0,
62 FBNIC_TWD_TYPE_META = 0,
71 #define FBNIC_TWD_TS_MASK DESC_GENMASK(39, 0)
72 #define FBNIC_TWD_ADDR_MASK DESC_GENMASK(45, 0)
76 #define FBNIC_TCD_TYPE0_HEAD0_MASK DESC_GENMASK(15, 0)
79 #define FBNIC_TCD_TYPE1_TS_MASK DESC_GENMASK(39, 0)
87 FBNIC_TCD_TYPE_0 = 0,
99 * address with the lowest 12 bits being reserved 0 due to the fact that
127 FBNIC_RCD_TYPE_HDR_AL = 0,
136 #define FBNIC_RCD_AL_BUFF_ID_MASK DESC_GENMASK(15, 0)
148 FBNIC_RCD_HDR_AL_DMA_HINT_NONE = 0,
155 #define FBNIC_RCD_OPT_META_TS_MASK DESC_GENMASK(39, 0)
162 #define FBNIC_RCD_META_RSS_HASH_MASK DESC_GENMASK(31, 0)
166 FBNIC_RCD_META_L3_TYPE_OTHER = 0,
174 FBNIC_RCD_META_L4_TYPE_OTHER = 0,
196 #define FBNIC_CSR_START_INTR 0x00000 /* CSR section delimiter */
197 #define FBNIC_INTR_STATUS(n) (0x00000 + (n)) /* 0x00000 + 4*n */
199 #define FBNIC_INTR_MASK(n) (0x00008 + (n)) /* 0x00020 + 4*n */
201 #define FBNIC_INTR_SET(n) (0x00010 + (n)) /* 0x00040 + 4*n */
203 #define FBNIC_INTR_CLEAR(n) (0x00018 + (n)) /* 0x00060 + 4*n */
205 #define FBNIC_INTR_SW_STATUS(n) (0x00020 + (n)) /* 0x00080 + 4*n */
207 #define FBNIC_INTR_SW_AC_MODE(n) (0x00028 + (n)) /* 0x000a0 + 4*n */
209 #define FBNIC_INTR_MASK_SET(n) (0x00030 + (n)) /* 0x000c0 + 4*n */
211 #define FBNIC_INTR_MASK_CLEAR(n) (0x00038 + (n)) /* 0x000e0 + 4*n */
214 #define FBNIC_INTR_MSIX_CTRL(n) (0x00040 + (n)) /* 0x00100 + 4*n */
215 #define FBNIC_INTR_MSIX_CTRL_VECTOR_MASK CSR_GENMASK(7, 0)
221 #define FBNIC_CSR_END_INTR 0x0005f /* CSR section delimiter */
224 #define FBNIC_CSR_START_INTR_CQ 0x00400 /* CSR section delimiter */
226 (0x00400 + 4 * (n)) /* 0x01000 + 16*n */
228 #define FBNIC_INTR_CQ_REARM_RCQ_TIMEOUT CSR_GENMASK(13, 0)
236 (0x00401 + 4 * (n)) /* 0x01004 + 16*n */
239 (0x00402 + 4 * (n)) /* 0x01008 + 16*n */
241 #define FBNIC_CSR_END_INTR_CQ 0x007fe /* CSR section delimiter */
244 #define FBNIC_CSR_START_QM_TX 0x00800 /* CSR section delimiter */
245 #define FBNIC_QM_TWQ_IDLE(n) (0x00800 + (n)) /* 0x02000 + 4*n */
247 #define FBNIC_QM_TWQ_DEFAULT_META_L 0x00818 /* 0x02060 */
248 #define FBNIC_QM_TWQ_DEFAULT_META_H 0x00819 /* 0x02064 */
250 #define FBNIC_QM_TQS_CTL0 0x0081b /* 0x0206c */
251 #define FBNIC_QM_TQS_CTL0_LSO_TS_MASK CSR_BIT(0)
253 FBNIC_QM_TQS_CTL0_LSO_TS_FIRST = 0,
262 #define FBNIC_QM_TQS_CTL1 0x0081c /* 0x02070 */
263 #define FBNIC_QM_TQS_CTL1_MC_MAX_CREDITS CSR_GENMASK(7, 0)
265 #define FBNIC_QM_TQS_MTU_CTL0 0x0081d /* 0x02074 */
266 #define FBNIC_QM_TQS_MTU_CTL1 0x0081e /* 0x02078 */
267 #define FBNIC_QM_TQS_MTU_CTL1_BULK CSR_GENMASK(13, 0)
268 #define FBNIC_QM_TCQ_IDLE(n) (0x00821 + (n)) /* 0x02084 + 4*n */
270 #define FBNIC_QM_TCQ_CTL0 0x0082d /* 0x020b4 */
271 #define FBNIC_QM_TCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0)
273 #define FBNIC_QM_TQS_IDLE(n) (0x00830 + (n)) /* 0x020c0 + 4*n */
275 #define FBNIC_QM_TQS_EDT_TS_RANGE 0x00849 /* 0x2124 */
276 #define FBNIC_QM_TDE_IDLE(n) (0x00853 + (n)) /* 0x0214c + 4*n */
278 #define FBNIC_QM_TNI_TDF_CTL 0x0086c /* 0x021b0 */
279 #define FBNIC_QM_TNI_TDF_CTL_MRRS CSR_GENMASK(1, 0)
283 #define FBNIC_QM_TNI_TDE_CTL 0x0086d /* 0x021b4 */
284 #define FBNIC_QM_TNI_TDE_CTL_MRRS CSR_GENMASK(1, 0)
289 #define FBNIC_QM_TNI_TCM_CTL 0x0086e /* 0x021b8 */
290 #define FBNIC_QM_TNI_TCM_CTL_MPS CSR_GENMASK(1, 0)
294 #define FBNIC_CSR_END_QM_TX 0x00873 /* CSR section delimiter */
297 #define FBNIC_CSR_START_QM_RX 0x00c00 /* CSR section delimiter */
298 #define FBNIC_QM_RCQ_IDLE(n) (0x00c00 + (n)) /* 0x03000 + 4*n */
300 #define FBNIC_QM_RCQ_CTL0 0x00c0c /* 0x03030 */
301 #define FBNIC_QM_RCQ_CTL0_COAL_WAIT CSR_GENMASK(15, 0)
303 #define FBNIC_QM_HPQ_IDLE(n) (0x00c0f + (n)) /* 0x0303c + 4*n */
305 #define FBNIC_QM_PPQ_IDLE(n) (0x00c13 + (n)) /* 0x0304c + 4*n */
307 #define FBNIC_QM_RNI_RBP_CTL 0x00c2d /* 0x030b4 */
308 #define FBNIC_QM_RNI_RBP_CTL_MRRS CSR_GENMASK(1, 0)
312 #define FBNIC_QM_RNI_RDE_CTL 0x00c2e /* 0x030b8 */
313 #define FBNIC_QM_RNI_RDE_CTL_MPS CSR_GENMASK(1, 0)
317 #define FBNIC_QM_RNI_RCM_CTL 0x00c2f /* 0x030bc */
318 #define FBNIC_QM_RNI_RCM_CTL_MPS CSR_GENMASK(1, 0)
322 #define FBNIC_CSR_END_QM_RX 0x00c34 /* CSR section delimiter */
325 #define FBNIC_CSR_START_TCE 0x04000 /* CSR section delimiter */
326 #define FBNIC_TCE_REG_BASE 0x04000 /* 0x10000 */
328 #define FBNIC_TCE_LSO_CTRL 0x04000 /* 0x10000 */
329 #define FBNIC_TCE_LSO_CTRL_TCPF_CLR_1ST CSR_GENMASK(8, 0)
334 #define FBNIC_TCE_CSO_CTRL 0x04001 /* 0x10004 */
335 #define FBNIC_TCE_CSO_CTRL_TCP_ZERO_CSUM CSR_BIT(0)
337 #define FBNIC_TCE_TXB_CTRL 0x04002 /* 0x10008 */
338 #define FBNIC_TCE_TXB_CTRL_LOAD CSR_BIT(0)
342 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL 0x04003 /* 0x1000c */
343 #define FBNIC_TCE_TXB_ENQ_WRR_CTRL_WEIGHT0 CSR_GENMASK(7, 0)
347 #define FBNIC_TCE_TXB_TEI_Q0_CTRL 0x04004 /* 0x10010 */
348 #define FBNIC_TCE_TXB_TEI_Q1_CTRL 0x04005 /* 0x10014 */
349 #define FBNIC_TCE_TXB_MC_Q_CTRL 0x04006 /* 0x10018 */
350 #define FBNIC_TCE_TXB_RX_TEI_Q_CTRL 0x04007 /* 0x1001c */
351 #define FBNIC_TCE_TXB_RX_BMC_Q_CTRL 0x04008 /* 0x10020 */
352 #define FBNIC_TCE_TXB_Q_CTRL_START CSR_GENMASK(10, 0)
355 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL 0x04009 /* 0x10024 */
356 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0)
358 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL 0x0400a /* 0x10028 */
359 #define FBNIC_TCE_TXB_NTWRK_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0)
363 #define FBNIC_TCE_TXB_CLDR_CFG 0x0400b /* 0x1002c */
364 #define FBNIC_TCE_TXB_CLDR_CFG_NUM_SLOT CSR_GENMASK(5, 0)
365 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG(n) (0x0400c + (n)) /* 0x10030 + 4*n */
367 #define FBNIC_TCE_TXB_CLDR_SLOT_CFG_DEST_ID_0_0 CSR_GENMASK(1, 0)
384 #define FBNIC_TCE_BMC_MAX_PKTSZ 0x0403a /* 0x100e8 */
385 #define FBNIC_TCE_BMC_MAX_PKTSZ_TX CSR_GENMASK(13, 0)
387 #define FBNIC_TCE_MC_MAX_PKTSZ 0x0403b /* 0x100ec */
388 #define FBNIC_TCE_MC_MAX_PKTSZ_TMI CSR_GENMASK(13, 0)
390 #define FBNIC_TCE_SOP_PROT_CTRL 0x0403c /* 0x100f0 */
391 #define FBNIC_TCE_SOP_PROT_CTRL_TBI CSR_GENMASK(7, 0)
395 #define FBNIC_TCE_DROP_CTRL 0x0403d /* 0x100f4 */
396 #define FBNIC_TCE_DROP_CTRL_TTI_CM_DROP_EN CSR_BIT(0)
400 #define FBNIC_TCE_TXB_TX_BMC_Q_CTRL 0x0404B /* 0x1012c */
401 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL 0x0404C /* 0x10130 */
402 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_QUANTUM0 CSR_GENMASK(7, 0)
404 #define FBNIC_TCE_TXB_TEI_DWRR_CTRL_EXT 0x0404D /* 0x10134 */
406 0x0404E /* 0x10138 */
407 #define FBNIC_TCE_TXB_BMC_DWRR_CTRL_EXT 0x0404F /* 0x1013c */
408 #define FBNIC_CSR_END_TCE 0x04050 /* CSR section delimiter */
411 #define FBNIC_CSR_START_TMI 0x04400 /* CSR section delimiter */
412 #define FBNIC_TMI_SOP_PROT_CTRL 0x04400 /* 0x11000 */
413 #define FBNIC_TMI_DROP_CTRL 0x04401 /* 0x11004 */
414 #define FBNIC_TMI_DROP_CTRL_EN CSR_BIT(0)
415 #define FBNIC_CSR_END_TMI 0x0443f /* CSR section delimiter */
417 #define FBNIC_CSR_START_RXB 0x08000 /* CSR section delimiter */
419 FBNIC_RXB_FIFO_MC = 0,
430 #define FBNIC_RXB_CT_SIZE(n) (0x08000 + (n)) /* 0x20000 + 4*n */
432 #define FBNIC_RXB_CT_SIZE_HEADER CSR_GENMASK(5, 0)
435 #define FBNIC_RXB_PAUSE_DROP_CTRL 0x08008 /* 0x20020 */
436 #define FBNIC_RXB_PAUSE_DROP_CTRL_DROP_ENABLE CSR_GENMASK(7, 0)
440 #define FBNIC_RXB_PAUSE_THLD(n) (0x08009 + (n)) /* 0x20024 + 4*n */
442 #define FBNIC_RXB_PAUSE_THLD_ON CSR_GENMASK(12, 0)
444 #define FBNIC_RXB_DROP_THLD(n) (0x08011 + (n)) /* 0x20044 + 4*n */
446 #define FBNIC_RXB_DROP_THLD_ON CSR_GENMASK(12, 0)
448 #define FBNIC_RXB_ECN_THLD(n) (0x0801e + (n)) /* 0x20078 + 4*n */
450 #define FBNIC_RXB_ECN_THLD_ON CSR_GENMASK(12, 0)
452 #define FBNIC_RXB_PBUF_CFG(n) (0x08027 + (n)) /* 0x2009c + 4*n */
454 #define FBNIC_RXB_PBUF_BASE_ADDR CSR_GENMASK(12, 0)
456 #define FBNIC_RXB_DWRR_RDE_WEIGHT0 0x0802f /* 0x200bc */
457 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_QUANTUM0 CSR_GENMASK(7, 0)
461 #define FBNIC_RXB_DWRR_RDE_WEIGHT1 0x08030 /* 0x200c0 */
462 #define FBNIC_RXB_DWRR_RDE_WEIGHT1_QUANTUM4 CSR_GENMASK(7, 0)
463 #define FBNIC_RXB_DWRR_BMC_WEIGHT 0x08031 /* 0x200c4 */
464 #define FBNIC_RXB_CLDR_PRIO_CFG(n) (0x8034 + (n)) /* 0x200d0 + 4*n */
466 #define FBNIC_RXB_ENDIAN_FCS 0x08044 /* 0x20110 */
475 #define FBNIC_RXB_PBUF_CREDIT(n) (0x08047 + (n)) /* 0x2011C + 4*n */
477 #define FBNIC_RXB_PBUF_CREDIT_MASK CSR_GENMASK(13, 0)
478 #define FBNIC_RXB_INTF_CREDIT 0x0804f /* 0x2013C */
479 #define FBNIC_RXB_INTF_CREDIT_MASK0 CSR_GENMASK(3, 0)
484 #define FBNIC_RXB_PAUSE_EVENT_CNT(n) (0x08053 + (n)) /* 0x2014c + 4*n */
485 #define FBNIC_RXB_DROP_FRMS_STS(n) (0x08057 + (n)) /* 0x2015c + 4*n */
487 (0x08080 + 2 * (n)) /* 0x20200 + 8*n */
489 (0x08081 + 2 * (n)) /* 0x20204 + 8*n */
490 #define FBNIC_RXB_TRUN_FRMS_STS(n) (0x08091 + (n)) /* 0x20244 + 4*n */
492 (0x080c0 + 2 * (n)) /* 0x20300 + 8*n */
494 (0x080c1 + 2 * (n)) /* 0x20304 + 8*n */
495 #define FBNIC_RXB_TRANS_PAUSE_STS(n) (0x080d1 + (n)) /* 0x20344 + 4*n */
496 #define FBNIC_RXB_TRANS_DROP_STS(n) (0x080d9 + (n)) /* 0x20364 + 4*n */
497 #define FBNIC_RXB_TRANS_ECN_STS(n) (0x080e1 + (n)) /* 0x20384 + 4*n */
499 FBNIC_RXB_ENQUEUE_NET = 0,
506 #define FBNIC_RXB_DRBO_FRM_CNT_SRC(n) (0x080f9 + (n)) /* 0x203e4 + 4*n */
508 (0x080fd + (n)) /* 0x203f4 + 4*n */
510 (0x08101 + (n)) /* 0x20404 + 4*n */
511 #define FBNIC_RXB_INTF_FRM_CNT_DST(n) (0x08105 + (n)) /* 0x20414 + 4*n */
513 (0x08109 + (n)) /* 0x20424 + 4*n */
515 (0x0810d + (n)) /* 0x20434 + 4*n */
516 #define FBNIC_RXB_PBUF_FRM_CNT_DST(n) (0x08111 + (n)) /* 0x20444 + 4*n */
518 (0x08115 + (n)) /* 0x20454 + 4*n */
520 (0x08119 + (n)) /* 0x20464 + 4*n */
522 #define FBNIC_RXB_PBUF_FIFO_LEVEL(n) (0x0811d + (n)) /* 0x20474 + 4*n */
524 #define FBNIC_RXB_INTEGRITY_ERR(n) (0x0812f + (n)) /* 0x204bc + 4*n */
525 #define FBNIC_RXB_MAC_ERR(n) (0x08133 + (n)) /* 0x204cc + 4*n */
526 #define FBNIC_RXB_PARSER_ERR(n) (0x08137 + (n)) /* 0x204dc + 4*n */
527 #define FBNIC_RXB_FRM_ERR(n) (0x0813b + (n)) /* 0x204ec + 4*n */
529 #define FBNIC_RXB_DWRR_RDE_WEIGHT0_EXT 0x08143 /* 0x2050c */
530 #define FBNIC_RXB_DWRR_RDE_WEIGHT1_EXT 0x08144 /* 0x20510 */
531 #define FBNIC_CSR_END_RXB 0x081b1 /* CSR section delimiter */
534 #define FBNIC_CSR_START_RPC 0x08400 /* CSR section delimiter */
535 #define FBNIC_RPC_RMI_CONFIG 0x08400 /* 0x21000 */
536 #define FBNIC_RPC_RMI_CONFIG_OH_BYTES CSR_GENMASK(4, 0)
541 #define FBNIC_RPC_ACT_TBL0_DEFAULT 0x0840a /* 0x21028 */
542 #define FBNIC_RPC_ACT_TBL0_DROP CSR_BIT(0)
553 #define FBNIC_RPC_ACT_TBL1_DEFAULT 0x0840b /* 0x2102c */
554 #define FBNIC_RPC_ACT_TBL1_RSS_ENA_MASK CSR_GENMASK(15, 0)
569 #define FBNIC_RPC_RSS_KEY(n) (0x0840c + (n)) /* 0x21030 + 4*n */
582 #define FBNIC_RPC_TCAM_MACDA_VALIDATE 0x0852d /* 0x214b4 */
583 #define FBNIC_CSR_END_RPC 0x0856b /* CSR section delimiter */
587 #define FBNIC_CSR_START_RPC_RAM 0x08800 /* CSR section delimiter */
588 #define FBNIC_RPC_ACT_TBL0(n) (0x08800 + (n)) /* 0x22000 + 4*n */
589 #define FBNIC_RPC_ACT_TBL1(n) (0x08840 + (n)) /* 0x22100 + 4*n */
599 (0x08880 + 0x40 * (n) + (m)) /* 0x22200 + 256*n + 4*m */
601 #define FBNIC_RPC_TCAM_ACT_VALUE CSR_GENMASK(15, 0)
605 (0x08b80 + 0x20 * (n) + (m)) /* 0x022e00 + 128*n + 4*m */
606 #define FBNIC_RPC_TCAM_MACDA_VALUE CSR_GENMASK(15, 0)
610 (0x08d20 + 0x100 * (n) + (m)) /* 0x023480 + 1024*n + 4*m */
613 #define FBNIC_CSR_END_RPC_RAM 0x08f1f /* CSR section delimiter */
616 #define FBNIC_CSR_START_FAB 0x0C000 /* CSR section delimiter */
617 #define FBNIC_FAB_AXI4_AR_SPACER_2_CFG 0x0C005 /* 0x30014 */
619 #define FBNIC_FAB_AXI4_AR_SPACER_THREADSHOLD CSR_GENMASK(15, 0)
620 #define FBNIC_CSR_END_FAB 0x0C020 /* CSR section delimiter */
623 #define FBNIC_CSR_START_MASTER 0x0C400 /* CSR section delimiter */
624 #define FBNIC_MASTER_SPARE_0 0x0C41B /* 0x3106c */
625 #define FBNIC_CSR_END_MASTER 0x0C452 /* CSR section delimiter */
628 #define FBNIC_CSR_START_MAC_MAC 0x11000 /* CSR section delimiter */
629 #define FBNIC_MAC_COMMAND_CONFIG 0x11002 /* 0x44008 */
637 #define FBNIC_MAC_COMMAND_CONFIG_TX_ENA CSR_BIT(0)
638 #define FBNIC_MAC_CL01_PAUSE_QUANTA 0x11015 /* 0x44054 */
639 #define FBNIC_MAC_CL01_QUANTA_THRESH 0x11019 /* 0x44064 */
640 #define FBNIC_CSR_END_MAC_MAC 0x11028 /* CSR section delimiter */
643 #define FBNIC_CSR_START_SIG 0x11800 /* CSR section delimiter */
644 #define FBNIC_SIG_MAC_IN0 0x11800 /* 0x46000 */
651 #define FBNIC_SIG_PCS_OUT0 0x11808 /* 0x46020 */
655 #define FBNIC_SIG_PCS_OUT1 0x11809 /* 0x46024 */
657 #define FBNIC_SIG_PCS_INTR_STS 0x11814 /* 0x46050 */
659 #define FBNIC_SIG_PCS_INTR_LINK_UP CSR_BIT(0)
660 #define FBNIC_SIG_PCS_INTR_MASK 0x11816 /* 0x46058 */
661 #define FBNIC_CSR_END_SIG 0x1184e /* CSR section delimiter */
663 #define FBNIC_CSR_START_MAC_STAT 0x11a00
664 #define FBNIC_MAC_STAT_RX_BYTE_COUNT_L 0x11a08 /* 0x46820 */
665 #define FBNIC_MAC_STAT_RX_BYTE_COUNT_H 0x11a09 /* 0x46824 */
667 0x11a0a /* 0x46828 */
669 0x11a0b /* 0x4682c */
670 #define FBNIC_MAC_STAT_RX_TOOLONG_L 0x11a0e /* 0x46838 */
671 #define FBNIC_MAC_STAT_RX_TOOLONG_H 0x11a0f /* 0x4683c */
673 0x11a12 /* 0x46848 */
675 0x11a13 /* 0x4684c */
677 0x11a14 /* 0x46850 */
679 0x11a15 /* 0x46854 */
680 #define FBNIC_MAC_STAT_RX_IFINERRORS_L 0x11a18 /* 0x46860 */
681 #define FBNIC_MAC_STAT_RX_IFINERRORS_H 0x11a19 /* 0x46864 */
682 #define FBNIC_MAC_STAT_RX_MULTICAST_L 0x11a1c /* 0x46870 */
683 #define FBNIC_MAC_STAT_RX_MULTICAST_H 0x11a1d /* 0x46874 */
684 #define FBNIC_MAC_STAT_RX_BROADCAST_L 0x11a1e /* 0x46878 */
685 #define FBNIC_MAC_STAT_RX_BROADCAST_H 0x11a1f /* 0x4687c */
686 #define FBNIC_MAC_STAT_TX_BYTE_COUNT_L 0x11a3e /* 0x468f8 */
687 #define FBNIC_MAC_STAT_TX_BYTE_COUNT_H 0x11a3f /* 0x468fc */
689 0x11a42 /* 0x46908 */
691 0x11a43 /* 0x4690c */
693 0x11a46 /* 0x46918 */
695 0x11a47 /* 0x4691c */
696 #define FBNIC_MAC_STAT_TX_MULTICAST_L 0x11a4a /* 0x46928 */
697 #define FBNIC_MAC_STAT_TX_MULTICAST_H 0x11a4b /* 0x4692c */
698 #define FBNIC_MAC_STAT_TX_BROADCAST_L 0x11a4c /* 0x46930 */
699 #define FBNIC_MAC_STAT_TX_BROADCAST_H 0x11a4d /* 0x46934 */
701 #define FBNIC_CSR_START_PUL_USER 0x31000 /* CSR section delimiter */
702 #define FBNIC_PUL_OB_TLP_HDR_AW_CFG 0x3103d /* 0xc40f4 */
704 #define FBNIC_PUL_OB_TLP_HDR_AR_CFG 0x3103e /* 0xc40f8 */
706 #define FBNIC_CSR_END_PUL_USER 0x31080 /* CSR section delimiter */
715 #define FBNIC_CSR_START_QUEUE 0x40000 /* CSR section delimiter */
716 #define FBNIC_QUEUE_STRIDE 0x400 /* 0x1000 */
718 (0x40000 + FBNIC_QUEUE_STRIDE * (n)) /* 0x100000 + 4096*n */
720 #define FBNIC_QUEUE_TWQ0_CTL 0x000 /* 0x000 */
721 #define FBNIC_QUEUE_TWQ1_CTL 0x001 /* 0x004 */
722 #define FBNIC_QUEUE_TWQ_CTL_RESET CSR_BIT(0)
724 #define FBNIC_QUEUE_TWQ0_TAIL 0x002 /* 0x008 */
725 #define FBNIC_QUEUE_TWQ1_TAIL 0x003 /* 0x00c */
727 #define FBNIC_QUEUE_TWQ0_SIZE 0x00a /* 0x028 */
728 #define FBNIC_QUEUE_TWQ1_SIZE 0x00b /* 0x02c */
729 #define FBNIC_QUEUE_TWQ_SIZE_MASK CSR_GENMASK(3, 0)
731 #define FBNIC_QUEUE_TWQ0_BAL 0x020 /* 0x080 */
733 #define FBNIC_QUEUE_TWQ0_BAH 0x021 /* 0x084 */
734 #define FBNIC_QUEUE_TWQ1_BAL 0x022 /* 0x088 */
735 #define FBNIC_QUEUE_TWQ1_BAH 0x023 /* 0x08c */
738 #define FBNIC_QUEUE_TCQ_CTL 0x080 /* 0x200 */
739 #define FBNIC_QUEUE_TCQ_CTL_RESET CSR_BIT(0)
742 #define FBNIC_QUEUE_TCQ_HEAD 0x081 /* 0x204 */
744 #define FBNIC_QUEUE_TCQ_SIZE 0x084 /* 0x210 */
745 #define FBNIC_QUEUE_TCQ_SIZE_MASK CSR_GENMASK(3, 0)
747 #define FBNIC_QUEUE_TCQ_BAL 0x0a0 /* 0x280 */
748 #define FBNIC_QUEUE_TCQ_BAH 0x0a1 /* 0x284 */
751 #define FBNIC_QUEUE_TIM_CTL 0x0c0 /* 0x300 */
752 #define FBNIC_QUEUE_TIM_CTL_MSIX_MASK CSR_GENMASK(7, 0)
754 #define FBNIC_QUEUE_TIM_THRESHOLD 0x0c1 /* 0x304 */
755 #define FBNIC_QUEUE_TIM_THRESHOLD_TWD_MASK CSR_GENMASK(14, 0)
757 #define FBNIC_QUEUE_TIM_CLEAR 0x0c2 /* 0x308 */
758 #define FBNIC_QUEUE_TIM_CLEAR_MASK CSR_BIT(0)
759 #define FBNIC_QUEUE_TIM_SET 0x0c3 /* 0x30c */
760 #define FBNIC_QUEUE_TIM_SET_MASK CSR_BIT(0)
761 #define FBNIC_QUEUE_TIM_MASK 0x0c4 /* 0x310 */
762 #define FBNIC_QUEUE_TIM_MASK_MASK CSR_BIT(0)
764 #define FBNIC_QUEUE_TIM_TIMER 0x0c5 /* 0x314 */
766 #define FBNIC_QUEUE_TIM_COUNTS 0x0c6 /* 0x318 */
768 #define FBNIC_QUEUE_TIM_COUNTS_CNT0_MASK CSR_GENMASK(14, 0)
771 #define FBNIC_QUEUE_RCQ_CTL 0x200 /* 0x800 */
772 #define FBNIC_QUEUE_RCQ_CTL_RESET CSR_BIT(0)
775 #define FBNIC_QUEUE_RCQ_HEAD 0x201 /* 0x804 */
777 #define FBNIC_QUEUE_RCQ_SIZE 0x204 /* 0x810 */
778 #define FBNIC_QUEUE_RCQ_SIZE_MASK CSR_GENMASK(3, 0)
780 #define FBNIC_QUEUE_RCQ_BAL 0x220 /* 0x880 */
781 #define FBNIC_QUEUE_RCQ_BAH 0x221 /* 0x884 */
784 #define FBNIC_QUEUE_BDQ_CTL 0x240 /* 0x900 */
785 #define FBNIC_QUEUE_BDQ_CTL_RESET CSR_BIT(0)
789 #define FBNIC_QUEUE_BDQ_HPQ_TAIL 0x241 /* 0x904 */
790 #define FBNIC_QUEUE_BDQ_PPQ_TAIL 0x242 /* 0x908 */
792 #define FBNIC_QUEUE_BDQ_HPQ_SIZE 0x247 /* 0x91c */
793 #define FBNIC_QUEUE_BDQ_PPQ_SIZE 0x248 /* 0x920 */
794 #define FBNIC_QUEUE_BDQ_SIZE_MASK CSR_GENMASK(3, 0)
796 #define FBNIC_QUEUE_BDQ_HPQ_BAL 0x260 /* 0x980 */
797 #define FBNIC_QUEUE_BDQ_HPQ_BAH 0x261 /* 0x984 */
798 #define FBNIC_QUEUE_BDQ_PPQ_BAL 0x262 /* 0x988 */
799 #define FBNIC_QUEUE_BDQ_PPQ_BAH 0x263 /* 0x98c */
802 #define FBNIC_QUEUE_RDE_CTL0 0x2a0 /* 0xa80 */
806 FBNIC_QUEUE_RDE_CTL0_DROP_IMMEDIATE = 0,
814 #define FBNIC_QUEUE_RDE_CTL1 0x2a1 /* 0xa84 */
819 #define FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_MASK CSR_GENMASK(1, 0)
821 FBNIC_QUEUE_RDE_CTL1_PAYLD_PACK_NONE = 0,
827 #define FBNIC_QUEUE_RIM_CTL 0x2c0 /* 0xb00 */
828 #define FBNIC_QUEUE_RIM_CTL_MSIX_MASK CSR_GENMASK(7, 0)
830 #define FBNIC_QUEUE_RIM_THRESHOLD 0x2c1 /* 0xb04 */
831 #define FBNIC_QUEUE_RIM_THRESHOLD_RCD_MASK CSR_GENMASK(14, 0)
833 #define FBNIC_QUEUE_RIM_CLEAR 0x2c2 /* 0xb08 */
834 #define FBNIC_QUEUE_RIM_CLEAR_MASK CSR_BIT(0)
835 #define FBNIC_QUEUE_RIM_SET 0x2c3 /* 0xb0c */
836 #define FBNIC_QUEUE_RIM_SET_MASK CSR_BIT(0)
837 #define FBNIC_QUEUE_RIM_MASK 0x2c4 /* 0xb10 */
838 #define FBNIC_QUEUE_RIM_MASK_MASK CSR_BIT(0)
840 #define FBNIC_QUEUE_RIM_COAL_STATUS 0x2c5 /* 0xb14 */
842 #define FBNIC_QUEUE_RIM_TIMER_MASK CSR_GENMASK(13, 0)
844 #define FBNIC_CSR_END_QUEUE (0x40000 + 0x400 * FBNIC_MAX_QUEUES - 1)
852 * Currently we use an offset of 0x6000 on BAR4 for the mailbox so we just
858 ((((mbx_idx) * FBNIC_IPC_MBX_DESC_LEN + (desc_idx)) * 2) + 0x6000)
861 #define FBNIC_FW_ZERO_REG FBNIC_IPC_MBX(0, 0)
873 #define FBNIC_IPC_MBX_DESC_HOST_CMPL DESC_BIT(0)