Lines Matching +full:0 +full:x01c
37 MTK_WED_WO_EVT_LOG_DUMP = 0x1,
38 MTK_WED_WO_EVT_PROFILING = 0x2,
39 MTK_WED_WO_EVT_RXCNT_INFO = 0x3,
47 MTK_WED_WARP_CMD_FLAG_RSP = BIT(0),
52 #define MTK_WED_WO_CPU_MCUSYS_RESET_ADDR 0x15194050
53 #define MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK 0x20
54 #define MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK 0x1
97 #define MTK_WO_MCU_CFG_LS_BASE 0
98 #define MTK_WO_MCU_CFG_LS_HW_VER_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x000)
99 #define MTK_WO_MCU_CFG_LS_FW_VER_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x004)
100 #define MTK_WO_MCU_CFG_LS_CFG_DBG1_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x00c)
101 #define MTK_WO_MCU_CFG_LS_CFG_DBG2_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x010)
102 #define MTK_WO_MCU_CFG_LS_WF_MCCR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x014)
103 #define MTK_WO_MCU_CFG_LS_WF_MCCR_SET_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x018)
104 #define MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x01c)
105 #define MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x050)
106 #define MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x060)
107 #define MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x064)
110 #define MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK BIT(0)
115 #define MTK_WED_WO_TXCH_NUM 0
119 #define MTK_WED_WO_TXCH_INT_MASK BIT(0)
125 #define MTK_WED_WO_CCIF_BUSY 0x004
126 #define MTK_WED_WO_CCIF_START 0x008
127 #define MTK_WED_WO_CCIF_TCHNUM 0x00c
128 #define MTK_WED_WO_CCIF_RCHNUM 0x010
129 #define MTK_WED_WO_CCIF_RCHNUM_MASK GENMASK(7, 0)
131 #define MTK_WED_WO_CCIF_ACK 0x014
132 #define MTK_WED_WO_CCIF_IRQ0_MASK 0x018
133 #define MTK_WED_WO_CCIF_IRQ1_MASK 0x01c
134 #define MTK_WED_WO_CCIF_DUMMY1 0x020
135 #define MTK_WED_WO_CCIF_DUMMY2 0x024
136 #define MTK_WED_WO_CCIF_DUMMY3 0x028
137 #define MTK_WED_WO_CCIF_DUMMY4 0x02c
138 #define MTK_WED_WO_CCIF_SHADOW1 0x030
139 #define MTK_WED_WO_CCIF_SHADOW2 0x034
140 #define MTK_WED_WO_CCIF_SHADOW3 0x038
141 #define MTK_WED_WO_CCIF_SHADOW4 0x03c
142 #define MTK_WED_WO_CCIF_DUMMY5 0x050
143 #define MTK_WED_WO_CCIF_DUMMY6 0x054
144 #define MTK_WED_WO_CCIF_DUMMY7 0x058
145 #define MTK_WED_WO_CCIF_DUMMY8 0x05c
146 #define MTK_WED_WO_CCIF_SHADOW5 0x060
147 #define MTK_WED_WO_CCIF_SHADOW6 0x064
148 #define MTK_WED_WO_CCIF_SHADOW7 0x068
149 #define MTK_WED_WO_CCIF_SHADOW8 0x06c
151 #define MTK_WED_WO_CTL_SD_LEN1 GENMASK(13, 0)
158 #define MTK_WED_WO_INFO_WINFO GENMASK(15, 0)
267 return 0; in mtk_wed_mcu_check_msg()