Lines Matching +full:16 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
7 #define MTK_WFDMA_DESC_CTRL_TO_HOST BIT(8)
10 #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15)
11 #define MTK_WDMA_DESC_CTRL_BURST BIT(16)
12 #define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16)
13 #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30)
14 #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)
16 #define MTK_WDMA_TXD0_DESC_INFO_DMA_DONE BIT(29)
17 #define MTK_WDMA_TXD1_DESC_INFO_DMA_DONE BIT(31)
29 #define MTK_WED_RESET_TX_BM BIT(0)
30 #define MTK_WED_RESET_RX_BM BIT(1)
31 #define MTK_WED_RESET_RX_PG_BM BIT(2)
32 #define MTK_WED_RESET_RRO_RX_TO_PG BIT(3)
33 #define MTK_WED_RESET_TX_FREE_AGENT BIT(4)
34 #define MTK_WED_RESET_WPDMA_TX_DRV BIT(8)
35 #define MTK_WED_RESET_WPDMA_RX_DRV BIT(9)
36 #define MTK_WED_RESET_WPDMA_RX_D_DRV BIT(10)
37 #define MTK_WED_RESET_WPDMA_INT_AGENT BIT(11)
38 #define MTK_WED_RESET_WED_TX_DMA BIT(12)
39 #define MTK_WED_RESET_WED_RX_DMA BIT(13)
40 #define MTK_WED_RESET_WDMA_TX_DRV BIT(16)
41 #define MTK_WED_RESET_WDMA_RX_DRV BIT(17)
42 #define MTK_WED_RESET_WDMA_INT_AGENT BIT(19)
43 #define MTK_WED_RESET_RX_RRO_QM BIT(20)
44 #define MTK_WED_RESET_RX_ROUTE_QM BIT(21)
45 #define MTK_WED_RESET_TX_AMSDU BIT(22)
46 #define MTK_WED_RESET_WED BIT(31)
49 #define MTK_WED_CTRL_WPDMA_INT_AGENT_EN BIT(0)
50 #define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY BIT(1)
51 #define MTK_WED_CTRL_WDMA_INT_AGENT_EN BIT(2)
52 #define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY BIT(3)
53 #define MTK_WED_CTRL_WED_RX_IND_CMD_EN BIT(5)
54 #define MTK_WED_CTRL_WED_RX_PG_BM_EN BIT(6)
55 #define MTK_WED_CTRL_WED_RX_PG_BM_BUSY BIT(7)
56 #define MTK_WED_CTRL_WED_TX_BM_EN BIT(8)
57 #define MTK_WED_CTRL_WED_TX_BM_BUSY BIT(9)
58 #define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN BIT(10)
59 #define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY BIT(11)
60 #define MTK_WED_CTRL_WED_RX_BM_EN BIT(12)
61 #define MTK_WED_CTRL_WED_RX_BM_BUSY BIT(13)
62 #define MTK_WED_CTRL_RX_RRO_QM_EN BIT(14)
63 #define MTK_WED_CTRL_RX_RRO_QM_BUSY BIT(15)
64 #define MTK_WED_CTRL_RX_ROUTE_QM_EN BIT(16)
65 #define MTK_WED_CTRL_RX_ROUTE_QM_BUSY BIT(17)
66 #define MTK_WED_CTRL_TX_TKID_ALI_EN BIT(20)
67 #define MTK_WED_CTRL_TX_TKID_ALI_BUSY BIT(21)
68 #define MTK_WED_CTRL_TX_AMSDU_EN BIT(22)
69 #define MTK_WED_CTRL_TX_AMSDU_BUSY BIT(23)
70 #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24)
71 #define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25)
72 #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28)
73 #define MTK_WED_CTRL_FLD_MIB_RD_CLR BIT(28)
76 #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0)
77 #define MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD BIT(1)
78 #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4)
79 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8)
80 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9)
81 #define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(10) /* wed v2 */
82 #define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(11) /* wed v2 */
83 #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16)
84 #define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR BIT(17)
85 #define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT BIT(18)
86 #define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN BIT(19)
87 #define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT BIT(20)
88 #define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR BIT(21)
89 #define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR BIT(22)
90 #define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR BIT(23)
91 #define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24)
92 #define MTK_WED_EXT_INT_STATUS_RX_DRV_GET_BM_DMAD_SKIP BIT(25)
93 #define MTK_WED_EXT_INT_STATUS_WPDMA_RX_D_DRV_ERR BIT(26)
94 #define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY BIT(27)
116 #define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM GENMASK(22, 16)
117 #define MTK_WED_TX_BM_CTRL_LEGACY_EN BIT(26)
118 #define MTK_WED_TX_TKID_CTRL_FREE_FORMAT BIT(27)
119 #define MTK_WED_TX_BM_CTRL_PAUSE BIT(28)
123 #define MTK_WED_TX_BM_SW_TAIL_IDX GENMASK(16, 0)
124 #define MTK_WED_TX_BM_INIT_SW_TAIL_IDX BIT(16)
127 #define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)
133 #define MTK_WED_TX_BM_INTF_TKFIFO_FDEP GENMASK(23, 16)
134 #define MTK_WED_TX_BM_INTF_TKID_VALID BIT(28)
135 #define MTK_WED_TX_BM_INTF_TKID_READ BIT(29)
140 #define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16)
141 #define MTK_WED_TX_BM_DYN_THR_HI_V2 GENMASK(24, 16)
145 #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16)
146 #define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28)
149 #define MTK_WED_TX_TKID_INTF_TKFIFO_FDEP GENMASK(25, 16)
152 #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM_V3 GENMASK(23, 16)
156 #define MTK_WED_TX_TKID_DYN_THR_HI GENMASK(22, 16)
160 #define MTK_WED_WPDMA_WRITE_TXP GENMASK(31, 16)
162 #define MTK_WED_TXDP_DW9_OVERWR BIT(9)
169 #define MTK_WED_GLO_CFG_TX_DMA_EN BIT(0)
170 #define MTK_WED_GLO_CFG_TX_DMA_BUSY BIT(1)
171 #define MTK_WED_GLO_CFG_RX_DMA_EN BIT(2)
172 #define MTK_WED_GLO_CFG_RX_DMA_BUSY BIT(3)
174 #define MTK_WED_GLO_CFG_TX_WB_DDONE BIT(6)
175 #define MTK_WED_GLO_CFG_BIG_ENDIAN BIT(7)
176 #define MTK_WED_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8)
177 #define MTK_WED_GLO_CFG_TX_BT_SIZE_LO BIT(9)
179 #define MTK_WED_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
182 #define MTK_WED_GLO_CFG_SW_RESET BIT(24)
183 #define MTK_WED_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)
184 #define MTK_WED_GLO_CFG_OMIT_RX_INFO BIT(27)
185 #define MTK_WED_GLO_CFG_OMIT_TX_INFO BIT(28)
186 #define MTK_WED_GLO_CFG_BYTE_SWAP BIT(29)
187 #define MTK_WED_GLO_CFG_RX_2B_OFFSET BIT(31)
203 #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE BIT(1)
207 #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN BIT(0)
208 #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY BIT(1)
209 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN BIT(2)
210 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY BIT(3)
212 #define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE BIT(6)
213 #define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
214 #define MTK_WED_WPDMA_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8)
215 #define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_LO BIT(9)
217 #define MTK_WED_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
220 #define MTK_WED_WPDMA_GLO_CFG_SW_RESET BIT(24)
221 #define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)
222 #define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27)
223 #define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28)
224 #define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP BIT(29)
225 #define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
228 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC BIT(4)
229 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC BIT(5)
230 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC BIT(6)
231 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC BIT(7)
233 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4 BIT(18)
234 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT BIT(19)
235 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_CHK BIT(20)
236 #define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR BIT(21)
237 #define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP BIT(24)
238 #define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST BIT(25)
239 #define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV BIT(28)
240 #define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK BIT(30)
244 #define MTK_WED_WPDMA_RESET_IDX_RX GENMASK(17, 16)
247 #define MTK_WED_WPDMA_CTRL_SDL1_FIXED BIT(31)
250 #define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV BIT(21)
251 #define MTK_WED_WPDMA_INT_CTRL_SIG_SRC BIT(22)
252 #define MTK_WED_WPDMA_INT_CTRL_SRC_SEL GENMASK(17, 16)
257 #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN BIT(0)
258 #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR BIT(1)
260 #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN BIT(8)
261 #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR BIT(9)
265 #define MTK_WED_WPDMA_INT_CTRL_RX0_EN BIT(0)
266 #define MTK_WED_WPDMA_INT_CTRL_RX0_CLR BIT(1)
268 #define MTK_WED_WPDMA_INT_CTRL_RX1_EN BIT(8)
269 #define MTK_WED_WPDMA_INT_CTRL_RX1_CLR BIT(9)
273 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN BIT(0)
274 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR BIT(1)
283 #define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16)
287 #define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16)
288 #define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20)
289 #define MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER BIT(21)
306 #define MTK_WED_WPDMA_RX_D_RX_DRV_EN BIT(0)
307 #define MTK_WED_WPDMA_RX_D_RX_DRV_BUSY BIT(1)
308 #define MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE BIT(3)
309 #define MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE BIT(4)
314 #define MTK_WED_WPDMA_RX_D_RST_CRX_IDX GENMASK(17, 16)
315 #define MTK_WED_WPDMA_RX_D_RST_DRV_IDX_ALL BIT(20)
325 #define MTK_WED_WPDMA_RX_D_PREF_EN BIT(0)
326 #define MTK_WED_WPDMA_RX_D_PREF_BUSY BIT(1)
328 #define MTK_WED_WPDMA_RX_D_PREF_LOW_THRES GENMASK(21, 16)
331 #define MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR BIT(15)
336 #define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR BIT(0)
337 #define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R1_CLR BIT(16)
347 #define MTK_WED_WDMA_RX_PREF_EN BIT(0)
348 #define MTK_WED_WDMA_RX_PREF_BUSY BIT(1)
350 #define MTK_WED_WDMA_RX_PREF_LOW_THRES GENMASK(21, 16)
351 #define MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR BIT(24)
352 #define MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR BIT(25)
353 #define MTK_WED_WDMA_RX_PREF_DDONE2_EN BIT(26)
354 #define MTK_WED_WDMA_RX_PREF_DDONE2_BUSY BIT(27)
357 #define MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR BIT(0)
358 #define MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR BIT(16)
361 #define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0)
362 #define MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK BIT(1)
363 #define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN BIT(2)
364 #define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY BIT(3)
366 #define MTK_WED_WDMA_GLO_CFG_TX_WB_DDONE BIT(6)
367 #define MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE BIT(13)
368 #define MTK_WED_WDMA_GLO_CFG_WCOMPLETE_SEL BIT(16)
369 #define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_RXDMA_BYPASS BIT(17)
370 #define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_BYPASS BIT(18)
371 #define MTK_WED_WDMA_GLO_CFG_FSM_RETURN_IDLE BIT(19)
372 #define MTK_WED_WDMA_GLO_CFG_WAIT_COHERENT BIT(20)
373 #define MTK_WED_WDMA_GLO_CFG_AXI_W_AFTER_AW BIT(21)
374 #define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY_SINGLE_W BIT(22)
375 #define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY BIT(23)
376 #define MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP BIT(24)
377 #define MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE BIT(25)
378 #define MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE BIT(26)
379 #define MTK_WED_WDMA_GLO_CFG_RXDRV_CLKGATE_BYPASS BIT(30)
382 #define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16)
383 #define MTK_WED_WDMA_RESET_IDX_RX_ALL BIT(20)
387 #define MTK_WED_WDMA_INT_CLR_RX_DONE GENMASK(17, 16)
390 #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16)
394 #define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL GENMASK(17, 16)
401 #define MTK_WED_WDMA_OFST0_GLO_CFG GENMASK(31, 16)
403 #define MTK_WED_WDMA_OFST1_RX_CTRL GENMASK(31, 16)
415 #define MTK_WED_RX_BM_INIT_SW_TAIL BIT(16)
420 #define MTK_WED_RX_BM_DYN_ALLOC_TH_H GENMASK(31, 16)
432 #define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0)
433 #define MTK_WDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
434 #define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2)
435 #define MTK_WDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
436 #define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26)
437 #define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27)
438 #define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28)
442 #define MTK_WDMA_RESET_IDX_RX GENMASK(17, 16)
448 #define MTK_WDMA_INT_MASK_RX_DONE GENMASK(17, 16)
449 #define MTK_WDMA_INT_MASK_TX_DELAY BIT(28)
450 #define MTK_WDMA_INT_MASK_TX_COHERENT BIT(29)
451 #define MTK_WDMA_INT_MASK_RX_DELAY BIT(30)
452 #define MTK_WDMA_INT_MASK_RX_COHERENT BIT(31)
455 #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR BIT(0)
456 #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR BIT(4)
457 #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR BIT(8)
458 #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR BIT(12)
461 #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR BIT(0)
462 #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR BIT(4)
463 #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR BIT(8)
464 #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR BIT(12)
465 #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR BIT(15)
466 #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR BIT(18)
467 #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR BIT(21)
473 #define MTK_WDMA_PREF_TX_CFG_PREF_EN BIT(0)
474 #define MTK_WDMA_PREF_TX_CFG_PREF_BUSY BIT(1)
477 #define MTK_WDMA_PREF_RX_CFG_PREF_EN BIT(0)
478 #define MTK_WDMA_PREF_RX_CFG_PREF_BUSY BIT(1)
481 #define MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR BIT(0)
482 #define MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR BIT(16)
485 #define MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR BIT(0)
486 #define MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR BIT(16)
493 #define MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY BIT(0)
494 #define MTK_WDMA_WRBK_TX_CFG_WRBK_EN BIT(30)
497 #define MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR BIT(0)
500 #define MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY BIT(0)
501 #define MTK_WDMA_WRBK_RX_CFG_WRBK_EN BIT(30)
504 #define MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR BIT(0)
511 #define MTK_PCIE_MIRROR_MAP_EN BIT(0)
512 #define MTK_PCIE_MIRROR_MAP_WED_ID BIT(1)
518 #define MTK_WED_RTQM_BUSY BIT(1)
519 #define MTK_WED_RTQM_Q_RST BIT(2)
520 #define MTK_WED_RTQM_Q_DBG_BYPASS BIT(5)
577 #define MTK_WED_RROQM_RST_IDX_MIOD BIT(0)
578 #define MTK_WED_RROQM_RST_IDX_FDBK BIT(4)
599 #define MTK_WED_RROQM_MIOD_ENTRY_DW GENMASK(22, 16)
615 #define MTK_WED_RX_BM_PTR_HEAD GENMASK(32, 16)
630 #define MTK_WED_IND_CMD_PREFETCH_FREE_CNT GENMASK(19, 16)
636 #define MTK_WED_IND_CMD_BASE_M GENMASK(19, 16)
641 #define MTK_WED_RRO_CFG1_ACK_SN_BASE_M GENMASK(19, 16)
646 #define MTK_WED_ADDR_ELEM_PREFETCH_FREE_CNT GENMASK(19, 16)
650 #define MTK_WED_ADDR_ELEM_TBL_RD_RDY BIT(28)
651 #define MTK_WED_ADDR_ELEM_TBL_WR_RDY BIT(29)
652 #define MTK_WED_ADDR_ELEM_TBL_RD BIT(30)
653 #define MTK_WED_ADDR_ELEM_TBL_WR BIT(31)
660 #define MTK_WED_PN_CHECK_RD_RDY BIT(28)
661 #define MTK_WED_PN_CHECK_WR_RDY BIT(29)
662 #define MTK_WED_PN_CHECK_RD BIT(30)
663 #define MTK_WED_PN_CHECK_WR BIT(31)
666 #define MTK_WED_PN_CHECK_IS_FIRST BIT(17)
671 #define MTK_WED_RRO_MSDU_PG_DRV_CLR BIT(26)
672 #define MTK_WED_RRO_MSDU_PG_DRV_EN BIT(31)
680 #define MTK_WED_RRO_RX_MAGIC_CNT BIT(13)
683 #define MTK_WED_RRO_RX_D_DRV_CLR BIT(26)
684 #define MTK_WED_RRO_RX_D_DRV_EN BIT(31)
692 #define MTK_WED_RRO_PG_BM_INIT_SW_TAIL_IDX BIT(16)
695 #define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_EN BIT(0)
696 #define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_CLR BIT(1)
698 #define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_EN BIT(8)
699 #define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_CLR BIT(9)
703 #define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_EN BIT(0)
704 #define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_CLR BIT(1)
706 #define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_EN BIT(8)
707 #define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_CLR BIT(9)
709 #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_EN BIT(16)
710 #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR BIT(17)
717 #define MTK_WED_RX_IND_CMD_DBG_CNT_EN BIT(31)
724 #define MTK_WED_ADDR_ELEM_FIRST_SIG_FAIL_CNT GENMASK(31, 16)
736 #define MTK_WED_AMSDU_IS_PRIOR0_RING BIT(10)
739 #define MTK_WED_AMSDU_STA_INFO_DO_INIT BIT(0)
740 #define MTK_WED_AMSDU_STA_INFO_SET_INIT BIT(1)
743 #define MTK_WED_AMSDU_STA_WTBL_HDRT_MODE BIT(0)
744 #define MTK_WED_AMSDU_STA_RMVL BIT(1)
751 #define MTK_WED_AMSDU_PSE_RESET BIT(16)
754 #define MTK_WED_AMSDU_HIFTXD_SRC GENMASK(16, 15)
766 #define MTK_WED_AMSDU_ENG_MAX_PL_CNT GENMASK(27, 16)
770 #define MTK_WED_AMSDU_ENG_MAX_BUF_MERGED GENMASK(20, 16)
776 #define MTK_WED_AMSDU_QMEM_FQ_CNT GENMASK(27, 16)
778 #define MTK_WED_AMSDU_QMEM_TID0_QCNT GENMASK(27, 16)
780 #define MTK_WED_AMSDU_QMEM_TID2_QCNT GENMASK(27, 16)
782 #define MTK_WED_AMSDU_QMEM_TID4_QCNT GENMASK(27, 16)
784 #define MTK_WED_AMSDU_QMEM_TID6_QCNT GENMASK(27, 16)
788 #define MTK_WED_AMSDU_QMEM_FQ_HEAD GENMASK(27, 16)
790 #define MTK_WED_AMSDU_QMEM_TID0_QHEAD GENMASK(27, 16)
792 #define MTK_WED_AMSDU_QMEM_TID2_QHEAD GENMASK(27, 16)
794 #define MTK_WED_AMSDU_QMEM_TID4_QHEAD GENMASK(27, 16)
796 #define MTK_WED_AMSDU_QMEM_TID6_QHEAD GENMASK(27, 16)
798 #define MTK_WED_AMSDU_QMEM_FQ_TAIL GENMASK(27, 16)
800 #define MTK_WED_AMSDU_QMEM_TID0_QTAIL GENMASK(27, 16)
802 #define MTK_WED_AMSDU_QMEM_TID2_QTAIL GENMASK(27, 16)
804 #define MTK_WED_AMSDU_QMEM_TID4_QTAIL GENMASK(27, 16)
806 #define MTK_WED_AMSDU_QMEM_TID6_QTAIL GENMASK(27, 16)