Lines Matching +full:0 +full:xeb8
8 #define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0)
9 #define MTK_WDMA_DESC_CTRL_LEN1_V2 GENMASK(13, 0)
26 #define MTK_WED_REV_ID 0x004
28 #define MTK_WED_RESET 0x008
29 #define MTK_WED_RESET_TX_BM BIT(0)
48 #define MTK_WED_CTRL 0x00c
49 #define MTK_WED_CTRL_WPDMA_INT_AGENT_EN BIT(0)
75 #define MTK_WED_EXT_INT_STATUS 0x020
76 #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0)
103 #define MTK_WED_EXT_INT_MASK 0x028
104 #define MTK_WED_EXT_INT_MASK1 0x02c
105 #define MTK_WED_EXT_INT_MASK2 0x030
106 #define MTK_WED_EXT_INT_MASK3 0x034
108 #define MTK_WED_STATUS 0x060
111 #define MTK_WED_WPDMA_STATUS 0x068
114 #define MTK_WED_TX_BM_CTRL 0x080
115 #define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM GENMASK(6, 0)
121 #define MTK_WED_TX_BM_BASE 0x084
122 #define MTK_WED_TX_BM_INIT_PTR 0x088
123 #define MTK_WED_TX_BM_SW_TAIL_IDX GENMASK(16, 0)
126 #define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)
129 #define MTK_WED_TX_BM_BUF_LEN 0x08c
131 #define MTK_WED_TX_BM_INTF 0x09c
132 #define MTK_WED_TX_BM_INTF_TKID GENMASK(15, 0)
137 #define MTK_WED_TX_BM_DYN_THR 0x0a0
138 #define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0)
139 #define MTK_WED_TX_BM_DYN_THR_LO_V2 GENMASK(8, 0)
143 #define MTK_WED_TX_TKID_CTRL 0x0c0
144 #define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(6, 0)
148 #define MTK_WED_TX_TKID_INTF 0x0dc
151 #define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM_V3 GENMASK(7, 0)
154 #define MTK_WED_TX_TKID_DYN_THR 0x0e0
155 #define MTK_WED_TX_TKID_DYN_THR_LO GENMASK(6, 0)
158 #define MTK_WED_TXP_DW0 0x120
159 #define MTK_WED_TXP_DW1 0x124
161 #define MTK_WED_TXDP_CTRL 0x130
163 #define MTK_WED_RX_BM_TKID_MIB 0x1cc
165 #define MTK_WED_INT_STATUS 0x200
166 #define MTK_WED_INT_MASK 0x204
168 #define MTK_WED_GLO_CFG 0x208
169 #define MTK_WED_GLO_CFG_TX_DMA_EN BIT(0)
189 #define MTK_WED_RESET_IDX 0x20c
192 #define MTK_WED_TX_MIB(_n) (0x2a0 + (_n) * 4)
193 #define MTK_WED_RX_MIB(_n) (0x2e0 + (_n) * 4)
195 #define MTK_WED_RING_TX(_n) (0x300 + (_n) * 0x10)
197 #define MTK_WED_RING_RX(_n) (0x400 + (_n) * 0x10)
198 #define MTK_WED_RING_RX_DATA(_n) (0x420 + (_n) * 0x10)
200 #define MTK_WED_SCR0 0x3c0
201 #define MTK_WED_RX1_CTRL2 0x418
202 #define MTK_WED_WPDMA_INT_TRIGGER 0x504
206 #define MTK_WED_WPDMA_GLO_CFG 0x508
207 #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN BIT(0)
242 #define MTK_WED_WPDMA_RESET_IDX 0x50c
243 #define MTK_WED_WPDMA_RESET_IDX_TX GENMASK(3, 0)
246 #define MTK_WED_WPDMA_CTRL 0x518
249 #define MTK_WED_WPDMA_INT_CTRL 0x520
254 #define MTK_WED_WPDMA_INT_MASK 0x524
256 #define MTK_WED_WPDMA_INT_CTRL_TX 0x530
257 #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN BIT(0)
264 #define MTK_WED_WPDMA_INT_CTRL_RX 0x534
265 #define MTK_WED_WPDMA_INT_CTRL_RX0_EN BIT(0)
272 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE 0x538
273 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN BIT(0)
277 #define MTK_WED_PCIE_CFG_BASE 0x560
279 #define MTK_WED_PCIE_CFG_BASE 0x560
280 #define MTK_WED_PCIE_CFG_INTM 0x564
281 #define MTK_WED_PCIE_CFG_MSIS 0x568
282 #define MTK_WED_PCIE_INT_TRIGGER 0x570
285 #define MTK_WED_PCIE_INT_CTRL 0x57c
291 #define MTK_WED_WPDMA_CFG_BASE 0x580
292 #define MTK_WED_WPDMA_CFG_INT_MASK 0x584
293 #define MTK_WED_WPDMA_CFG_TX 0x588
294 #define MTK_WED_WPDMA_CFG_TX_FREE 0x58c
296 #define MTK_WED_WPDMA_TX_MIB(_n) (0x5a0 + (_n) * 4)
297 #define MTK_WED_WPDMA_TX_COHERENT_MIB(_n) (0x5d0 + (_n) * 4)
298 #define MTK_WED_WPDMA_RX_MIB(_n) (0x5e0 + (_n) * 4)
299 #define MTK_WED_WPDMA_RX_COHERENT_MIB(_n) (0x5f0 + (_n) * 4)
301 #define MTK_WED_WPDMA_RING_TX(_n) (0x600 + (_n) * 0x10)
302 #define MTK_WED_WPDMA_RING_RX(_n) (0x700 + (_n) * 0x10)
303 #define MTK_WED_WPDMA_RING_RX_DATA(_n) (0x730 + (_n) * 0x10)
305 #define MTK_WED_WPDMA_RX_D_GLO_CFG 0x75c
306 #define MTK_WED_WPDMA_RX_D_RX_DRV_EN BIT(0)
313 #define MTK_WED_WPDMA_RX_D_RST_IDX 0x760
318 #define MTK_WED_WPDMA_RX_GLO_CFG 0x76c
320 #define MTK_WED_WPDMA_RX_D_MIB(_n) (0x774 + (_n) * 4)
321 #define MTK_WED_WPDMA_RX_D_PROCESSED_MIB(_n) (0x784 + (_n) * 4)
322 #define MTK_WED_WPDMA_RX_D_COHERENT_MIB 0x78c
324 #define MTK_WED_WPDMA_RX_D_PREF_CFG 0x7b4
325 #define MTK_WED_WPDMA_RX_D_PREF_EN BIT(0)
330 #define MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX 0x7b8
333 #define MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX 0x7bc
335 #define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG 0x7c0
336 #define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR BIT(0)
339 #define MTK_WED_WDMA_RING_TX 0x800
341 #define MTK_WED_WDMA_TX_MIB 0x810
343 #define MTK_WED_WDMA_RING_RX(_n) (0x900 + (_n) * 0x10)
344 #define MTK_WED_WDMA_RX_THRES(_n) (0x940 + (_n) * 0x4)
346 #define MTK_WED_WDMA_RX_PREF_CFG 0x950
347 #define MTK_WED_WDMA_RX_PREF_EN BIT(0)
356 #define MTK_WED_WDMA_RX_PREF_FIFO_CFG 0x95C
357 #define MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR BIT(0)
360 #define MTK_WED_WDMA_GLO_CFG 0xa04
361 #define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0)
381 #define MTK_WED_WDMA_RESET_IDX 0xa08
386 #define MTK_WED_WDMA_INT_CLR 0xa24
389 #define MTK_WED_WDMA_INT_TRIGGER 0xa28
392 #define MTK_WED_WDMA_INT_CTRL 0xa2c
393 #define MTK_WED_WDMA_INT_POLL_PRD GENMASK(7, 0)
396 #define MTK_WED_WDMA_CFG_BASE 0xaa0
397 #define MTK_WED_WDMA_OFFSET0 0xaa4
398 #define MTK_WED_WDMA_OFFSET1 0xaa8
400 #define MTK_WED_WDMA_OFST0_GLO_INTS GENMASK(15, 0)
402 #define MTK_WED_WDMA_OFST1_TX_CTRL GENMASK(15, 0)
405 #define MTK_WED_WDMA_RX_MIB(_n) (0xae0 + (_n) * 4)
406 #define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4)
407 #define MTK_WED_WDMA_RX_PROCESSED_MIB(_n) (0xaf0 + (_n) * 4)
409 #define MTK_WED_RX_BM_RX_DMAD 0xd80
410 #define MTK_WED_RX_BM_RX_DMAD_SDL0 GENMASK(13, 0)
412 #define MTK_WED_RX_BM_BASE 0xd84
413 #define MTK_WED_RX_BM_INIT_PTR 0xd88
414 #define MTK_WED_RX_BM_SW_TAIL GENMASK(15, 0)
417 #define MTK_WED_RX_PTR 0xd8c
419 #define MTK_WED_RX_BM_DYN_ALLOC_TH 0xdb4
421 #define MTK_WED_RX_BM_DYN_ALLOC_TH_L GENMASK(15, 0)
423 #define MTK_WED_RING_OFS_BASE 0x00
424 #define MTK_WED_RING_OFS_COUNT 0x04
425 #define MTK_WED_RING_OFS_CPU_IDX 0x08
426 #define MTK_WED_RING_OFS_DMA_IDX 0x0c
428 #define MTK_WDMA_RING_TX(_n) (0x000 + (_n) * 0x10)
429 #define MTK_WDMA_RING_RX(_n) (0x100 + (_n) * 0x10)
431 #define MTK_WDMA_GLO_CFG 0x204
432 #define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0)
440 #define MTK_WDMA_RESET_IDX 0x208
441 #define MTK_WDMA_RESET_IDX_TX GENMASK(3, 0)
444 #define MTK_WDMA_INT_STATUS 0x220
446 #define MTK_WDMA_INT_MASK 0x228
447 #define MTK_WDMA_INT_MASK_TX_DONE GENMASK(3, 0)
454 #define MTK_WDMA_XDMA_TX_FIFO_CFG 0x238
455 #define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR BIT(0)
460 #define MTK_WDMA_XDMA_RX_FIFO_CFG 0x23c
461 #define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR BIT(0)
469 #define MTK_WDMA_INT_GRP1 0x250
470 #define MTK_WDMA_INT_GRP2 0x254
472 #define MTK_WDMA_PREF_TX_CFG 0x2d0
473 #define MTK_WDMA_PREF_TX_CFG_PREF_EN BIT(0)
476 #define MTK_WDMA_PREF_RX_CFG 0x2dc
477 #define MTK_WDMA_PREF_RX_CFG_PREF_EN BIT(0)
480 #define MTK_WDMA_PREF_RX_FIFO_CFG 0x2e0
481 #define MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR BIT(0)
484 #define MTK_WDMA_PREF_TX_FIFO_CFG 0x2d4
485 #define MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR BIT(0)
488 #define MTK_WDMA_PREF_SIDX_CFG 0x2e4
489 #define MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR GENMASK(3, 0)
492 #define MTK_WDMA_WRBK_TX_CFG 0x300
493 #define MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY BIT(0)
496 #define MTK_WDMA_WRBK_TX_FIFO_CFG(_n) (0x304 + (_n) * 0x4)
497 #define MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR BIT(0)
499 #define MTK_WDMA_WRBK_RX_CFG 0x344
500 #define MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY BIT(0)
503 #define MTK_WDMA_WRBK_RX_FIFO_CFG(_n) (0x348 + (_n) * 0x4)
504 #define MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR BIT(0)
506 #define MTK_WDMA_WRBK_SIDX_CFG 0x388
507 #define MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR GENMASK(3, 0)
510 #define MTK_PCIE_MIRROR_MAP(n) ((n) ? 0x4 : 0x0)
511 #define MTK_PCIE_MIRROR_MAP_EN BIT(0)
515 #define HIFSYS_DMA_AG_MAP 0x008
517 #define MTK_WED_RTQM_GLO_CFG 0xb00
523 #define MTK_WED_RTQM_RST 0xb04
525 #define MTK_WED_RTQM_IGRS0_I2HW_DMAD_CNT 0xb1c
526 #define MTK_WED_RTQM_IGRS0_I2H_DMAD_CNT(_n) (0xb20 + (_n) * 0x4)
527 #define MTK_WED_RTQM_IGRS0_I2HW_PKT_CNT 0xb28
528 #define MTK_WED_RTQM_IGRS0_I2H_PKT_CNT(_n) (0xb2c + (_n) * 0x4)
529 #define MTK_WED_RTQM_IGRS0_FDROP_CNT 0xb34
531 #define MTK_WED_RTQM_IGRS1_I2HW_DMAD_CNT 0xb44
532 #define MTK_WED_RTQM_IGRS1_I2H_DMAD_CNT(_n) (0xb48 + (_n) * 0x4)
533 #define MTK_WED_RTQM_IGRS1_I2HW_PKT_CNT 0xb50
534 #define MTK_WED_RTQM_IGRS1_I2H_PKT_CNT(_n) (0xb54 + (_n) * 0x4)
535 #define MTK_WED_RTQM_IGRS1_FDROP_CNT 0xb5c
537 #define MTK_WED_RTQM_IGRS2_I2HW_DMAD_CNT 0xb6c
538 #define MTK_WED_RTQM_IGRS2_I2H_DMAD_CNT(_n) (0xb70 + (_n) * 0x4)
539 #define MTK_WED_RTQM_IGRS2_I2HW_PKT_CNT 0xb78
540 #define MTK_WED_RTQM_IGRS2_I2H_PKT_CNT(_n) (0xb7c + (_n) * 0x4)
541 #define MTK_WED_RTQM_IGRS2_FDROP_CNT 0xb84
543 #define MTK_WED_RTQM_IGRS3_I2HW_DMAD_CNT 0xb94
544 #define MTK_WED_RTQM_IGRS3_I2H_DMAD_CNT(_n) (0xb98 + (_n) * 0x4)
545 #define MTK_WED_RTQM_IGRS3_I2HW_PKT_CNT 0xba0
546 #define MTK_WED_RTQM_IGRS3_I2H_PKT_CNT(_n) (0xba4 + (_n) * 0x4)
547 #define MTK_WED_RTQM_IGRS3_FDROP_CNT 0xbac
549 #define MTK_WED_RTQM_R2H_MIB(_n) (0xb70 + (_n) * 0x4)
550 #define MTK_WED_RTQM_R2Q_MIB(_n) (0xb78 + (_n) * 0x4)
551 #define MTK_WED_RTQM_Q2N_MIB 0xb80
552 #define MTK_WED_RTQM_Q2H_MIB(_n) (0xb84 + (_n) * 0x4)
554 #define MTK_WED_RTQM_Q2B_MIB 0xb8c
555 #define MTK_WED_RTQM_PFDBK_MIB 0xb90
557 #define MTK_WED_RTQM_ENQ_CFG0 0xbb8
560 #define MTK_WED_RTQM_FDROP_MIB 0xb84
561 #define MTK_WED_RTQM_ENQ_I2Q_DMAD_CNT 0xbbc
562 #define MTK_WED_RTQM_ENQ_I2N_DMAD_CNT 0xbc0
563 #define MTK_WED_RTQM_ENQ_I2Q_PKT_CNT 0xbc4
564 #define MTK_WED_RTQM_ENQ_I2N_PKT_CNT 0xbc8
565 #define MTK_WED_RTQM_ENQ_USED_ENTRY_CNT 0xbcc
566 #define MTK_WED_RTQM_ENQ_ERR_CNT 0xbd0
568 #define MTK_WED_RTQM_DEQ_DMAD_CNT 0xbd8
569 #define MTK_WED_RTQM_DEQ_Q2I_DMAD_CNT 0xbdc
570 #define MTK_WED_RTQM_DEQ_PKT_CNT 0xbe0
571 #define MTK_WED_RTQM_DEQ_Q2I_PKT_CNT 0xbe4
572 #define MTK_WED_RTQM_DEQ_USED_PFDBK_CNT 0xbe8
573 #define MTK_WED_RTQM_DEQ_ERR_CNT 0xbec
575 #define MTK_WED_RROQM_GLO_CFG 0xc04
576 #define MTK_WED_RROQM_RST_IDX 0xc08
577 #define MTK_WED_RROQM_RST_IDX_MIOD BIT(0)
580 #define MTK_WED_RROQM_MIOD_CTRL0 0xc40
581 #define MTK_WED_RROQM_MIOD_CTRL1 0xc44
582 #define MTK_WED_RROQM_MIOD_CNT GENMASK(11, 0)
584 #define MTK_WED_RROQM_MIOD_CTRL2 0xc48
585 #define MTK_WED_RROQM_MIOD_CTRL3 0xc4c
587 #define MTK_WED_RROQM_FDBK_CTRL0 0xc50
588 #define MTK_WED_RROQM_FDBK_CTRL1 0xc54
589 #define MTK_WED_RROQM_FDBK_CNT GENMASK(11, 0)
591 #define MTK_WED_RROQM_FDBK_CTRL2 0xc58
593 #define MTK_WED_RROQ_BASE_L 0xc80
594 #define MTK_WED_RROQ_BASE_H 0xc84
596 #define MTK_WED_RROQM_MIOD_CFG 0xc8c
597 #define MTK_WED_RROQM_MIOD_MID_DW GENMASK(5, 0)
601 #define MTK_WED_RROQM_MID_MIB 0xcc0
602 #define MTK_WED_RROQM_MOD_MIB 0xcc4
603 #define MTK_WED_RROQM_MOD_COHERENT_MIB 0xcc8
604 #define MTK_WED_RROQM_FDBK_MIB 0xcd0
605 #define MTK_WED_RROQM_FDBK_COHERENT_MIB 0xcd4
606 #define MTK_WED_RROQM_FDBK_IND_MIB 0xce0
607 #define MTK_WED_RROQM_FDBK_ENQ_MIB 0xce4
608 #define MTK_WED_RROQM_FDBK_ANC_MIB 0xce8
609 #define MTK_WED_RROQM_FDBK_ANC2H_MIB 0xcec
611 #define MTK_WED_RX_BM_RX_DMAD 0xd80
612 #define MTK_WED_RX_BM_BASE 0xd84
613 #define MTK_WED_RX_BM_INIT_PTR 0xd88
614 #define MTK_WED_RX_BM_PTR 0xd8c
616 #define MTK_WED_RX_BM_PTR_TAIL GENMASK(15, 0)
618 #define MTK_WED_RX_BM_BLEN 0xd90
619 #define MTK_WED_RX_BM_STS 0xd94
620 #define MTK_WED_RX_BM_INTF2 0xd98
621 #define MTK_WED_RX_BM_INTF 0xd9c
622 #define MTK_WED_RX_BM_ERR_STS 0xda8
624 #define MTK_RRO_IND_CMD_SIGNATURE 0xe00
625 #define MTK_RRO_IND_CMD_DMA_IDX GENMASK(11, 0)
628 #define MTK_WED_IND_CMD_RX_CTRL0 0xe04
629 #define MTK_WED_IND_CMD_PROC_IDX GENMASK(11, 0)
633 #define MTK_WED_IND_CMD_RX_CTRL1 0xe08
634 #define MTK_WED_IND_CMD_RX_CTRL2 0xe0c
635 #define MTK_WED_IND_CMD_MAX_CNT GENMASK(11, 0)
638 #define MTK_WED_RRO_CFG0 0xe10
639 #define MTK_WED_RRO_CFG1 0xe14
642 #define MTK_WED_RRO_CFG1_PARTICL_SE_ID GENMASK(11, 0)
644 #define MTK_WED_ADDR_ELEM_CFG0 0xe18
645 #define MTK_WED_ADDR_ELEM_CFG1 0xe1c
648 #define MTK_WED_ADDR_ELEM_TBL_CFG 0xe20
649 #define MTK_WED_ADDR_ELEM_TBL_OFFSET GENMASK(6, 0)
655 #define MTK_WED_RADDR_ELEM_TBL_WDATA 0xe24
656 #define MTK_WED_RADDR_ELEM_TBL_RDATA 0xe28
658 #define MTK_WED_PN_CHECK_CFG 0xe30
659 #define MTK_WED_PN_CHECK_SE_ID GENMASK(11, 0)
665 #define MTK_WED_PN_CHECK_WDATA_M 0xe38
668 #define MTK_WED_RRO_MSDU_PG_RING_CFG(_n) (0xe44 + (_n) * 0x8)
670 #define MTK_WED_RRO_MSDU_PG_RING2_CFG 0xe58
674 #define MTK_WED_RRO_MSDU_PG_CTRL0(_n) (0xe5c + (_n) * 0xc)
675 #define MTK_WED_RRO_MSDU_PG_CTRL1(_n) (0xe60 + (_n) * 0xc)
676 #define MTK_WED_RRO_MSDU_PG_CTRL2(_n) (0xe64 + (_n) * 0xc)
678 #define MTK_WED_RRO_RX_D_RX(_n) (0xe80 + (_n) * 0x10)
682 #define MTK_WED_RRO_RX_D_CFG(_n) (0xea0 + (_n) * 0x4)
686 #define MTK_WED_RRO_PG_BM_RX_DMAM 0xeb0
687 #define MTK_WED_RRO_PG_BM_RX_SDL0 GENMASK(13, 0)
689 #define MTK_WED_RRO_PG_BM_BASE 0xeb4
690 #define MTK_WED_RRO_PG_BM_INIT_PTR 0xeb8
691 #define MTK_WED_RRO_PG_BM_SW_TAIL_IDX GENMASK(15, 0)
694 #define MTK_WED_WPDMA_INT_CTRL_RRO_RX 0xeec
695 #define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_EN BIT(0)
702 #define MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG 0xef4
703 #define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_EN BIT(0)
713 #define MTK_WED_RRO_RX_HW_STS 0xf00
714 #define MTK_WED_RX_IND_CMD_BUSY GENMASK(31, 0)
716 #define MTK_WED_RX_IND_CMD_CNT0 0xf20
719 #define MTK_WED_RX_IND_CMD_CNT(_n) (0xf20 + (_n) * 0x4)
720 #define MTK_WED_IND_CMD_MAGIC_CNT_FAIL_CNT GENMASK(15, 0)
722 #define MTK_WED_RX_ADDR_ELEM_CNT(_n) (0xf48 + (_n) * 0x4)
723 #define MTK_WED_ADDR_ELEM_SIG_FAIL_CNT GENMASK(15, 0)
725 #define MTK_WED_ADDR_ELEM_ACKSN_CNT GENMASK(27, 0)
727 #define MTK_WED_RX_MSDU_PG_CNT(_n) (0xf5c + (_n) * 0x4)
729 #define MTK_WED_RX_PN_CHK_CNT 0xf70
730 #define MTK_WED_PN_CHK_FAIL_CNT GENMASK(15, 0)
732 #define MTK_WED_WOCPU_VIEW_MIOD_BASE 0x8000
733 #define MTK_WED_PCIE_INT_MASK 0x0
735 #define MTK_WED_AMSDU_FIFO 0x1800
738 #define MTK_WED_AMSDU_STA_INFO 0x01810
739 #define MTK_WED_AMSDU_STA_INFO_DO_INIT BIT(0)
742 #define MTK_WED_AMSDU_STA_INFO_INIT 0x01814
743 #define MTK_WED_AMSDU_STA_WTBL_HDRT_MODE BIT(0)
748 #define MTK_WED_AMSDU_HIFTXD_BASE_L(_n) (0x1980 + (_n) * 0x4)
750 #define MTK_WED_AMSDU_PSE 0x1910
753 #define MTK_WED_AMSDU_HIFTXD_CFG 0x1968
756 #define MTK_WED_MON_AMSDU_FIFO_DMAD 0x1a34
758 #define MTK_WED_MON_AMSDU_ENG_DMAD(_n) (0x1a80 + (_n) * 0x50)
759 #define MTK_WED_MON_AMSDU_ENG_QFPL(_n) (0x1a84 + (_n) * 0x50)
760 #define MTK_WED_MON_AMSDU_ENG_QENI(_n) (0x1a88 + (_n) * 0x50)
761 #define MTK_WED_MON_AMSDU_ENG_QENO(_n) (0x1a8c + (_n) * 0x50)
762 #define MTK_WED_MON_AMSDU_ENG_MERG(_n) (0x1a90 + (_n) * 0x50)
764 #define MTK_WED_MON_AMSDU_ENG_CNT8(_n) (0x1a94 + (_n) * 0x50)
765 #define MTK_WED_AMSDU_ENG_MAX_QGPP_CNT GENMASK(10, 0)
768 #define MTK_WED_MON_AMSDU_ENG_CNT9(_n) (0x1a98 + (_n) * 0x50)
769 #define MTK_WED_AMSDU_ENG_CUR_ENTRY GENMASK(10, 0)
773 #define MTK_WED_MON_AMSDU_QMEM_STS1 0x1e04
775 #define MTK_WED_MON_AMSDU_QMEM_CNT(_n) (0x1e0c + (_n) * 0x4)
777 #define MTK_WED_AMSDU_QMEM_SP_QCNT GENMASK(11, 0)
779 #define MTK_WED_AMSDU_QMEM_TID1_QCNT GENMASK(11, 0)
781 #define MTK_WED_AMSDU_QMEM_TID3_QCNT GENMASK(11, 0)
783 #define MTK_WED_AMSDU_QMEM_TID5_QCNT GENMASK(11, 0)
785 #define MTK_WED_AMSDU_QMEM_TID7_QCNT GENMASK(11, 0)
787 #define MTK_WED_MON_AMSDU_QMEM_PTR(_n) (0x1e20 + (_n) * 0x4)
789 #define MTK_WED_AMSDU_QMEM_SP_QHEAD GENMASK(11, 0)
791 #define MTK_WED_AMSDU_QMEM_TID1_QHEAD GENMASK(11, 0)
793 #define MTK_WED_AMSDU_QMEM_TID3_QHEAD GENMASK(11, 0)
795 #define MTK_WED_AMSDU_QMEM_TID5_QHEAD GENMASK(11, 0)
797 #define MTK_WED_AMSDU_QMEM_TID7_QHEAD GENMASK(11, 0)
799 #define MTK_WED_AMSDU_QMEM_SP_QTAIL GENMASK(11, 0)
801 #define MTK_WED_AMSDU_QMEM_TID1_QTAIL GENMASK(11, 0)
803 #define MTK_WED_AMSDU_QMEM_TID3_QTAIL GENMASK(11, 0)
805 #define MTK_WED_AMSDU_QMEM_TID5_QTAIL GENMASK(11, 0)
807 #define MTK_WED_AMSDU_QMEM_TID7_QTAIL GENMASK(11, 0)
809 #define MTK_WED_MON_AMSDU_HIFTXD_FETCH_MSDU(_n) (0x1ec4 + (_n) * 0x4)
811 #define MTK_WED_PCIE_BASE 0x11280000
812 #define MTK_WED_PCIE_BASE0 0x11300000
813 #define MTK_WED_PCIE_BASE1 0x11310000
814 #define MTK_WED_PCIE_BASE2 0x11290000