Lines Matching refs:wed_w32
383 wed_w32(dev, MTK_WED_RESET, mask); in mtk_wed_reset()
592 wed_w32(dev, MTK_WED_AMSDU_HIFTXD_BASE_L(i), in mtk_wed_amsdu_init()
596 wed_w32(dev, MTK_WED_AMSDU_STA_INFO_INIT, MTK_WED_AMSDU_STA_RMVL | in mtk_wed_amsdu_init()
603 wed_w32(dev, MTK_WED_AMSDU_STA_INFO, MTK_WED_AMSDU_STA_INFO_DO_INIT); in mtk_wed_amsdu_init()
906 wed_w32(dev, MTK_WED_RRO_PG_BM_BASE, dev->hw_rro.desc_phys); in mtk_wed_hwrro_init()
908 wed_w32(dev, MTK_WED_RRO_PG_BM_INIT_PTR, in mtk_wed_hwrro_init()
920 wed_w32(dev, MTK_WED_RX_BM_RX_DMAD, in mtk_wed_rx_buffer_hw_init()
922 wed_w32(dev, MTK_WED_RX_BM_BASE, dev->rx_buf_ring.desc_phys); in mtk_wed_rx_buffer_hw_init()
923 wed_w32(dev, MTK_WED_RX_BM_INIT_PTR, MTK_WED_RX_BM_INIT_SW_TAIL | in mtk_wed_rx_buffer_hw_init()
925 wed_w32(dev, MTK_WED_RX_BM_DYN_ALLOC_TH, in mtk_wed_rx_buffer_hw_init()
986 wed_w32(dev, MTK_WED_EXT_INT_MASK, en ? mask : 0); in mtk_wed_set_ext_int()
997 wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR); in mtk_wed_set_512_support()
998 wed_w32(dev, MTK_WED_TXP_DW1, in mtk_wed_set_512_support()
1001 wed_w32(dev, MTK_WED_TXP_DW1, in mtk_wed_set_512_support()
1080 wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0); in mtk_wed_stop()
1081 wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0); in mtk_wed_stop()
1088 wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0); in mtk_wed_stop()
1089 wed_w32(dev, MTK_WED_EXT_INT_MASK2, 0); in mtk_wed_stop()
1187 wed_w32(dev, MTK_WED_PCIE_CFG_INTM, in mtk_wed_bus_init()
1189 wed_w32(dev, MTK_WED_PCIE_CFG_BASE, in mtk_wed_bus_init()
1191 wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(8)); in mtk_wed_bus_init()
1193 wed_w32(dev, MTK_WED_PCIE_CFG_INTM, in mtk_wed_bus_init()
1195 wed_w32(dev, MTK_WED_PCIE_CFG_BASE, in mtk_wed_bus_init()
1197 wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24)); in mtk_wed_bus_init()
1200 wed_w32(dev, MTK_WED_PCIE_INT_CTRL, in mtk_wed_bus_init()
1227 wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys); in mtk_wed_set_wpdma()
1233 wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int); in mtk_wed_set_wpdma()
1234 wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask); in mtk_wed_set_wpdma()
1235 wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx); in mtk_wed_set_wpdma()
1236 wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree); in mtk_wed_set_wpdma()
1241 wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo); in mtk_wed_set_wpdma()
1242 wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring0, dev->wlan.wpdma_rx); in mtk_wed_set_wpdma()
1247 wed_w32(dev, MTK_WED_RRO_RX_D_CFG(0), dev->wlan.wpdma_rx_rro[0]); in mtk_wed_set_wpdma()
1248 wed_w32(dev, MTK_WED_RRO_RX_D_CFG(1), dev->wlan.wpdma_rx_rro[1]); in mtk_wed_set_wpdma()
1250 wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING_CFG(i), in mtk_wed_set_wpdma()
1280 wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset); in mtk_wed_hw_init_early()
1281 wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset); in mtk_wed_hw_init_early()
1282 wed_w32(dev, MTK_WED_PCIE_CFG_BASE, in mtk_wed_hw_init_early()
1285 wed_w32(dev, MTK_WED_WDMA_CFG_BASE, dev->hw->wdma_phy); in mtk_wed_hw_init_early()
1287 wed_w32(dev, MTK_WED_WDMA_OFFSET0, in mtk_wed_hw_init_early()
1293 wed_w32(dev, MTK_WED_WDMA_OFFSET1, in mtk_wed_hw_init_early()
1381 wed_w32(dev, MTK_WED_RROQM_MIOD_CFG, in mtk_wed_rro_hw_init()
1387 wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL0, dev->rro.miod_phys); in mtk_wed_rro_hw_init()
1388 wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL1, in mtk_wed_rro_hw_init()
1390 wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL0, dev->rro.fdbk_phys); in mtk_wed_rro_hw_init()
1391 wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL1, in mtk_wed_rro_hw_init()
1393 wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL2, 0); in mtk_wed_rro_hw_init()
1394 wed_w32(dev, MTK_WED_RROQ_BASE_L, dev->rro.ring.desc_phys); in mtk_wed_rro_hw_init()
1400 wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0); in mtk_wed_rro_hw_init()
1401 wed_w32(dev, MTK_WED_RROQM_MIOD_CTRL2, MTK_WED_MIOD_CNT - 1); in mtk_wed_rro_hw_init()
1408 wed_w32(dev, MTK_WED_RESET, MTK_WED_RESET_RX_ROUTE_QM); in mtk_wed_route_qm_hw_init()
1442 wed_w32(dev, MTK_WED_TX_BM_BASE, dev->tx_buf_ring.desc_phys); in mtk_wed_hw_init()
1443 wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE); in mtk_wed_hw_init()
1446 wed_w32(dev, MTK_WED_TX_BM_CTRL, in mtk_wed_hw_init()
1452 wed_w32(dev, MTK_WED_TX_BM_DYN_THR, in mtk_wed_hw_init()
1456 wed_w32(dev, MTK_WED_TX_BM_CTRL, in mtk_wed_hw_init()
1462 wed_w32(dev, MTK_WED_TX_TKID_DYN_THR, in mtk_wed_hw_init()
1465 wed_w32(dev, MTK_WED_TX_BM_DYN_THR, in mtk_wed_hw_init()
1468 wed_w32(dev, MTK_WED_TX_TKID_CTRL, in mtk_wed_hw_init()
1476 wed_w32(dev, dev->hw->soc->regmap.tx_bm_tkid, in mtk_wed_hw_init()
1488 wed_w32(dev, MTK_WED_TX_TKID_CTRL, in mtk_wed_hw_init()
1498 wed_w32(dev, MTK_WED_TX_BM_INIT_PTR, in mtk_wed_hw_init()
1509 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, in mtk_wed_hw_init()
1512 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0); in mtk_wed_hw_init()
1529 wed_w32(dev, MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG, 0); in mtk_wed_hw_init()
1597 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, in mtk_wed_rx_reset()
1601 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, in mtk_wed_rx_reset()
1612 wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0); in mtk_wed_rx_reset()
1625 wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0); in mtk_wed_rx_reset()
1637 wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG, in mtk_wed_rx_reset()
1643 wed_w32(dev, MTK_WED_RRO_RX_D_CFG(2), in mtk_wed_rx_reset()
1685 wed_w32(dev, MTK_WED_RESET_IDX, 0); in mtk_wed_rx_reset()
1746 wed_w32(dev, MTK_WED_RESET_IDX, in mtk_wed_reset_dma()
1748 wed_w32(dev, MTK_WED_RESET_IDX, 0); in mtk_wed_reset_dma()
1757 wed_w32(dev, MTK_WED_WDMA_GLO_CFG, val); in mtk_wed_reset_dma()
1784 wed_w32(dev, MTK_WED_WDMA_RESET_IDX, in mtk_wed_reset_dma()
1788 wed_w32(dev, MTK_WED_WDMA_RESET_IDX, in mtk_wed_reset_dma()
1790 wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0); in mtk_wed_reset_dma()
1832 wed_w32(dev, MTK_WED_RX1_CTRL2, 0); in mtk_wed_reset_dma()
1834 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, in mtk_wed_reset_dma()
1837 wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0); in mtk_wed_reset_dma()
1845 wed_w32(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_WPDMA_IDX_RX); in mtk_wed_reset_dma()
1846 wed_w32(dev, MTK_WED_RESET_IDX, 0); in mtk_wed_reset_dma()
1895 wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE, in mtk_wed_wdma_rx_ring_setup()
1897 wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT, in mtk_wed_wdma_rx_ring_setup()
1946 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_BASE, in mtk_wed_wdma_tx_ring_setup()
1948 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_COUNT, in mtk_wed_wdma_tx_ring_setup()
1950 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_CPU_IDX, in mtk_wed_wdma_tx_ring_setup()
1952 wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_DMA_IDX, in mtk_wed_wdma_tx_ring_setup()
1991 wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, in mtk_wed_configure_irq()
1994 wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, in mtk_wed_configure_irq()
2004 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX, in mtk_wed_configure_irq()
2015 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX_FREE, in mtk_wed_configure_irq()
2022 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX, in mtk_wed_configure_irq()
2036 wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask); in mtk_wed_configure_irq()
2042 wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask); in mtk_wed_configure_irq()
2046 wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask); in mtk_wed_configure_irq()
2047 wed_w32(dev, MTK_WED_INT_MASK, irq_mask); in mtk_wed_configure_irq()
2166 wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask); in mtk_wed_start_hw_rro()
2167 wed_w32(dev, MTK_WED_INT_MASK, irq_mask); in mtk_wed_start_hw_rro()
2179 wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG, in mtk_wed_start_hw_rro()
2182 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RRO_RX, in mtk_wed_start_hw_rro()
2192 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG, in mtk_wed_start_hw_rro()
2242 wed_w32(dev, MTK_WED_RRO_RX_D_RX(idx) + MTK_WED_RING_OFS_BASE, in mtk_wed_rro_rx_ring_setup()
2244 wed_w32(dev, MTK_WED_RRO_RX_D_RX(idx) + MTK_WED_RING_OFS_COUNT, in mtk_wed_rro_rx_ring_setup()
2255 wed_w32(dev, MTK_WED_RRO_MSDU_PG_CTRL0(idx) + MTK_WED_RING_OFS_BASE, in mtk_wed_msdu_pg_rx_ring_setup()
2257 wed_w32(dev, MTK_WED_RRO_MSDU_PG_CTRL0(idx) + MTK_WED_RING_OFS_COUNT, in mtk_wed_msdu_pg_rx_ring_setup()
2270 wed_w32(dev, MTK_WED_IND_CMD_RX_CTRL1 + MTK_WED_RING_OFS_BASE, in mtk_wed_ind_rx_ring_setup()
2273 wed_w32(dev, MTK_WED_IND_CMD_RX_CTRL1 + MTK_WED_RING_OFS_COUNT, in mtk_wed_ind_rx_ring_setup()
2277 wed_w32(dev, MTK_WED_RRO_CFG0, dev->wlan.phy_base + in mtk_wed_ind_rx_ring_setup()
2279 wed_w32(dev, MTK_WED_RRO_CFG1, in mtk_wed_ind_rx_ring_setup()
2286 wed_w32(dev, MTK_WED_ADDR_ELEM_CFG0, in mtk_wed_ind_rx_ring_setup()
2290 wed_w32(dev, MTK_WED_RADDR_ELEM_TBL_WDATA, in mtk_wed_ind_rx_ring_setup()
2292 wed_w32(dev, MTK_WED_ADDR_ELEM_TBL_CFG, in mtk_wed_ind_rx_ring_setup()
2305 wed_w32(dev, MTK_WED_PN_CHECK_WDATA_M, in mtk_wed_ind_rx_ring_setup()
2308 wed_w32(dev, MTK_WED_PN_CHECK_CFG, MTK_WED_PN_CHECK_WR | in mtk_wed_ind_rx_ring_setup()
2320 wed_w32(dev, MTK_WED_RX_IND_CMD_CNT0, MTK_WED_RX_IND_CMD_DBG_CNT_EN); in mtk_wed_ind_rx_ring_setup()
2352 wed_w32(dev, MTK_WED_EXT_INT_MASK1, in mtk_wed_start()
2354 wed_w32(dev, MTK_WED_EXT_INT_MASK2, in mtk_wed_start()
2361 wed_w32(dev, MTK_WED_EXT_INT_MASK3, in mtk_wed_start()
2501 wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG, in mtk_wed_tx_ring_setup()
2504 wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG, 0); in mtk_wed_tx_ring_setup()
2512 wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE, in mtk_wed_tx_ring_setup()
2514 wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT, in mtk_wed_tx_ring_setup()
2516 wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0); in mtk_wed_tx_ring_setup()
2538 wed_w32(dev, MTK_WED_RING_RX(index) + i, val); in mtk_wed_txfree_ring_setup()
2539 wed_w32(dev, MTK_WED_WPDMA_RING_RX(index) + i, val); in mtk_wed_txfree_ring_setup()
2570 wed_w32(dev, MTK_WED_WPDMA_RING_RX_DATA(idx) + MTK_WED_RING_OFS_BASE, in mtk_wed_rx_ring_setup()
2572 wed_w32(dev, MTK_WED_WPDMA_RING_RX_DATA(idx) + MTK_WED_RING_OFS_COUNT, in mtk_wed_rx_ring_setup()
2590 wed_w32(dev, MTK_WED_EXT_INT_STATUS, val); in mtk_wed_irq_get()
2599 wed_w32(dev, MTK_WED_INT_STATUS, val); /* ACK */ in mtk_wed_irq_get()
2608 wed_w32(dev, MTK_WED_INT_MASK, mask); in mtk_wed_irq_set_mask()
2773 .reg_write = wed_w32, in mtk_wed_add_hw()