Lines Matching +full:0 +full:x33c
7 #define MTK_PPE_GLO_CFG 0x200
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
23 #define MTK_PPE_FLOW_CFG 0x204
42 #define MTK_PPE_IP_PROTO_CHK 0x208
43 #define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
46 #define MTK_PPE_TB_CFG 0x21c
47 #define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
63 #define MTK_PPE_BIND_LMT1 0x230
66 #define MTK_PPE_KEEPALIVE 0x234
86 #define MTK_PPE_TB_BASE 0x220
88 #define MTK_PPE_TB_USED 0x224
89 #define MTK_PPE_TB_USED_NUM GENMASK(13, 0)
91 #define MTK_PPE_BIND_RATE 0x228
92 #define MTK_PPE_BIND_RATE_BIND GENMASK(15, 0)
95 #define MTK_PPE_BIND_LIMIT0 0x22c
96 #define MTK_PPE_BIND_LIMIT0_QUARTER GENMASK(13, 0)
99 #define MTK_PPE_BIND_LIMIT1 0x230
100 #define MTK_PPE_BIND_LIMIT1_FULL GENMASK(13, 0)
103 #define MTK_PPE_KEEPALIVE 0x234
104 #define MTK_PPE_KEEPALIVE_TIME GENMASK(15, 0)
108 #define MTK_PPE_UNBIND_AGE 0x238
110 #define MTK_PPE_UNBIND_AGE_DELTA GENMASK(7, 0)
112 #define MTK_PPE_BIND_AGE0 0x23c
114 #define MTK_PPE_BIND_AGE0_DELTA_UDP GENMASK(14, 0)
116 #define MTK_PPE_BIND_AGE1 0x240
118 #define MTK_PPE_BIND_AGE1_DELTA_TCP GENMASK(14, 0)
120 #define MTK_PPE_HASH_SEED 0x244
122 #define MTK_PPE_DEFAULT_CPU_PORT 0x248
123 #define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n) (GENMASK(2, 0) << ((_n) * 4))
125 #define MTK_PPE_DEFAULT_CPU_PORT1 0x24c
127 #define MTK_PPE_MTU_DROP 0x308
129 #define MTK_PPE_VLAN_MTU0 0x30c
130 #define MTK_PPE_VLAN_MTU0_NONE GENMASK(13, 0)
133 #define MTK_PPE_VLAN_MTU1 0x310
134 #define MTK_PPE_VLAN_MTU1_2TAG GENMASK(13, 0)
137 #define MTK_PPE_VPM_TPID 0x318
139 #define MTK_PPE_CACHE_CTL 0x320
140 #define MTK_PPE_CACHE_CTL_EN BIT(0)
146 #define MTK_PPE_MIB_CFG 0x334
147 #define MTK_PPE_MIB_CFG_EN BIT(0)
150 #define MTK_PPE_MIB_TB_BASE 0x338
152 #define MTK_PPE_MIB_SER_CR 0x33C
154 #define MTK_PPE_MIB_SER_CR_ADDR GENMASK(13, 0)
156 #define MTK_PPE_MIB_SER_R0 0x340
157 #define MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW GENMASK(31, 0)
159 #define MTK_PPE_MIB_SER_R1 0x344
161 #define MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH GENMASK(15, 0)
163 #define MTK_PPE_MIB_SER_R2 0x348
164 #define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH GENMASK(23, 0)
166 #define MTK_PPE_MIB_SER_R3 0x34c
168 #define MTK_PPE_MIB_CACHE_CTL 0x350
169 #define MTK_PPE_MIB_CACHE_CTL_EN BIT(0)
172 #define MTK_PPE_SBW_CTRL 0x374