Lines Matching +full:32 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
41 PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
48 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
49 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
50 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
52 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
53 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
57 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
62 P_CLK_ASF_REGS_DIS = 1<<18,/* Disable Clock ASF (Yukon-Ext.) */
64 P_CLK_MACSEC_DIS = 1<<17,/* Disable Clock MACSec (Yukon-Ext.) */
91 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
94 P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */
98 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
114 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
116 /* Bit 31..27: for A3 & later */
118 P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */
119 P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */
120 P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
121 /* Bit 26..16: Release Clock on Event */
122 P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */
134 /* Bit 10.. 0: Mask for Gate Clock */
141 P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */
157 /* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
160 /* Bit 23..21: Release Clock on Event */
163 P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */
164 /* Bit 20..18: Gate Clock on Event */
166 P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */
167 P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */
168 P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
169 P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */
188 /* Yukon-Optima */
208 /* Yukon-Supreme */
230 PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA = 1<<11, /* Disable flip-flop chain for sndmsg_inta */
234 PSM_CONFIG_REG1_DIS_PIG = 1<<7, /* Disable Plug-in-Go SM after PSM Goes back to IDLE */
265 /* Special ISR registers (Yukon-2 only) */
308 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
310 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
366 /* B0_CTST 24 bit Control/Status register */
368 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
369 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
370 Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
371 Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
372 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
373 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
374 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
375 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
376 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
377 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
382 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
389 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
401 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
403 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
404 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
405 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
406 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
423 Y2_IS_PSM_ACK = 1<<7, /* PSM Acknowledge (Yukon-Optima only) */
424 Y2_IS_PTP_TIST = 1<<6, /* PTP Time Stamp (Yukon-Optima only) */
425 Y2_IS_PHY_QLNK = 1<<5, /* PHY Quick Link (Yukon-Optima only) */
443 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
469 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
470 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
495 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
501 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
524 GLB_GPIO_RAND_BIT_1 = 1<<9, /* Random Bit 1 */
527 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
529 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
530 /* Bit 3.. 2: reserved */
535 /* B2_CHIP_ID 8 bit Chip Identification Number */
537 CHIP_ID_YUKON_XL = 0xb3, /* YUKON-2 XL */
538 CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */
539 CHIP_ID_YUKON_EX = 0xb5, /* YUKON-2 Extreme */
540 CHIP_ID_YUKON_EC = 0xb6, /* YUKON-2 EC */
541 CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */
542 CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
543 CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
544 CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
545 CHIP_ID_YUKON_OPT = 0xbc, /* YUKON-2 Optima */
546 CHIP_ID_YUKON_PRM = 0xbd, /* YUKON-2 Optima Prime */
547 CHIP_ID_YUKON_OP_2 = 0xbe, /* YUKON-2 Optima 2 */
558 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
559 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
560 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
590 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
602 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
604 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
612 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
614 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
616 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
617 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
624 /* B2_TI_CTRL 8 bit Timer control */
625 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
632 /* B2_TI_TEST 8 Bit Timer Test */
633 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
634 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
641 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
647 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
648 /* Bit 31..19: reserved */
649 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
652 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
668 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
669 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
670 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
671 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
673 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
675 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
688 * Bank 4 - 5
692 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
693 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
694 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
695 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
696 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
697 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
698 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
730 Q_D = 0x00, /* 8*32 bit Current Descriptor */
731 Q_VLAN = 0x20, /* 16 bit Current VLAN Tag */
732 Q_DONE = 0x24, /* 16 bit Done Index */
733 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
734 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
735 Q_BC = 0x30, /* 32 bit Current Byte Counter */
736 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
737 Q_TEST = 0x38, /* 32 bit Test/Control Register */
739 /* Yukon-2 */
740 Q_WM = 0x40, /* 16 bit FIFO Watermark */
741 Q_AL = 0x42, /* 8 bit FIFO Alignment */
742 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
743 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
744 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
745 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
746 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
747 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
748 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
749 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
753 /* Q_TEST 32 bit Test Register */
765 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
769 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
770 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
771 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
772 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
773 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
774 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
775 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
776 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
777 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
778 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
787 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
788 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
789 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
790 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
791 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
792 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
793 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
794 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
795 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
796 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
797 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
798 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
799 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
800 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
822 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
823 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
824 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
825 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
827 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
829 /* Receive GMAC FIFO (YUKON and Yukon-2) */
831 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
832 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
833 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
834 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
835 RX_GMF_FL_THR = 0x0c50,/* 16 bit Rx GMAC FIFO Flush Threshold */
836 RX_GMF_FL_CTRL = 0x0c52,/* 16 bit Rx GMAC FIFO Flush Control */
837 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
838 RX_GMF_UP_THR = 0x0c58,/* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
839 RX_GMF_LP_THR = 0x0c5a,/* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
840 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
841 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
843 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
845 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
847 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
851 /* Q_BC 32 bit Current Byte Counter */
854 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
855 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
856 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
857 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
858 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
859 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
860 /* Q_CSR 32 bit BMU Control/Status Register */
862 /* Rx BMU Control / Status Registers (Yukon-2) */
894 /* Tx BMU Control / Status Registers (Yukon-2) */
895 /* Bit 31: same as for Rx */
938 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
939 /* PREF_UNIT_CTRL 32 bit Prefetch Control register */
948 /* RB_START 32 bit RAM Buffer Start Address */
949 /* RB_END 32 bit RAM Buffer End Address */
950 /* RB_WP 32 bit RAM Buffer Write Pointer */
951 /* RB_RP 32 bit RAM Buffer Read Pointer */
952 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
953 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
954 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
955 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
956 /* RB_PC 32 bit RAM Buffer Packet Counter */
957 /* RB_LEV 32 bit RAM Buffer Level Register */
959 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
960 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
961 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
963 /* RB_CTRL 8 bit RAM Buffer Control Register */
976 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
977 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
978 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
980 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
981 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
982 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
984 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
985 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
986 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
988 /* Threshold values for Yukon-EC Ultra and Extreme */
996 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
997 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
998 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
1000 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
1005 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
1006 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
1007 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
1010 /* Polling Unit Registers (Yukon-2 only) */
1012 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
1013 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
1015 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
1016 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
1020 SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */
1021 SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */
1025 CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */
1026 CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */
1027 CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */
1028 CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */
1029 CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */
1030 CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */
1031 HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */
1032 CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */
1033 HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */
1034 HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */
1037 /* ASF Subsystem Registers (Yukon-2 only) */
1039 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
1040 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
1041 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
1043 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
1044 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
1045 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
1046 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
1047 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
1048 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
1051 /* Status BMU Registers (Yukon-2 only)*/
1053 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
1054 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
1056 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
1057 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
1058 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
1059 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
1060 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
1061 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
1062 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
1063 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
1065 /* FIFO Control/Status Registers (Yukon-2 only)*/
1066 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
1067 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
1068 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
1069 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
1070 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
1071 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
1072 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
1074 /* Level and ISR Timer Registers (Yukon-2 only)*/
1075 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
1076 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
1077 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
1078 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
1079 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
1080 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
1081 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
1082 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
1083 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
1084 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
1085 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
1086 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
1100 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
1101 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
1102 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
1103 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
1104 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
1106 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
1107 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
1108 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
1109 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
1110 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
1111 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
1114 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
1115 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
1118 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
1119 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
1135 * Marvel-PHY Registers, indirect addressed over GMAC
1138 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1139 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1140 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1141 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1142 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1143 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1144 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1145 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1146 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1147 /* Marvel-specific registers */
1148 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1149 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1150 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1151 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
1152 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
1153 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1154 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1155 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
1156 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1157 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1158 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1159 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1160 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1161 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1162 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1163 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1164 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1165 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1168 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1169 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1170 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1171 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1172 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1176 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1177 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1178 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1179 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1180 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1181 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1182 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1183 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1184 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1185 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1195 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1197 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1198 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1199 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occurred */
1200 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1201 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1202 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1203 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1207 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1208 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1209 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1222 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1223 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1224 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1225 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
1226 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
1231 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1232 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1233 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1235 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1236 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1237 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1238 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1239 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1240 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1241 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1242 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1243 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1249 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1250 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1252 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1253 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1254 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1255 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1256 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1257 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1258 /* Bit 9..8: reserved */
1259 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1262 /** Marvell-Specific */
1270 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1271 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1272 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1273 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1274 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1275 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1282 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1283 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1288 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1289 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1290 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1291 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1294 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1296 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1299 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1304 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1306 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1307 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1310 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1312 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1333 /* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
1351 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1354 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1356 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1364 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1383 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1387 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1406 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1412 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1414 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1416 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1421 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1422 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1427 PHY_M_10B_TE_ENABLE = 1<<7, /* 10Base-Te Enable (88E8079 and above) */
1438 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1441 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
1454 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1457 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1459 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1462 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1467 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1478 /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1480 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1481 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1482 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1483 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1484 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1485 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1516 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1517 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1519 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1520 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1521 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1522 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1523 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1524 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1533 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1539 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1542 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1553 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1555 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1559 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1560 /* Bit 15..12: reserved (used internally) */
1562 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1563 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1564 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1590 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1594 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1597 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1598 /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
1605 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1606 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1608 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1610 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1612 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1616 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1618 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1619 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1620 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1621 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1632 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1633 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1634 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1635 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1636 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1637 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1638 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1640 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1641 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1642 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1643 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1644 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1645 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1648 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1649 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1650 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1651 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1654 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1655 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1656 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1659 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1660 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1661 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1664 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1665 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1666 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1674 * MIB Counters base address definitions (low word) -
1675 * use offset 4 for access to high word (32 bit r/o)
1682 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1691 GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
1692 GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
1693 GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
1694 GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
1695 GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
1696 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
1708 GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
1709 GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
1710 GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
1711 GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
1712 GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
1713 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
1723 /* GMAC Bit Definitions */
1724 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1726 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1727 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1728 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1729 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1730 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1731 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1732 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occurred */
1733 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occurred */
1735 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1736 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1737 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1738 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1739 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1742 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1744 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1745 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1746 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1747 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1748 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1749 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1750 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1751 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1752 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1753 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1754 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1755 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1756 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1757 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1758 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1763 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1765 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1766 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1767 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1768 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1774 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1776 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1777 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1778 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1779 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1782 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1784 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1785 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1786 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1787 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1801 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1803 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1808 GM_NEW_FLOW_CTRL = 1<<6, /* Enable New Flow-Control */
1810 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1820 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1822 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1823 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1824 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1825 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1826 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1832 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1834 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1835 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1840 GMR_FS_LEN = 0x7fff<<16, /* Bit 30..16: Rx Frame Length */
1847 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1848 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1862 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1907 /* RX_GMF_FL_CTRL 16 bit Rx GMAC FIFO Flush Control (Yukon-Supreme) */
1917 RX_FLSH_MISSPKT_ENA = 1<<1, /* RX Flush Miss-Packet Enable */
1918 RX_FLSH_MISSPKT_DIS = 1<<0, /* RX Flush Miss-Packet Disable */
1921 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1923 TX_DYN_WM_ENA = 3, /* Yukon-FE+ specific */
1926 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1946 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1953 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1965 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
2004 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
2013 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
2034 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
2062 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
2063 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2075 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2082 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
2139 /* YUKON-2 STATUS opcodes defines */
2311 return !(hw->flags & SKY2_HW_FIBRE_PHY); in sky2_is_copper()
2317 return readl(hw->regs + reg); in sky2_read32()
2322 return readw(hw->regs + reg); in sky2_read16()
2327 return readb(hw->regs + reg); in sky2_read8()
2332 writel(val, hw->regs + reg); in sky2_write32()
2337 writew(val, hw->regs + reg); in sky2_write16()
2342 writeb(val, hw->regs + reg); in sky2_write8()
2347 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2368 | (u64) sky2_read16(hw, base+8) << 32 in gma_read64()
2372 /* There is no way to atomically read32 bit values from PHY, so retry */