Lines Matching +full:reset +full:- +full:pin +full:- +full:assert +full:- +full:time +full:- +full:ms
1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
143 CS_MRST_CLR = 1<<3, /* Clear Master reset */
144 CS_MRST_SET = 1<<2, /* Set Master reset */
145 CS_RST_CLR = 1<<1, /* Clear Software reset */
146 CS_RST_SET = 1, /* Set Software reset */
217 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
223 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
224 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
268 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
269 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
302 GP_IO_9 = 1<<9, /* IO_9 pin */
303 GP_IO_8 = 1<<8, /* IO_8 pin */
304 GP_IO_7 = 1<<7, /* IO_7 pin */
305 GP_IO_6 = 1<<6, /* IO_6 pin */
306 GP_IO_5 = 1<<5, /* IO_5 pin */
307 GP_IO_4 = 1<<4, /* IO_4 pin */
308 GP_IO_3 = 1<<3, /* IO_3 pin */
309 GP_IO_2 = 1<<2, /* IO_2 pin */
310 GP_IO_1 = 1<<1, /* IO_1 pin */
311 GP_IO_0 = 1<<0, /* IO_0 pin */
366 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
367 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
375 MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
376 MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
401 PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
402 PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
430 * Bank 4 - 5
489 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
544 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
574 MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
575 MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
576 MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
593 MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
594 MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
629 MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
630 MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
708 CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
709 CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
710 CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
711 CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
713 CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
715 CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
717 CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
719 CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
721 CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
772 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
773 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
798 #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
799 #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
801 #define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
803 #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
804 /* 215 ms at 78.12 MHz */
832 /* Time Stamp Timer Registers (YUKON only) */
833 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
834 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
835 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
856 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
858 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
908 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
927 ,* XMAC-PHY Registers, indirect addressed over the XMAC
934 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
936 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
944 * Broadcom-PHY Registers, indirect addressed over XMAC
951 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
953 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
956 /* Broadcom-specific registers */
957 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
958 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
973 * Marvel-PHY Registers, indirect addressed over GMAC
980 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
982 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
985 /* Marvel-specific registers */
986 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
987 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1017 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1020 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1036 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1038 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1062 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1063 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1064 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1076 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1077 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1078 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1079 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1127 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1130 /* Broadcom-Specific */
1131 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1141 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1142 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1156 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1157 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1158 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1159 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1164 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1169 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1173 PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
1200 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1246 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1247 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1285 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1286 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1289 /** Marvell-Specific */
1297 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1298 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1299 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1300 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1301 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1309 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1310 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1321 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1326 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1335 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1402 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1406 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1441 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1484 PULS_21MS = 1, /* 21 ms to 42 ms */
1485 PULS_42MS = 2, /* 42 ms to 84 ms */
1486 PULS_84MS = 3, /* 84 ms to 170 ms */
1487 PULS_170MS = 4, /* 170 ms to 340 ms */
1488 PULS_340MS = 5, /* 340 ms to 670 ms */
1489 PULS_670MS = 6, /* 670 ms to 1.3 s */
1495 BLINK_42MS = 0, /* 42 ms */
1496 BLINK_84MS = 1, /* 84 ms */
1497 BLINK_170MS = 2, /* 170 ms */
1498 BLINK_340MS = 3, /* 340 ms */
1499 BLINK_670MS = 4, /* 670 ms */
1599 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1623 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1661 * MIB Counters base address definitions (low word) -
1678 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1679 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1680 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1681 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1682 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1683 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1696 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1697 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1698 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1699 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1700 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1701 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1716 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1726 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1733 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1742 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1744 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1745 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1746 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1754 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1767 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1793 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1830 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1831 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1865 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1866 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1883 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1885 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1886 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1887 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1898 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1899 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1904 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1926 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1927 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1940 /* auto-negotiation with limited advertised speeds */
1967 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1968 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
2027 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2044 XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */
2045 XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */
2071 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2072 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2073 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2074 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2075 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2101 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2102 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2103 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2104 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2105 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2166 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2168 XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */
2169 XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */
2170 XM_GP_INP_ASS = 1<<0, /* Bit 0: (ro) GP Input Pin asserted */
2184 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2185 XM_IS_TSC_OV = 1<<6, /* Bit 6: Time Stamp Counter Overflow */
2254 XM_MD_ATS = 1<<19, /* Bit 19: Append Time Stamp */
2296 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2297 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2298 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2299 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2300 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2318 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2319 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2333 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2334 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2335 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2336 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2337 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2350 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2427 FLOW_MODE_NONE = 1, /* No Flow-Control */
2478 return readl(hw->regs + reg); in skge_read32()
2483 return readw(hw->regs + reg); in skge_read16()
2488 return readb(hw->regs + reg); in skge_read8()
2493 writel(val, hw->regs + reg); in skge_write32()
2498 writew(val, hw->regs + reg); in skge_write16()
2503 writeb(val, hw->regs + reg); in skge_write8()
2509 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2553 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))