Lines Matching +full:32 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
164 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
168 /* Bit 30: reserved */
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
238 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
250 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
252 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
253 /* Bit 3.. 2: reserved */
258 /* B2_CHIP_ID 8 bit Chip Identification Number */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
266 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
268 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
269 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
272 /* B2_TI_CTRL 8 bit Timer control */
273 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
280 /* B2_TI_TEST 8 Bit Timer Test */
281 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
282 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
289 /* B2_GP_IO 32 bit General Purpose I/O Register */
314 /* Descriptor Bit Definition */
318 BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
326 BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
331 /* Bit 23..16: BMU Check Opcodes */
335 BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
338 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
344 /* B2_BSC_STAT 8 bit Blink Source Counter Status */
349 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
356 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
357 /* Bit 31..19: reserved */
358 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
361 /* B3_RI_CTRL 16 bit RAM Iface Control Register */
371 /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
387 /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
410 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
411 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
412 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
413 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
415 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
417 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
430 * Bank 4 - 5
434 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
435 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
436 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
437 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
438 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
439 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
440 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
459 Q_D = 0x00, /* 8*32 bit Current Descriptor */
460 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
461 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
462 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
463 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
464 Q_BC = 0x30, /* 32 bit Current Byte Counter */
465 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
466 Q_F = 0x38, /* 32 bit Flag Register */
467 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
468 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
469 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
470 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
471 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
472 Q_T2 = 0x40, /* 32 bit Test Register 2 */
473 Q_T3 = 0x44, /* 32 bit Test Register 3 */
481 RB_START= 0x00,/* 32 bit RAM Buffer Start Address */
482 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
483 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
484 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
485 RB_RX_UTPP= 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
486 RB_RX_LTPP= 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
487 RB_RX_UTHP= 0x18,/* 32 bit Rx Upper Threshold, High Prio */
488 RB_RX_LTHP= 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
489 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
490 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
491 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
492 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
493 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
494 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
536 RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
537 RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
539 RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
540 RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
541 RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
542 RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
543 RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
544 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
545 RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
546 RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
547 RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
549 RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
550 RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
551 RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
552 RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
554 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
555 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
556 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
557 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
558 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
562 /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
581 /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
600 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
601 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
612 /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
613 /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
624 /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
625 /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
636 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
637 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
638 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
645 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
646 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
647 /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
654 /* LNK_LED_REG 8 bit Link LED Register */
666 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
667 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
668 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
669 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
670 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
671 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
672 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
673 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
674 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
678 /* TXA_TEST 8 bit Tx Arbiter Test Register */
688 /* TXA_STAT 8 bit Tx Arbiter Status Register */
694 /* Q_BC 32 bit Current Byte Counter */
697 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
698 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
699 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
700 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
701 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
702 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
703 /* Q_CSR 32 bit BMU Control/Status Register */
739 /* Q_F 32 bit Flag Register */
743 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
746 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
747 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
751 /* RB_START 32 bit RAM Buffer Start Address */
752 /* RB_END 32 bit RAM Buffer End Address */
753 /* RB_WP 32 bit RAM Buffer Write Pointer */
754 /* RB_RP 32 bit RAM Buffer Read Pointer */
755 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
756 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
757 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
758 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
759 /* RB_PC 32 bit RAM Buffer Packet Counter */
760 /* RB_LEV 32 bit RAM Buffer Level Register */
762 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
763 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
764 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
766 /* RB_CTRL 8 bit RAM Buffer Control Register */
778 TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
779 TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
780 TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
781 TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
782 TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
783 TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
784 TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
785 TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
787 TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
788 TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
789 TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
791 TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
792 TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
793 TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
794 TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
813 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
814 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
815 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
817 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
818 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
819 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
821 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
822 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
823 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
826 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
827 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
828 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
830 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
833 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
834 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
835 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
850 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
851 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
852 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
853 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
854 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
856 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
858 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
860 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
861 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
862 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
863 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
864 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
868 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
869 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
873 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
874 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
895 XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
897 XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
898 XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
899 XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
900 XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
901 XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
903 XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
904 XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
905 XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
906 XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
907 XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
908 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
909 XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
910 XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
911 XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
912 XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
913 XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
914 XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
921 * XMR_FS_ERR unless the corresponding bit in the Receive Command
927 ,* XMAC-PHY Registers, indirect addressed over the XMAC
930 PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
931 PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
932 PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
933 PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
934 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
935 PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
936 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
937 PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
938 PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
940 PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
941 PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
944 * Broadcom-PHY Registers, indirect addressed over XMAC
947 PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
948 PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
949 PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
950 PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
951 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
952 PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
953 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
954 PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
955 PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
956 /* Broadcom-specific registers */
957 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
958 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
959 PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
960 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
961 PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
962 PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
963 PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
964 PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
966 PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
967 PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
968 PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
969 PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
973 * Marvel-PHY Registers, indirect addressed over GMAC
976 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
977 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
978 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
979 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
980 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
981 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
982 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
983 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
984 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
985 /* Marvel-specific registers */
986 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
987 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
988 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
989 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
990 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
991 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
992 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
993 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
994 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
995 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
996 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
997 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
998 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
999 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1000 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1001 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1002 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1003 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1006 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1007 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1008 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1009 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1010 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1014 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1015 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1016 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1017 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1018 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1019 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1020 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1021 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1022 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1023 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1033 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1035 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1036 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1037 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occurred */
1038 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1039 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1040 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1041 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1045 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1046 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1047 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1062 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1063 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1064 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1069 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1070 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1071 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1073 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1074 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1075 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1076 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1077 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1078 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1079 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1080 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1081 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1089 PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1090 PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1091 PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
1093 PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
1094 PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
1095 PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
1100 PHY_X_P_NO_PAUSE= 0<<7,/* Bit 8..7: no Pause Mode */
1101 PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
1102 PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
1103 PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
1107 /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/
1109 PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */
1110 PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */
1113 /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/
1115 PHY_X_RS_PAUSE = 3<<7, /* Bit 8..7: selected Pause Mode */
1116 PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
1117 PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
1118 PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */
1119 PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */
1124 X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */
1125 X_RFB_LF = 1<<12,/* Bit 13..12 Link Failure */
1126 X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */
1127 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1130 /* Broadcom-Specific */
1131 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1133 PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1134 PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1135 PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1136 PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1137 PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1138 PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1141 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1142 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1144 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1145 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1146 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1147 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1148 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1149 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1150 /* Bit 9..8: reserved */
1151 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1154 /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
1156 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1157 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1158 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1159 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1162 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1164 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1165 PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
1166 PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
1167 PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
1168 PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
1169 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1170 PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
1171 PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
1172 PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
1173 PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
1174 PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
1175 PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
1176 PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
1177 PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
1178 PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
1179 PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
1182 /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
1184 PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
1185 PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
1186 PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
1187 PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
1188 PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
1189 PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
1190 PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
1191 PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
1192 PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
1193 PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
1194 PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
1195 PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
1196 PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
1197 PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
1200 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1201 /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
1203 PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1205 PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1206 PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1210 /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1212 PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
1214 /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
1215 PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
1216 PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
1218 /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
1219 PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */
1220 PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */
1221 PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */
1222 /* Bit 11: reserved */
1223 PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
1224 /* Bit 9.. 8: reserved */
1225 PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */
1226 /* Bit 6: reserved */
1227 PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
1228 /* Bit 4: reserved */
1229 PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
1232 /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
1234 PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */
1235 PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */
1236 PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */
1237 PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */
1238 PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
1239 PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */
1240 PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */
1241 PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */
1242 PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
1243 PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */
1244 PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */
1245 PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */
1246 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1247 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1251 /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1252 /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1254 PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */
1255 PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */
1256 PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */
1257 PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
1258 PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */
1259 PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */
1260 PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */
1261 PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */
1262 PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */
1263 PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
1264 PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */
1265 PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
1266 PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */
1267 PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
1268 PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
1276 PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
1277 PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1278 PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1279 PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1285 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1286 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1289 /** Marvell-Specific */
1297 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1298 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1299 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1300 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1301 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1302 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1309 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1310 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1315 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1316 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1317 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1318 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1321 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1323 PHY_M_1000C_TEST= 7<<13,/* Bit 15..13: Test Modes */
1326 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1331 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1333 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1334 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1337 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1339 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1370 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1373 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1375 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1383 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1402 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1406 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1425 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1431 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1433 PHY_M_EC_S_DSC_MSK = 3<<8, /* Bit 9.. 8: Slave Downshift Counter */
1435 PHY_M_EC_M_DSC_MSK2 = 7<<9, /* Bit 11.. 9: Master Downshift Counter */
1440 PHY_M_EC_MAC_S_MSK = 7<<4, /* Bit 6.. 4: Def. MAC interface speed */
1441 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1458 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1461 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1463 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1466 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1473 PHY_M_LEDC_LINK_MSK = 3<<3, /* Bit 4.. 3: Link Control Mask */
1502 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1503 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1504 /* Bit 13..12: reserved */
1505 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1506 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1507 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1508 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1509 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1510 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1519 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1525 PHY_M_EC2_FO_AM_MSK = 7, /* Bit 2.. 0: Fiber Output Amplitude */
1528 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1538 /* Bit 9.. 4: reserved (88E1011 only) */
1539 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1541 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1544 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1549 PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
1550 PHY_M_CABD_AMPL_MSK = 0x1f<<8, /* Bit 12.. 8: Amplitude Mask */
1552 PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
1564 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1565 /* Bit 15..12: reserved (used internally) */
1567 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1568 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1569 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1595 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1599 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1603 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1605 PHY_M_LEDC_LOS_MSK = 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
1606 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1607 PHY_M_LEDC_STA1_MSK = 0xf<<4, /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1608 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1619 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1620 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1621 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1622 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1623 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1624 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1625 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1627 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1628 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1629 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1630 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1631 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1632 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1635 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1636 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1637 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1638 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1641 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1642 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1643 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1646 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1647 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1648 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1651 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1652 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1653 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1661 * MIB Counters base address definitions (low word) -
1662 * use offset 4 for access to high word (32 bit r/o)
1669 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1678 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1679 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1680 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1681 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1682 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1683 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1696 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1697 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1698 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1699 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1700 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1701 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1711 /* GMAC Bit Definitions */
1712 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1714 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1715 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1716 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1717 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1718 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1719 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1720 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occurred */
1721 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occurred */
1723 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1724 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1725 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1726 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1727 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1730 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1732 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1733 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1734 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1735 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1736 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1737 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1738 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1739 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1740 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1741 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1742 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1743 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1744 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1745 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1746 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1752 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1754 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1755 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1756 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1757 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1763 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1765 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1766 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1767 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1768 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1771 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1773 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1774 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1775 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1787 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1789 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1790 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1791 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1792 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1793 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1802 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1804 GM_SMI_CT_PHY_A_MSK = 0x1f<<11, /* Bit 15..11: PHY Device Address */
1805 GM_SMI_CT_REG_A_MSK = 0x1f<<6, /* Bit 10.. 6: PHY Register Address */
1806 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1807 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1808 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1814 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1816 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1817 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1822 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1824 GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
1825 GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
1826 GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
1827 GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
1828 GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
1829 GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
1830 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1831 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1832 GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
1833 GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
1834 GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
1836 GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
1837 GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
1850 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1872 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1883 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1890 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1902 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1904 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1920 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1921 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1922 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1923 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1924 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1940 /* auto-negotiation with limited advertised speeds */
1953 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1954 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1965 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1971 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1998 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
2004 XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
2005 XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
2006 XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
2007 XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
2008 XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
2009 XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
2010 XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
2011 XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
2012 XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
2013 XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
2014 XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
2015 XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
2016 XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
2017 XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
2018 XM_ISRC = 0x0048, /* 16 bit r/o Interrupt Status Register */
2019 XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
2020 XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2021 XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2022 XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
2023 XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
2025 XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
2026 XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2027 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2028 XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
2037 XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
2038 XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
2039 XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
2040 XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
2041 XM_DEV_ID = 0x0120, /* 32 bit r/o Device ID Register */
2042 XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
2044 XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */
2045 XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */
2046 XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
2047 XM_RX_CNT_EV = 0x0204, /* 32 bit r/o Rx Counter Event Register */
2048 XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */
2049 XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
2050 XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2051 XM_TXF_OK = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
2052 XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
2053 XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
2054 XM_TXF_BC_OK = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
2055 XM_TXF_MC_OK = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
2056 XM_TXF_UC_OK = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
2057 XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
2058 XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
2059 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2060 XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
2061 XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
2062 XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
2063 XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
2064 XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
2065 XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
2066 XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
2067 XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
2068 XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
2069 XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */
2070 XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
2071 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2072 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2073 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2074 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2075 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2076 XM_RXF_OK = 0x0300, /* 32 bit r/o Frames Received OK */
2077 XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
2078 XM_RXO_OK_LO = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
2079 XM_RXF_BC_OK = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
2080 XM_RXF_MC_OK = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
2081 XM_RXF_UC_OK = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
2082 XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
2083 XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
2084 XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
2085 XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
2086 XM_RXE_BURST = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
2087 XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
2088 XM_RXF_FRA_ERR = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
2089 XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
2090 XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
2091 XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
2092 XM_RXF_LEN_ERR = 0x0340, /* 32 bit r/o Rx in Range Length Error */
2093 XM_RXE_SYM_ERR = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
2094 XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
2095 XM_RXE_RUNT = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
2096 XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
2097 XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
2098 XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
2099 XM_RXP_UTIL = 0x0360, /* 32 bit r/o Rx Utilization in % */
2100 XM_RXF_64B = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
2101 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2102 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2103 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2104 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2105 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2108 /* XM_MMU_CMD 16 bit r/w MMU Command Register */
2110 XM_MMU_PHY_RDY = 1<<12, /* Bit 12: PHY Read Ready */
2111 XM_MMU_PHY_BUSY = 1<<11, /* Bit 11: PHY Busy */
2112 XM_MMU_IGN_PF = 1<<10, /* Bit 10: Ignore Pause Frame */
2113 XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
2114 XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
2115 XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
2116 XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
2117 XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
2118 XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
2119 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
2120 XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
2121 XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
2125 /* XM_TX_CMD 16 bit r/w Transmit Command Register */
2127 XM_TX_BK2BK = 1<<6, /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
2128 XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */
2129 XM_TX_SAM_LINE = 1<<4, /* Bit 4: (sc) Start utilization calculation */
2130 XM_TX_NO_GIG_MD = 1<<3, /* Bit 3: Disable Carrier Extension */
2131 XM_TX_NO_PRE = 1<<2, /* Bit 2: Disable Preamble Generation */
2132 XM_TX_NO_CRC = 1<<1, /* Bit 1: Disable CRC Generation */
2133 XM_TX_AUTO_PAD = 1<<0, /* Bit 0: Enable Automatic Padding */
2136 /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
2137 #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
2140 /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
2141 #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
2144 /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
2145 #define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
2148 /* XM_RX_CMD 16 bit r/w Receive Command Register */
2150 XM_RX_LENERR_OK = 1<<8, /* Bit 8 don't set Rx Err bit for */
2152 XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 don't set Rx Err bit for */
2154 XM_RX_IPG_CAP = 1<<6, /* Bit 6 repl. type field with IPG */
2155 XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
2156 XM_RX_STRIP_FCS = 1<<4, /* Bit 4: Enable FCS Stripping */
2157 XM_RX_SELF_RX = 1<<3, /* Bit 3: Enable Rx of own packets */
2158 XM_RX_SAM_LINE = 1<<2, /* Bit 2: (sc) Start utilization calculation */
2159 XM_RX_STRIP_PAD = 1<<1, /* Bit 1: Strip pad bytes of Rx frames */
2160 XM_RX_DIS_CEXT = 1<<0, /* Bit 0: Disable carrier ext. check */
2164 /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
2166 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2167 XM_GP_FRC_INT = 1<<5, /* Bit 5: (sc) Force Interrupt */
2168 XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */
2169 XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */
2170 XM_GP_INP_ASS = 1<<0, /* Bit 0: (ro) GP Input Pin asserted */
2174 /* XM_IMSK 16 bit r/w Interrupt Mask Register */
2175 /* XM_ISRC 16 bit r/o Interrupt Status Register */
2177 XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */
2178 XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */
2179 XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */
2180 XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */
2181 XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */
2182 XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */
2183 XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */
2184 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2185 XM_IS_TSC_OV = 1<<6, /* Bit 6: Time Stamp Counter Overflow */
2186 XM_IS_RXC_OV = 1<<5, /* Bit 5: Rx Counter Event Overflow */
2187 XM_IS_TXC_OV = 1<<4, /* Bit 4: Tx Counter Event Overflow */
2188 XM_IS_RXF_OV = 1<<3, /* Bit 3: Receive FIFO Overflow */
2189 XM_IS_TXF_UR = 1<<2, /* Bit 2: Transmit FIFO Underrun */
2190 XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */
2191 XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */
2196 /* XM_HW_CFG 16 bit r/w Hardware Config Register */
2198 XM_HW_GEN_EOP = 1<<3, /* Bit 3: generate End of Packet pulse */
2199 XM_HW_COM4SIG = 1<<2, /* Bit 2: use Comma Detect for Sig. Det.*/
2200 XM_HW_GMII_MD = 1<<0, /* Bit 0: GMII Interface selected */
2204 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
2205 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
2206 #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
2208 /* XM_TX_THR 16 bit r/w Tx Request Threshold */
2209 /* XM_HT_THR 16 bit r/w Host Request Threshold */
2210 /* XM_RX_THR 16 bit r/w Rx Request Threshold */
2211 #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
2214 /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
2216 XM_ST_VALID = (1UL<<31), /* Bit 31: Status Valid */
2217 XM_ST_BYTE_CNT = (0x3fffL<<17), /* Bit 30..17: Tx frame Length */
2218 XM_ST_RETRY_CNT = (0x1fL<<12), /* Bit 16..12: Retry Count */
2219 XM_ST_EX_COL = 1<<11, /* Bit 11: Excessive Collisions */
2220 XM_ST_EX_DEF = 1<<10, /* Bit 10: Excessive Deferral */
2221 XM_ST_BURST = 1<<9, /* Bit 9: p. xmitted in burst md*/
2222 XM_ST_DEFER = 1<<8, /* Bit 8: packet was defered */
2223 XM_ST_BC = 1<<7, /* Bit 7: Broadcast packet */
2224 XM_ST_MC = 1<<6, /* Bit 6: Multicast packet */
2225 XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */
2226 XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occurred */
2227 XM_ST_CS_ERR = 1<<3, /* Bit 3: Carrier Sense Error */
2228 XM_ST_LAT_COL = 1<<2, /* Bit 2: Late Collision Error */
2229 XM_ST_MUL_COL = 1<<1, /* Bit 1: Multiple Collisions */
2230 XM_ST_SGN_COL = 1<<0, /* Bit 0: Single Collision */
2233 /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
2234 /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
2235 #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
2238 /* XM_DEV_ID 32 bit r/o Device ID Register */
2239 #define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
2240 #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
2243 /* XM_MODE 32 bit r/w Mode Register */
2245 XM_MD_ENA_REJ = 1<<26, /* Bit 26: Enable Frame Reject */
2246 XM_MD_SPOE_E = 1<<25, /* Bit 25: Send Pause on Edge */
2248 XM_MD_TX_REP = 1<<24, /* Bit 24: Transmit Repeater Mode */
2249 XM_MD_SPOFF_I = 1<<23, /* Bit 23: Send Pause on FIFO full */
2251 XM_MD_LE_STW = 1<<22, /* Bit 22: Rx Stat Word in Little Endian */
2252 XM_MD_TX_CONT = 1<<21, /* Bit 21: Send Continuous */
2253 XM_MD_TX_PAUSE = 1<<20, /* Bit 20: (sc) Send Pause Frame */
2254 XM_MD_ATS = 1<<19, /* Bit 19: Append Time Stamp */
2255 XM_MD_SPOL_I = 1<<18, /* Bit 18: Send Pause on Low */
2257 XM_MD_SPOH_I = 1<<17, /* Bit 17: Send Pause on High */
2259 XM_MD_CAP = 1<<16, /* Bit 16: Check Address Pair */
2260 XM_MD_ENA_HASH = 1<<15, /* Bit 15: Enable Hashing */
2261 XM_MD_CSA = 1<<14, /* Bit 14: Check Station Address */
2262 XM_MD_CAA = 1<<13, /* Bit 13: Check Address Array */
2263 XM_MD_RX_MCTRL = 1<<12, /* Bit 12: Rx MAC Control Frame */
2264 XM_MD_RX_RUNT = 1<<11, /* Bit 11: Rx Runt Frames */
2265 XM_MD_RX_IRLE = 1<<10, /* Bit 10: Rx in Range Len Err Frame */
2266 XM_MD_RX_LONG = 1<<9, /* Bit 9: Rx Long Frame */
2267 XM_MD_RX_CRCE = 1<<8, /* Bit 8: Rx CRC Error Frame */
2268 XM_MD_RX_ERR = 1<<7, /* Bit 7: Rx Error Frame */
2269 XM_MD_DIS_UC = 1<<6, /* Bit 6: Disable Rx Unicast */
2270 XM_MD_DIS_MC = 1<<5, /* Bit 5: Disable Rx Multicast */
2271 XM_MD_DIS_BC = 1<<4, /* Bit 4: Disable Rx Broadcast */
2272 XM_MD_ENA_PROM = 1<<3, /* Bit 3: Enable Promiscuous */
2273 XM_MD_ENA_BE = 1<<2, /* Bit 2: Enable Big Endian */
2274 XM_MD_FTF = 1<<1, /* Bit 1: (sc) Flush Tx FIFO */
2275 XM_MD_FRF = 1<<0, /* Bit 0: (sc) Flush Rx FIFO */
2282 /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
2284 XM_SC_SNP_RXC = 1<<5, /* Bit 5: (sc) Snap Rx Counters */
2285 XM_SC_SNP_TXC = 1<<4, /* Bit 4: (sc) Snap Tx Counters */
2286 XM_SC_CP_RXC = 1<<3, /* Bit 3: Copy Rx Counters Continuously */
2287 XM_SC_CP_TXC = 1<<2, /* Bit 2: Copy Tx Counters Continuously */
2288 XM_SC_CLR_RXC = 1<<1, /* Bit 1: (sc) Clear Rx Counters */
2289 XM_SC_CLR_TXC = 1<<0, /* Bit 0: (sc) Clear Tx Counters */
2293 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
2294 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
2296 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2297 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2298 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2299 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2300 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2301 XMR_64B_OV = 1<<26, /* Bit 26: 64 Byte Rx Cnt Ov */
2302 XMR_UTIL_OV = 1<<25, /* Bit 25: Rx Util Cnt Overflow */
2303 XMR_UTIL_UR = 1<<24, /* Bit 24: Rx Util Cnt Underrun */
2304 XMR_CEX_ERR_OV = 1<<23, /* Bit 23: CEXT Err Cnt Ov */
2305 XMR_FCS_ERR_OV = 1<<21, /* Bit 21: Rx FCS Error Cnt Ov */
2306 XMR_LNG_ERR_OV = 1<<20, /* Bit 20: Rx too Long Err Cnt Ov*/
2307 XMR_RUNT_OV = 1<<19, /* Bit 19: Runt Event Cnt Ov */
2308 XMR_SHT_ERR_OV = 1<<18, /* Bit 18: Rx Short Ev Err Cnt Ov*/
2309 XMR_SYM_ERR_OV = 1<<17, /* Bit 17: Rx Sym Err Cnt Ov */
2310 XMR_CAR_ERR_OV = 1<<15, /* Bit 15: Rx Carr Ev Err Cnt Ov */
2311 XMR_JAB_PKT_OV = 1<<14, /* Bit 14: Rx Jabb Packet Cnt Ov */
2312 XMR_FIFO_OV = 1<<13, /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
2313 XMR_FRA_ERR_OV = 1<<12, /* Bit 12: Rx Framing Err Cnt Ov */
2314 XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */
2315 XMR_BURST = 1<<10, /* Bit 10: Rx Burst Event Cnt Ov */
2316 XMR_INV_MOC = 1<<9, /* Bit 9: Rx with inv. MAC OC Ov*/
2317 XMR_INV_MP = 1<<8, /* Bit 8: Rx inv Pause Frame Ov */
2318 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2319 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2320 XMR_UC_OK_OV = 1<<5, /* Bit 5: Rx Unicast Frame CntOv*/
2321 XMR_MC_OK_OV = 1<<4, /* Bit 4: Rx Multicast Cnt Ov */
2322 XMR_BC_OK_OV = 1<<3, /* Bit 3: Rx Broadcast Cnt Ov */
2323 XMR_OK_LO_OV = 1<<2, /* Bit 2: Octets Rx OK Low CntOv*/
2324 XMR_OK_HI_OV = 1<<1, /* Bit 1: Octets Rx OK Hi Cnt Ov*/
2325 XMR_OK_OV = 1<<0, /* Bit 0: Frames Received Ok Ov */
2330 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
2331 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
2333 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2334 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2335 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2336 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2337 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2338 XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */
2339 XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */
2340 XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */
2341 XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/
2342 XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
2343 XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */
2344 XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */
2345 XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */
2346 XMT_ABO_COL_OV = 1<<12, /* Bit 12: Tx abo dueto Ex Col Ov*/
2347 XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */
2348 XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */
2349 XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/
2350 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2351 XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */
2352 XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */
2353 XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
2354 XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */
2355 XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */
2356 XMT_OK_LO_OV = 1<<2, /* Bit 2: Octets Tx OK Low CntOv*/
2357 XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/
2358 XMT_OK_OV = 1<<0, /* Bit 0: Frames Tx Ok Ov */
2427 FLOW_MODE_NONE = 1, /* No Flow-Control */
2478 return readl(hw->regs + reg); in skge_read32()
2483 return readw(hw->regs + reg); in skge_read16()
2488 return readb(hw->regs + reg); in skge_read8()
2493 writel(val, hw->regs + reg); in skge_write32()
2498 writew(val, hw->regs + reg); in skge_write16()
2503 writeb(val, hw->regs + reg); in skge_write8()
2509 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2553 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))