56 #define SKGE_EEPROM_MAGIC	0x9933aabb
69 module_param(debug, int, 0);
70 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
73 	{ PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) },	  /* 3Com 3C940 */
74 	{ PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) },	  /* 3Com 3C940B */
76 	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
78 	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
79 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },	  /* D-Link DGE-530T (rev.B) */
80 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) },	  /* D-Link DGE-530T */
81 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) },	  /* D-Link DGE-530T Rev C1 */
82 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },	  /* Marvell Yukon 88E8001/8003/8010 */
83 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) },	  /* Belkin */
84 	{ PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, 	  /* CNet PowerG-2000 */
85 	{ PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) },	  /* Linksys EG1064 v2 */
86 	{ PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
87 	{ 0 }
124 	return 0x4000;  in skge_get_regs_len()
139 	memset(p, 0, regs->len);  in skge_get_regs()
152 		return 0;  in wol_supported()
154 	if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)  in wol_supported()
155 		return 0;  in wol_supported()
199 	gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);  in skge_wol_init()
216 	ctrl = 0;  in skge_wol_init()
255 	return 0;  in skge_set_wol()
317 	return 0;  in skge_get_link_ksettings()
326 	int err = 0;  in skge_set_link_ksettings()
370 		if ((setting & supported) == 0)  in skge_set_link_ksettings()
389 	return 0;  in skge_set_link_ksettings()
469 	dev->stats.tx_bytes = data[0];  in skge_get_stats()
486 		for (i = 0; i < ARRAY_SIZE(skge_stats); i++)  in skge_get_strings()
513 	int err = 0;  in skge_set_ring_param()
515 	if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||  in skge_set_ring_param()
552 	return 0;  in skge_nway_reset()
573 	int err = 0;  in skge_set_pauseparam()
599 	return 0;  in skge_set_pauseparam()
629 	ecmd->rx_coalesce_usecs = 0;  in skge_get_coalesce()
630 	ecmd->tx_coalesce_usecs = 0;  in skge_get_coalesce()
642 	return 0;  in skge_get_coalesce()
657 	if (ecmd->rx_coalesce_usecs == 0)  in skge_set_coalesce()
667 	if (ecmd->tx_coalesce_usecs == 0)  in skge_set_coalesce()
678 	if (msk == 0)  in skge_set_coalesce()
684 	return 0;  in skge_set_coalesce()
700 				skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);  in skge_led()
704 			skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);  in skge_led()
734 			gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);  in skge_led()
752 				      PHY_M_LED_MO_100(MO_LED_ON) : 0));  in skge_led()
755 			gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);  in skge_led()
790 	return 0;  in skge_set_phys_id()
841 	while (length > 0) {  in skge_get_eeprom()
850 	return 0;  in skge_get_eeprom()
868 	while (length > 0) {  in skge_set_eeprom()
882 	return 0;  in skge_set_eeprom()
927 	for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {  in skge_ring_alloc()
939 	return 0;  in skge_ring_alloc()
960 	rd->csum1 = 0;  in skge_rx_setup()
961 	rd->csum2 = 0;  in skge_rx_setup()
968 	return 0;  in skge_rx_setup()
979 	rd->csum2 = 0;  in skge_rx_reuse()
998 		rd->control = 0;  in skge_rx_clean()
1030 		if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) {  in skge_rx_fill()
1037 	return 0;  in skge_rx_fill()
1102 	for (i = 0; i < PHY_RETRIES; i++) {  in __xm_phy_read()
1112 	return 0;  in __xm_phy_read()
1117 	u16 v = 0;  in xm_phy_read()
1128 	for (i = 0; i < PHY_RETRIES; i++) {  in xm_phy_write()
1137 	for (i = 0; i < PHY_RETRIES; i++) {  in xm_phy_write()
1139 			return 0;  in xm_phy_write()
1160 	skge_write8(hw, B3_MA_RCINI_RX1, 0);  in genesis_init()
1161 	skge_write8(hw, B3_MA_RCINI_RX2, 0);  in genesis_init()
1162 	skge_write8(hw, B3_MA_RCINI_TX1, 0);  in genesis_init()
1163 	skge_write8(hw, B3_MA_RCINI_TX2, 0);  in genesis_init()
1175 	static const u8 zero[8]  = { 0 };  in genesis_reset()
1178 	skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);  in genesis_reset()
1183 	xm_write32(hw, port, XM_MODE, 0);		/* clear Mode Reg */  in genesis_reset()
1184 	xm_write16(hw, port, XM_TX_CMD, 0);	/* reset TX CMD Reg */  in genesis_reset()
1185 	xm_write16(hw, port, XM_RX_CMD, 0);	/* reset RX CMD Reg */  in genesis_reset()
1189 		xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);  in genesis_reset()
1201 	[FLOW_MODE_NONE] =	0,
1227 	if ((status & PHY_ST_LSYNC) == 0) {  in bcom_check_link()
1259 		/* We are using IEEE 802.3z/D5.0 Table 37-4 */  in bcom_check_link()
1295 		{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },  in bcom_phy_init()
1296 		{ 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },  in bcom_phy_init()
1297 		{ 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },  in bcom_phy_init()
1298 		{ 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },  in bcom_phy_init()
1300 		{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },  in bcom_phy_init()
1301 		{ 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },  in bcom_phy_init()
1318 		for (i = 0; i < ARRAY_SIZE(C0hack); i++)  in bcom_phy_init()
1328 		for (i = 0; i < ARRAY_SIZE(A1hack); i++)  in bcom_phy_init()
1393 	u16 ctrl = 0;  in xm_phy_init()
1434 	if ((status & PHY_ST_LSYNC) == 0) {  in xm_check_link()
1436 		return 0;  in xm_check_link()
1443 			return 0;  in xm_check_link()
1448 			return 0;  in xm_check_link()
1463 			return 0;  in xm_check_link()
1466 		/* We are using IEEE 802.3z/D5.0 Table 37-4 */  in xm_check_link()
1514 	for (i = 0; i < 3; i++) {  in xm_link_timer()
1540 	static const u8 zero[6]  = { 0 };  in genesis_mac_init()
1542 	for (i = 0; i < 10; i++) {  in genesis_mac_init()
1564 		if (port == 0)  in genesis_mac_init()
1666 	skge_write8(hw, B3_MA_RCINI_RX1, 0);  in genesis_mac_init()
1667 	skge_write8(hw, B3_MA_RCINI_RX2, 0);  in genesis_mac_init()
1668 	skge_write8(hw, B3_MA_RCINI_TX1, 0);  in genesis_mac_init()
1669 	skge_write8(hw, B3_MA_RCINI_TX2, 0);  in genesis_mac_init()
1687 			     (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);  in genesis_mac_init()
1707 		     port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);  in genesis_stop()
1715 	} while (--retries > 0);  in genesis_stop()
1720 		if (port == 0) {  in genesis_stop()
1758 	data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32  in genesis_get_stats()
1774 		     "mac interrupt status 0x%x\n", status);  in genesis_mac_intr()
1822 		/* XM_MAC_PTIME = 0xffff (maximum) */  in genesis_link_up()
1824 		xm_write16(hw, port, XM_MAC_PTIME, 0xffff);  in genesis_link_up()
1879 		     "phy interrupt status 0x%x\n", isrc);  in bcom_phy_intr()
1908 	for (i = 0; i < PHY_RETRIES; i++) {  in gm_phy_write()
1912 			return 0;  in gm_phy_write()
1927 	for (i = 0; i < PHY_RETRIES; i++) {  in __gm_phy_read()
1936 	return 0;  in __gm_phy_read()
1941 	u16 v = 0;  in gm_phy_read()
1960 		ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);  in yukon_init()
1972 	ctrl = 0;  in yukon_init()
1973 	ct1000 = 0;  in yukon_init()
2037 	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */  in yukon_reset()
2038 	gma_write16(hw, port, GM_MC_ADDR_H1, 0);	/* clear MC hash */  in yukon_reset()
2039 	gma_write16(hw, port, GM_MC_ADDR_H2, 0);  in yukon_reset()
2040 	gma_write16(hw, port, GM_MC_ADDR_H3, 0);  in yukon_reset()
2041 	gma_write16(hw, port, GM_MC_ADDR_H4, 0);  in yukon_reset()
2055 		return 0;  in is_yukon_lite_a0()
2058 	skge_write8(hw, B2_FAR + 3, 0xff);  in is_yukon_lite_a0()
2059 	ret = (skge_read8(hw, B2_FAR + 3) != 0);  in is_yukon_lite_a0()
2150 	for (i = 0; i < GM_MIB_CNT_SIZE; i++)  in yukon_mac_init()
2162 	gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);  in yukon_mac_init()
2186 	gma_write16(hw, port, GM_TX_IRQ_MSK, 0);  in yukon_mac_init()
2187 	gma_write16(hw, port, GM_RX_IRQ_MSK, 0);  in yukon_mac_init()
2188 	gma_write16(hw, port, GM_TR_IRQ_MSK, 0);  in yukon_mac_init()
2238 	skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);  in yukon_stop()
2259 	data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32  in yukon_get_stats()
2276 		     "mac interrupt status 0x%x\n", status);  in yukon_mac_intr()
2356 		     "phy interrupt status 0x%x 0x%x\n", istatus, phystat);  in yukon_phy_intr()
2379 		/* We are using IEEE 802.3z/D5.0 Table 37-4 */  in yukon_phy_intr()
2460 		u16 val = 0;  in skge_ioctl()
2464 			err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);  in skge_ioctl()
2466 			err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);  in skge_ioctl()
2475 			err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,  in skge_ioctl()
2478 			err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,  in skge_ioctl()
2521 	u32 watermark = 0x600;  in skge_qset()
2525 	if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)  in skge_qset()
2628 	return 0;  in skge_up()
2659 		return 0;  in skge_down()
2673 	skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);  in skge_down()
2697 	skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);  in skge_down()
2698 	skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);  in skge_down()
2705 	skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);  in skge_down()
2730 	return 0;  in skge_down()
2736 	return ((ring->to_clean > ring->to_use) ? 0 : ring->count)  in skge_avail()
2779 		    hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)  in skge_xmit_frame()
2784 		td->csum_offs = 0;  in skge_xmit_frame()
2796 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {  in skge_xmit_frame()
2799 			map = skb_frag_dma_map(&hw->pdev->dev, frag, 0,  in skge_xmit_frame()
2845 	while (i-- > 0) {  in skge_xmit_frame()
2885 		td->control = 0;  in skge_tx_clean()
2909 		return 0;  in skge_change_mtu()
2923 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2930 	bit = ~crc & 0x3f;  in genesis_add_filter()
2951 		memset(filter, 0xff, sizeof(filter));  in genesis_set_multicast()
2953 		memset(filter, 0, sizeof(filter));  in genesis_set_multicast()
2969 	u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;  in yukon_add_filter()
2985 	memset(filter, 0, sizeof(filter));  in yukon_set_multicast()
2993 		memset(filter, 0xff, sizeof(filter));  in yukon_set_multicast()
3008 			 (u16)filter[0] | ((u16)filter[1] << 8));  in yukon_set_multicast()
3030 		return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;  in bad_phy_status()
3033 			(status & GMR_FS_RX_OK) == 0;  in bad_phy_status()
3060 		     "rx slot %td status 0x%x len %d\n",  in skge_rx_get()
3103 		if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) {  in skge_rx_get()
3126 		     "rx err, slot %td control 0x%x status 0x%x\n",  in skge_rx_get()
3156 	unsigned int bytes_compl = 0, pkts_compl = 0;  in skge_tx_done()
3204 	int work_done = 0;  in skge_poll()
3260 			    (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)  in skge_mac_parity()
3301 		skge_mac_parity(hw, 0);  in skge_error_irq()
3308 			hw->dev[0]->name);  in skge_error_irq()
3354 	for (port = 0; port < hw->ports; port++) {  in skge_extirq()
3380 	int handled = 0;  in skge_intr()
3385 	if (status == 0 || status == ~0)  in skge_intr()
3396 		struct skge_port *skge = netdev_priv(hw->dev[0]);  in skge_intr()
3405 		++hw->dev[0]->stats.rx_over_errors;  in skge_intr()
3411 		skge_mac_intr(hw, 0);  in skge_intr()
3490 	return 0;  in skge_set_mac_address()
3508 	for (i = 0; i < ARRAY_SIZE(skge_chips); i++)  in skge_board_name()
3512 	snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id);  in skge_board_name()
3536 	skge_write8(hw, B2_TST_CTRL2, 0);  in skge_reset()
3549 	hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;  in skge_reset()
3564 			dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",  in skge_reset()
3584 		dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",  in skge_reset()
3597 			/* special case: 4 x 64k x 36, offset = 0x80000 */  in skge_reset()
3598 			hw->ram_size = 0x100000;  in skge_reset()
3599 			hw->ram_offset = 0x80000;  in skge_reset()
3602 	} else if (t8 == 0)  in skge_reset()
3603 		hw->ram_size = 0x20000;  in skge_reset()
3635 		for (i = 0; i < hw->ports; i++) {  in skge_reset()
3647 	for (i = 0; i < hw->ports; i++)  in skge_reset()
3676 	skge_write32(hw, B0_IMSK, 0);  in skge_reset()
3678 	for (i = 0; i < hw->ports; i++) {  in skge_reset()
3685 	return 0;  in skge_reset()
3726 	return 0;  in skge_debug_show()
3861 		timer_setup(&skge->link_timer, xm_link_timer, 0);  in skge_devinit()
3888 	int err, using_dac = 0;  in skge_probe()
3908 		using_dac = 0;  in skge_probe()
3942 	hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000);  in skge_probe()
3952 	pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",  in skge_probe()
3954 		(unsigned long long)pci_resource_start(pdev, 0), pdev->irq,  in skge_probe()
3957 	dev = skge_devinit(hw, 0, using_dac);  in skge_probe()
4000 	return 0;  in skge_probe()
4035 	dev0 = hw->dev[0];  in skge_remove()
4041 	hw->intr_mask = 0;  in skge_remove()
4044 		skge_write32(hw, B0_IMSK, 0);  in skge_remove()
4071 		return 0;  in skge_suspend()
4073 	for (i = 0; i < hw->ports; i++) {  in skge_suspend()
4084 	skge_write32(hw, B0_IMSK, 0);  in skge_suspend()
4086 	return 0;  in skge_suspend()
4095 		return 0;  in skge_resume()
4101 	for (i = 0; i < hw->ports; i++) {  in skge_resume()
4134 	for (i = 0; i < hw->ports; i++) {  in skge_shutdown()