510 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);  in nix_setup_bpids()
595 		cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan));  in rvu_mbox_handler_nix_bp_disable()
728 		cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan));  in rvu_mbox_handler_nix_bp_enable()
806 	cfg = (rvu_read64(rvu, blkaddr, NIX_AF_CONST1) >> 48) & 0xFF;  in nix_setup_lso()
810 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_LSO_CFG);  in nix_setup_lso()
924 	reg = rvu_read64(rvu, block->addr, NIX_AF_AQ_STATUS);  in nix_aq_enqueue_wait()
1030 		cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RSS_CFG(nixlf));  in rvu_nix_blk_aq_enq_inst()
1036 		cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG);  in rvu_nix_blk_aq_enq_inst()
1505 	ctx_cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST3);  in rvu_mbox_handler_nix_lf_alloc()
1565 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);  in rvu_mbox_handler_nix_lf_alloc()
1579 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);  in rvu_mbox_handler_nix_lf_alloc()
1645 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQ_CONST);  in rvu_mbox_handler_nix_lf_alloc()
1654 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);  in rvu_mbox_handler_nix_lf_alloc()
1658 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST2);  in rvu_mbox_handler_nix_lf_alloc()
1800 	oldval = rvu_read64(rvu, blkaddr, reg);  in handle_txschq_shaper_update()
1828 			dbgval = rvu_read64(rvu, blkaddr, md_debug0);  in handle_txschq_shaper_update()
1919 	cfg = rvu_read64(rvu, blkaddr, cir_reg);  in nix_reset_tx_shaping()
1924 	cfg = rvu_read64(rvu, blkaddr, pir_reg);  in nix_reset_tx_shaping()
1942 	link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ?  in nix_reset_tx_linkcfg()
2238 	rsp->link_cfg_lvl = rvu_read64(rvu, blkaddr,  in rvu_mbox_handler_nix_txsch_alloc()
2286 		smq_tree_ctx->cir_val = rvu_read64(rvu, blkaddr, smq_tree_ctx->cir_off);  in nix_smq_flush_fill_ctx()
2288 			smq_tree_ctx->pir_val = rvu_read64(rvu, blkaddr, smq_tree_ctx->pir_off);  in nix_smq_flush_fill_ctx()
2292 			regval = rvu_read64(rvu, blkaddr, parent_off);  in nix_smq_flush_fill_ctx()
2373 		cfg = rvu_read64(rvu, blkaddr, NIX_AF_MDQX_IN_MD_COUNT(smq));  in nix_smq_flush()
2398 	link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ?  in nix_smq_flush()
2404 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq));  in nix_smq_flush()
2410 		cfg = rvu_read64(rvu, blkaddr,  in nix_smq_flush()
2421 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_SMQX_CFG(smq));  in nix_smq_flush()
2437 		cfg = rvu_read64(rvu, blkaddr,  in nix_smq_flush()
2747 		rsp->regval[idx] = rvu_read64(rvu, blkaddr, reg);  in nix_txschq_cfg_read()
2839 		val = rvu_read64(rvu, blkaddr, reg);  in rvu_mbox_handler_nix_txschq_cfg()
3531 		cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));  in nix_setup_mce_tables()
3598 	size = (rvu_read64(rvu, blkaddr, NIX_AF_CONST3) >> 16) & 0x0F;  in nix_setup_mcast()
3632 	size = rvu_read64(rvu, blkaddr, NIX_AF_MC_MIRROR_CONST) & 0xFFFF;  in nix_setup_mcast()
3712 		cfg = rvu_read64(rvu, blkaddr, reg);  in nix_setup_txschq()
3781 	total = (rvu_read64(rvu, blkaddr, NIX_AF_PSE_CONST) & 0xFF00) >> 8;  in nix_af_mark_format_setup()
3847 	dwrr_mtu = rvu_read64(rvu, blkaddr,  in rvu_mbox_handler_nix_get_hw_info()
3851 	dwrr_mtu = rvu_read64(rvu, blkaddr,  in rvu_mbox_handler_nix_get_hw_info()
3855 	dwrr_mtu = rvu_read64(rvu, blkaddr,  in rvu_mbox_handler_nix_get_hw_info()
3874 	stats = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);  in rvu_mbox_handler_nix_stats_rst()
4594 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_LINKX_CFG(link));  in rvu_mbox_handler_nix_set_hw_frs()
4613 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_CFG(nixlf));  in rvu_mbox_handler_nix_set_rx_cfg()
4737 		    rvu_read64(rvu, blkaddr, NIX_AF_CFG) | BIT_ULL(9));  in nix_calibrate_x2p()
4746 	status = rvu_read64(rvu, blkaddr, NIX_AF_STATUS);  in nix_calibrate_x2p()
4767 		    rvu_read64(rvu, blkaddr, NIX_AF_CFG) & ~BIT_ULL(9));  in nix_calibrate_x2p()
4782 	cfg = rvu_read64(rvu, block->addr, NIX_AF_CFG);  in nix_aq_init()
4792 	cfg = rvu_read64(rvu, block->addr, NIX_AF_NDC_CFG);  in nix_aq_init()
4821 	hw_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);  in rvu_nix_setup_capabilities()
4858 			    rvu_read64(rvu, blkaddr, NIX_AF_CFG) | 0x40ULL);  in rvu_nix_block_init()
4868 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS);  in rvu_nix_block_init()
4889 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_SEB_CFG);  in rvu_nix_block_init()
5291 	sa_base = rvu_read64(rvu, blkaddr, NIX_AF_LFX_RX_IPSEC_SA_BASE(nixlf));  in rvu_nix_lf_teardown()
5323 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_LFX_TX_CFG(nixlf));  in rvu_nix_lf_ptp_tx_cfg()
5369 			reg = rvu_read64(rvu, blkaddr,  in rvu_mbox_handler_nix_lso_format_cfg()
5447 		val = rvu_read64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx));  in nix_inline_ipsec_cfg()
5460 		val = rvu_read64(rvu, blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx));  in nix_inline_ipsec_cfg()
5491 	val = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_RX_IPSEC_GEN_CFG);  in rvu_mbox_handler_nix_read_inline_ipsec_cfg()
5497 	val = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_RX_CPTX_CREDIT(0));  in rvu_mbox_handler_nix_read_inline_ipsec_cfg()
5630 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST);  in nix_setup_ipolicers()
5642 	cfg = rvu_read64(rvu, blkaddr, NIX_AF_PL_CONST);  in nix_setup_ipolicers()
6174 	tu = rvu_read64(rvu, blkaddr, NIX_AF_PL_TS) & GENMASK_ULL(9, 0);  in rvu_mbox_handler_nix_bandprof_get_hwinfo()