Lines Matching +full:sci +full:- +full:intr

1 // SPDX-License-Identifier: GPL-2.0
27 struct hwinfo *hw = mcs->hw; in cnf10kb_mcs_set_hw_capabilities()
29 hw->tcam_entries = 64; /* TCAM entries */ in cnf10kb_mcs_set_hw_capabilities()
30 hw->secy_entries = 64; /* SecY entries */ in cnf10kb_mcs_set_hw_capabilities()
31 hw->sc_entries = 64; /* SC CAM entries */ in cnf10kb_mcs_set_hw_capabilities()
32 hw->sa_entries = 128; /* SA entries */ in cnf10kb_mcs_set_hw_capabilities()
33 hw->lmac_cnt = 4; /* lmacs/ports per mcs block */ in cnf10kb_mcs_set_hw_capabilities()
34 hw->mcs_x2p_intf = 1; /* x2p clabration intf */ in cnf10kb_mcs_set_hw_capabilities()
35 hw->mcs_blks = 7; /* MCS blocks */ in cnf10kb_mcs_set_hw_capabilities()
36 hw->ip_vec = MCS_CNF10KB_INT_VEC_IP; /* IP vector */ in cnf10kb_mcs_set_hw_capabilities()
77 val = (map->secy & 0x3F) | (map->ctrl_pkt & 0x1) << 6; in cnf10kb_mcs_flowid_secy_map()
79 reg = MCSX_CPM_RX_SLAVE_SECY_MAP_MEMX(map->flow_id); in cnf10kb_mcs_flowid_secy_map()
81 reg = MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_0X(map->flow_id); in cnf10kb_mcs_flowid_secy_map()
82 mcs_reg_write(mcs, reg, map->sci); in cnf10kb_mcs_flowid_secy_map()
83 val |= (map->sc & 0x3F) << 7; in cnf10kb_mcs_flowid_secy_map()
84 reg = MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_1X(map->flow_id); in cnf10kb_mcs_flowid_secy_map()
94 val = (map->sa_index0 & 0x7F) | (map->sa_index1 & 0x7F) << 7; in cnf10kb_mcs_tx_sa_mem_map_write()
96 reg = MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(map->sc_id); in cnf10kb_mcs_tx_sa_mem_map_write()
102 if (map->rekey_ena) in cnf10kb_mcs_tx_sa_mem_map_write()
103 val |= BIT_ULL(map->sc_id); in cnf10kb_mcs_tx_sa_mem_map_write()
105 val &= ~BIT_ULL(map->sc_id); in cnf10kb_mcs_tx_sa_mem_map_write()
109 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_SA_INDEX0_VLDX(map->sc_id), map->sa_index0_vld); in cnf10kb_mcs_tx_sa_mem_map_write()
110 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_SA_INDEX1_VLDX(map->sc_id), map->sa_index1_vld); in cnf10kb_mcs_tx_sa_mem_map_write()
112 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(map->sc_id), map->tx_sa_active); in cnf10kb_mcs_tx_sa_mem_map_write()
119 val = (map->sa_index & 0x7F) | (map->sa_in_use << 7); in cnf10kb_mcs_rx_sa_mem_map_write()
121 reg = MCSX_CPM_RX_SLAVE_SA_MAP_MEMX((4 * map->sc_id) + map->an); in cnf10kb_mcs_rx_sa_mem_map_write()
139 dev_err(mcs->dev, "MCS set force clk enable failed\n"); in mcs_set_force_clk_en()
164 sc_bmap = &mcs->tx.sc; in cnf10kb_mcs_tx_pn_thresh_reached_handler()
166 event.mcs_id = mcs->mcs_id; in cnf10kb_mcs_tx_pn_thresh_reached_handler()
171 for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) { in cnf10kb_mcs_tx_pn_thresh_reached_handler()
177 if (sa_status == mcs->tx_sa_active[sc]) in cnf10kb_mcs_tx_pn_thresh_reached_handler()
187 event.pcifunc = mcs->tx.sa2pf_map[event.sa_id]; in cnf10kb_mcs_tx_pn_thresh_reached_handler()
199 sc_bmap = &mcs->tx.sc; in cnf10kb_mcs_tx_pn_wrapped_handler()
201 event.mcs_id = mcs->mcs_id; in cnf10kb_mcs_tx_pn_wrapped_handler()
204 for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) { in cnf10kb_mcs_tx_pn_wrapped_handler()
207 if (mcs->tx_sa_active[sc]) in cnf10kb_mcs_tx_pn_wrapped_handler()
214 event.pcifunc = mcs->tx.sa2pf_map[event.sa_id]; in cnf10kb_mcs_tx_pn_wrapped_handler()
219 void cnf10kb_mcs_bbe_intr_handler(struct mcs *mcs, u64 intr, in cnf10kb_mcs_bbe_intr_handler() argument
225 if (!(intr & MCS_BBE_INT_MASK)) in cnf10kb_mcs_bbe_intr_handler()
228 event.mcs_id = mcs->mcs_id; in cnf10kb_mcs_bbe_intr_handler()
229 event.pcifunc = mcs->pf_map[0]; in cnf10kb_mcs_bbe_intr_handler()
232 if (!(intr & BIT_ULL(i))) in cnf10kb_mcs_bbe_intr_handler()
238 if (intr & 0xFULL) in cnf10kb_mcs_bbe_intr_handler()
253 void cnf10kb_mcs_pab_intr_handler(struct mcs *mcs, u64 intr, in cnf10kb_mcs_pab_intr_handler() argument
259 if (!(intr & MCS_PAB_INT_MASK)) in cnf10kb_mcs_pab_intr_handler()
262 event.mcs_id = mcs->mcs_id; in cnf10kb_mcs_pab_intr_handler()
263 event.pcifunc = mcs->pf_map[0]; in cnf10kb_mcs_pab_intr_handler()
266 if (!(intr & BIT_ULL(i))) in cnf10kb_mcs_pab_intr_handler()