Lines Matching refs:mcs_reg_write
266 mcs_reg_write(mcs, reg, BIT_ULL(0)); in mcs_clear_stats()
289 mcs_reg_write(mcs, reg, 0x0); in mcs_clear_stats()
340 mcs_reg_write(mcs, reg, next_pn); in mcs_pn_table_write()
355 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_tx_sa_mem_map_write()
359 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_tx_sa_mem_map_write()
369 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_rx_sa_mem_map_write()
380 mcs_reg_write(mcs, reg, plcy[reg_id]); in mcs_sa_plcy_write()
385 mcs_reg_write(mcs, reg, plcy[reg_id]); in mcs_sa_plcy_write()
403 mcs_reg_write(mcs, reg, val); in mcs_ena_dis_sc_cam_entry()
408 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SC_CAMX(0, sc_id), sci); in mcs_rx_sc_cam_write()
409 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SC_CAMX(1, sc_id), secy); in mcs_rx_sc_cam_write()
423 mcs_reg_write(mcs, reg, plcy); in mcs_secy_plcy_write()
426 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SECY_PLCY_MEM_1X(secy_id), 0x0ull); in mcs_secy_plcy_write()
441 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_flowid_secy_map()
464 mcs_reg_write(mcs, reg, val); in mcs_ena_dis_flowid_entry()
475 mcs_reg_write(mcs, reg, data[reg_id]); in mcs_flowid_entry_write()
479 mcs_reg_write(mcs, reg, mask[reg_id]); in mcs_flowid_entry_write()
484 mcs_reg_write(mcs, reg, data[reg_id]); in mcs_flowid_entry_write()
488 mcs_reg_write(mcs, reg, mask[reg_id]); in mcs_flowid_entry_write()
506 mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0)); in mcs_install_flowid_bypass_entry()
510 mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0)); in mcs_install_flowid_bypass_entry()
599 mcs_reg_write(mcs, reg, dis); in mcs_free_ctrlpktrule()
607 mcs_reg_write(mcs, reg, dis); in mcs_free_ctrlpktrule()
627 mcs_reg_write(mcs, reg, req->data0); in mcs_ctrlpktrule_write()
637 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
646 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
648 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
651 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
653 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
665 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
667 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
669 mcs_reg_write(mcs, reg, req->data2); in mcs_ctrlpktrule_write()
672 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
674 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
676 mcs_reg_write(mcs, reg, req->data2); in mcs_ctrlpktrule_write()
687 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
695 mcs_reg_write(mcs, reg, enb); in mcs_ctrlpktrule_write()
984 mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1C, BIT_ULL(0)); in mcs_ip_intr_handler()
1001 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_RX_INT, cpm_intr); in mcs_ip_intr_handler()
1025 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_INT, cpm_intr); in mcs_ip_intr_handler()
1034 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1035 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT, bbe_intr); in mcs_ip_intr_handler()
1044 mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1045 mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT, bbe_intr); in mcs_ip_intr_handler()
1054 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1055 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT, pab_intr); in mcs_ip_intr_handler()
1064 mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1065 mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT, pab_intr); in mcs_ip_intr_handler()
1069 mcs_reg_write(mcs, MCSX_IP_INT, BIT_ULL(0)); in mcs_ip_intr_handler()
1070 mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1S, BIT_ULL(0)); in mcs_ip_intr_handler()
1159 mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1S, BIT_ULL(0)); in mcs_register_interrupts()
1162 mcs_reg_write(mcs, MCSX_TOP_SLAVE_INT_SUM_ENB, in mcs_register_interrupts()
1167 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_INT_ENB, 0x7ULL); in mcs_register_interrupts()
1168 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_RX_INT_ENB, 0x7FULL); in mcs_register_interrupts()
1170 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT_ENB, 0xFFULL); in mcs_register_interrupts()
1171 mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT_ENB, 0xFFULL); in mcs_register_interrupts()
1173 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT_ENB, 0xFFFFFULL); in mcs_register_interrupts()
1174 mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT_ENB, 0xFFFFFULL); in mcs_register_interrupts()
1237 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PORT_CFGX(req->port_id), in mcs_set_port_cfg()
1246 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(req->port_id), val); in mcs_set_port_cfg()
1247 mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(req->port_id), in mcs_set_port_cfg()
1256 mcs_reg_write(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION, val); in mcs_set_port_cfg()
1260 mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id), val); in mcs_set_port_cfg()
1324 mcs_reg_write(mcs, reg, reset & 0x1); in mcs_reset_port()
1334 mcs_reg_write(mcs, reg, (u64)mode); in mcs_set_lmac_mode()
1336 mcs_reg_write(mcs, reg, (u64)mode); in mcs_set_lmac_mode()
1348 mcs_reg_write(mcs, reg, pn->threshold); in mcs_pn_threshold_set()
1359 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1363 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1369 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1373 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1382 mcs_reg_write(mcs, reg, 0); in mcs_lmac_init()
1386 mcs_reg_write(mcs, reg, 0xe000e); in mcs_lmac_init()
1391 mcs_reg_write(mcs, reg, 0); in mcs_lmac_init()
1408 mcs_reg_write(mcs, MCSX_LINK_LMACX_CFG(lmac), cfg); in mcs_set_lmac_channels()
1423 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val); in mcs_x2p_calibration()
1445 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, mcs_reg_read(mcs, MCSX_MIL_GLOBAL) & ~BIT_ULL(5)); in mcs_x2p_calibration()
1460 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val); in mcs_set_external_bypass()
1470 mcs_reg_write(mcs, MCSX_CSE_RX_SLAVE_STATS_CLEAR, 0x1F); in mcs_global_cfg()
1471 mcs_reg_write(mcs, MCSX_CSE_TX_SLAVE_STATS_CLEAR, 0x1F); in mcs_global_cfg()
1475 mcs_reg_write(mcs, MCSX_IP_MODE, BIT_ULL(3)); in mcs_global_cfg()
1479 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_CAL_ENTRY, 0xe4); in mcs_global_cfg()
1480 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_CAL_LEN, 4); in mcs_global_cfg()