Lines Matching full:reg
29 u64 reg; in mcs_get_tx_secy_stats() local
31 reg = MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLBCPKTSX(id); in mcs_get_tx_secy_stats()
32 stats->ctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
34 reg = MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLMCPKTSX(id); in mcs_get_tx_secy_stats()
35 stats->ctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
37 reg = MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLOCTETSX(id); in mcs_get_tx_secy_stats()
38 stats->ctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
40 reg = MCSX_CSE_TX_MEM_SLAVE_IFOUTCTLUCPKTSX(id); in mcs_get_tx_secy_stats()
41 stats->ctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
43 reg = MCSX_CSE_TX_MEM_SLAVE_IFOUTUNCTLBCPKTSX(id); in mcs_get_tx_secy_stats()
44 stats->unctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
46 reg = MCSX_CSE_TX_MEM_SLAVE_IFOUTUNCTLMCPKTSX(id); in mcs_get_tx_secy_stats()
47 stats->unctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
49 reg = MCSX_CSE_TX_MEM_SLAVE_IFOUTUNCTLOCTETSX(id); in mcs_get_tx_secy_stats()
50 stats->unctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
52 reg = MCSX_CSE_TX_MEM_SLAVE_IFOUTUNCTLUCPKTSX(id); in mcs_get_tx_secy_stats()
53 stats->unctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
55 reg = MCSX_CSE_TX_MEM_SLAVE_OUTOCTETSSECYENCRYPTEDX(id); in mcs_get_tx_secy_stats()
56 stats->octet_encrypted_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
58 reg = MCSX_CSE_TX_MEM_SLAVE_OUTOCTETSSECYPROTECTEDX(id); in mcs_get_tx_secy_stats()
59 stats->octet_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
61 reg = MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSECYNOACTIVESAX(id); in mcs_get_tx_secy_stats()
62 stats->pkt_noactivesa_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
64 reg = MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSECYTOOLONGX(id); in mcs_get_tx_secy_stats()
65 stats->pkt_toolong_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
67 reg = MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSECYUNTAGGEDX(id); in mcs_get_tx_secy_stats()
68 stats->pkt_untagged_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
73 u64 reg; in mcs_get_rx_secy_stats() local
75 reg = MCSX_CSE_RX_MEM_SLAVE_IFINCTLBCPKTSX(id); in mcs_get_rx_secy_stats()
76 stats->ctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
78 reg = MCSX_CSE_RX_MEM_SLAVE_IFINCTLMCPKTSX(id); in mcs_get_rx_secy_stats()
79 stats->ctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
81 reg = MCSX_CSE_RX_MEM_SLAVE_IFINCTLOCTETSX(id); in mcs_get_rx_secy_stats()
82 stats->ctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
84 reg = MCSX_CSE_RX_MEM_SLAVE_IFINCTLUCPKTSX(id); in mcs_get_rx_secy_stats()
85 stats->ctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
87 reg = MCSX_CSE_RX_MEM_SLAVE_IFINUNCTLBCPKTSX(id); in mcs_get_rx_secy_stats()
88 stats->unctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
90 reg = MCSX_CSE_RX_MEM_SLAVE_IFINUNCTLMCPKTSX(id); in mcs_get_rx_secy_stats()
91 stats->unctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
93 reg = MCSX_CSE_RX_MEM_SLAVE_IFINUNCTLOCTETSX(id); in mcs_get_rx_secy_stats()
94 stats->unctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
96 reg = MCSX_CSE_RX_MEM_SLAVE_IFINUNCTLUCPKTSX(id); in mcs_get_rx_secy_stats()
97 stats->unctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
99 reg = MCSX_CSE_RX_MEM_SLAVE_INOCTETSSECYDECRYPTEDX(id); in mcs_get_rx_secy_stats()
100 stats->octet_decrypted_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
102 reg = MCSX_CSE_RX_MEM_SLAVE_INOCTETSSECYVALIDATEX(id); in mcs_get_rx_secy_stats()
103 stats->octet_validated_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
105 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSCTRLPORTDISABLEDX(id); in mcs_get_rx_secy_stats()
106 stats->pkt_port_disabled_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
108 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYBADTAGX(id); in mcs_get_rx_secy_stats()
109 stats->pkt_badtag_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
111 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYNOSAX(id); in mcs_get_rx_secy_stats()
112 stats->pkt_nosa_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
114 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYNOSAERRORX(id); in mcs_get_rx_secy_stats()
115 stats->pkt_nosaerror_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
117 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYTAGGEDCTLX(id); in mcs_get_rx_secy_stats()
118 stats->pkt_tagged_ctl_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
120 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYUNTAGGEDX(id); in mcs_get_rx_secy_stats()
121 stats->pkt_untaged_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
123 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYCTLX(id); in mcs_get_rx_secy_stats()
124 stats->pkt_ctl_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
127 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSECYNOTAGX(id); in mcs_get_rx_secy_stats()
128 stats->pkt_notag_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
135 u64 reg; in mcs_get_flowid_stats() local
138 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSFLOWIDTCAMHITX(id); in mcs_get_flowid_stats()
140 reg = MCSX_CSE_TX_MEM_SLAVE_OUTPKTSFLOWIDTCAMHITX(id); in mcs_get_flowid_stats()
142 stats->tcam_hit_cnt = mcs_reg_read(mcs, reg); in mcs_get_flowid_stats()
148 u64 reg; in mcs_get_port_stats() local
151 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSFLOWIDTCAMMISSX(id); in mcs_get_port_stats()
152 stats->tcam_miss_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
154 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSPARSEERRX(id); in mcs_get_port_stats()
155 stats->parser_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
157 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSEARLYPREEMPTERRX(id); in mcs_get_port_stats()
158 stats->preempt_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
161 reg = MCSX_CSE_TX_MEM_SLAVE_OUTPKTSFLOWIDTCAMMISSX(id); in mcs_get_port_stats()
162 stats->tcam_miss_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
164 reg = MCSX_CSE_TX_MEM_SLAVE_OUTPKTSPARSEERRX(id); in mcs_get_port_stats()
165 stats->parser_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
167 reg = MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSECTAGINSERTIONERRX(id); in mcs_get_port_stats()
168 stats->sectag_insert_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
174 u64 reg; in mcs_get_sa_stats() local
177 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSAINVALIDX(id); in mcs_get_sa_stats()
178 stats->pkt_invalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
180 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTUSINGSAERRORX(id); in mcs_get_sa_stats()
181 stats->pkt_nosaerror_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
183 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSANOTVALIDX(id); in mcs_get_sa_stats()
184 stats->pkt_notvalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
186 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSAOKX(id); in mcs_get_sa_stats()
187 stats->pkt_ok_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
189 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSAUNUSEDSAX(id); in mcs_get_sa_stats()
190 stats->pkt_nosa_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
192 reg = MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSAENCRYPTEDX(id); in mcs_get_sa_stats()
193 stats->pkt_encrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
195 reg = MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSAPROTECTEDX(id); in mcs_get_sa_stats()
196 stats->pkt_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
203 u64 reg; in mcs_get_sc_stats() local
206 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCCAMHITX(id); in mcs_get_sc_stats()
207 stats->hit_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
209 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCINVALIDX(id); in mcs_get_sc_stats()
210 stats->pkt_invalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
212 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCLATEORDELAYEDX(id); in mcs_get_sc_stats()
213 stats->pkt_late_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
215 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCNOTVALIDX(id); in mcs_get_sc_stats()
216 stats->pkt_notvalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
218 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCUNCHECKEDX(id); in mcs_get_sc_stats()
219 stats->pkt_unchecked_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
222 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCDELAYEDX(id); in mcs_get_sc_stats()
223 stats->pkt_delay_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
225 reg = MCSX_CSE_RX_MEM_SLAVE_INPKTSSCOKX(id); in mcs_get_sc_stats()
226 stats->pkt_ok_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
229 reg = MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCDECRYPTEDX(id); in mcs_get_sc_stats()
230 stats->octet_decrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
232 reg = MCSX_CSE_RX_MEM_SLAVE_INOCTETSSCVALIDATEX(id); in mcs_get_sc_stats()
233 stats->octet_validate_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
236 reg = MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSCENCRYPTEDX(id); in mcs_get_sc_stats()
237 stats->pkt_encrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
239 reg = MCSX_CSE_TX_MEM_SLAVE_OUTPKTSSCPROTECTEDX(id); in mcs_get_sc_stats()
240 stats->pkt_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
243 reg = MCSX_CSE_TX_MEM_SLAVE_OUTOCTETSSCENCRYPTEDX(id); in mcs_get_sc_stats()
244 stats->octet_encrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
246 reg = MCSX_CSE_TX_MEM_SLAVE_OUTOCTETSSCPROTECTEDX(id); in mcs_get_sc_stats()
247 stats->octet_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
259 u64 reg; in mcs_clear_stats() local
262 reg = MCSX_CSE_RX_SLAVE_CTRL; in mcs_clear_stats()
264 reg = MCSX_CSE_TX_SLAVE_CTRL; in mcs_clear_stats()
266 mcs_reg_write(mcs, reg, BIT_ULL(0)); in mcs_clear_stats()
289 mcs_reg_write(mcs, reg, 0x0); in mcs_clear_stats()
334 u64 reg; in mcs_pn_table_write() local
337 reg = MCSX_CPM_RX_SLAVE_SA_PN_TABLE_MEMX(pn_id); in mcs_pn_table_write()
339 reg = MCSX_CPM_TX_SLAVE_SA_PN_TABLE_MEMX(pn_id); in mcs_pn_table_write()
340 mcs_reg_write(mcs, reg, next_pn); in mcs_pn_table_write()
345 u64 reg, val; in cn10kb_mcs_tx_sa_mem_map_write() local
354 reg = MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(map->sc_id); in cn10kb_mcs_tx_sa_mem_map_write()
355 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_tx_sa_mem_map_write()
358 reg = MCSX_CPM_TX_SLAVE_SA_MAP_MEM_1X(map->sc_id); in cn10kb_mcs_tx_sa_mem_map_write()
359 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_tx_sa_mem_map_write()
364 u64 val, reg; in cn10kb_mcs_rx_sa_mem_map_write() local
368 reg = MCSX_CPM_RX_SLAVE_SA_MAP_MEMX((4 * map->sc_id) + map->an); in cn10kb_mcs_rx_sa_mem_map_write()
369 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_rx_sa_mem_map_write()
375 u64 reg; in mcs_sa_plcy_write() local
379 reg = MCSX_CPM_RX_SLAVE_SA_PLCY_MEMX(reg_id, sa_id); in mcs_sa_plcy_write()
380 mcs_reg_write(mcs, reg, plcy[reg_id]); in mcs_sa_plcy_write()
384 reg = MCSX_CPM_TX_SLAVE_SA_PLCY_MEMX(reg_id, sa_id); in mcs_sa_plcy_write()
385 mcs_reg_write(mcs, reg, plcy[reg_id]); in mcs_sa_plcy_write()
392 u64 reg, val; in mcs_ena_dis_sc_cam_entry() local
394 reg = MCSX_CPM_RX_SLAVE_SC_CAM_ENA(0); in mcs_ena_dis_sc_cam_entry()
396 reg = MCSX_CPM_RX_SLAVE_SC_CAM_ENA(1); in mcs_ena_dis_sc_cam_entry()
399 val = mcs_reg_read(mcs, reg) | BIT_ULL(sc_id); in mcs_ena_dis_sc_cam_entry()
401 val = mcs_reg_read(mcs, reg) & ~BIT_ULL(sc_id); in mcs_ena_dis_sc_cam_entry()
403 mcs_reg_write(mcs, reg, val); in mcs_ena_dis_sc_cam_entry()
416 u64 reg; in mcs_secy_plcy_write() local
419 reg = MCSX_CPM_RX_SLAVE_SECY_PLCY_MEM_0X(secy_id); in mcs_secy_plcy_write()
421 reg = MCSX_CPM_TX_SLAVE_SECY_PLCY_MEMX(secy_id); in mcs_secy_plcy_write()
423 mcs_reg_write(mcs, reg, plcy); in mcs_secy_plcy_write()
431 u64 reg, val; in cn10kb_mcs_flowid_secy_map() local
435 reg = MCSX_CPM_RX_SLAVE_SECY_MAP_MEMX(map->flow_id); in cn10kb_mcs_flowid_secy_map()
438 reg = MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_0X(map->flow_id); in cn10kb_mcs_flowid_secy_map()
441 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_flowid_secy_map()
446 u64 reg, val; in mcs_ena_dis_flowid_entry() local
449 reg = MCSX_CPM_RX_SLAVE_FLOWID_TCAM_ENA_0; in mcs_ena_dis_flowid_entry()
451 reg = MCSX_CPM_RX_SLAVE_FLOWID_TCAM_ENA_1; in mcs_ena_dis_flowid_entry()
453 reg = MCSX_CPM_TX_SLAVE_FLOWID_TCAM_ENA_0; in mcs_ena_dis_flowid_entry()
455 reg = MCSX_CPM_TX_SLAVE_FLOWID_TCAM_ENA_1; in mcs_ena_dis_flowid_entry()
460 val = mcs_reg_read(mcs, reg) | BIT_ULL(flow_id); in mcs_ena_dis_flowid_entry()
462 val = mcs_reg_read(mcs, reg) & ~BIT_ULL(flow_id); in mcs_ena_dis_flowid_entry()
464 mcs_reg_write(mcs, reg, val); in mcs_ena_dis_flowid_entry()
470 u64 reg; in mcs_flowid_entry_write() local
474 reg = MCSX_CPM_RX_SLAVE_FLOWID_TCAM_DATAX(reg_id, flow_id); in mcs_flowid_entry_write()
475 mcs_reg_write(mcs, reg, data[reg_id]); in mcs_flowid_entry_write()
478 reg = MCSX_CPM_RX_SLAVE_FLOWID_TCAM_MASKX(reg_id, flow_id); in mcs_flowid_entry_write()
479 mcs_reg_write(mcs, reg, mask[reg_id]); in mcs_flowid_entry_write()
483 reg = MCSX_CPM_TX_SLAVE_FLOWID_TCAM_DATAX(reg_id, flow_id); in mcs_flowid_entry_write()
484 mcs_reg_write(mcs, reg, data[reg_id]); in mcs_flowid_entry_write()
487 reg = MCSX_CPM_TX_SLAVE_FLOWID_TCAM_MASKX(reg_id, flow_id); in mcs_flowid_entry_write()
488 mcs_reg_write(mcs, reg, mask[reg_id]); in mcs_flowid_entry_write()
497 u64 reg, plcy = 0; in mcs_install_flowid_bypass_entry() local
505 reg = MCSX_CPM_RX_SLAVE_FLOWID_TCAM_MASKX(reg_id, flow_id); in mcs_install_flowid_bypass_entry()
506 mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0)); in mcs_install_flowid_bypass_entry()
509 reg = MCSX_CPM_TX_SLAVE_FLOWID_TCAM_MASKX(reg_id, flow_id); in mcs_install_flowid_bypass_entry()
510 mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0)); in mcs_install_flowid_bypass_entry()
586 u64 dis, reg; in mcs_free_ctrlpktrule() local
589 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_RULE_ENABLE : MCSX_PEX_TX_SLAVE_RULE_ENABLE; in mcs_free_ctrlpktrule()
597 dis = mcs_reg_read(mcs, reg); in mcs_free_ctrlpktrule()
599 mcs_reg_write(mcs, reg, dis); in mcs_free_ctrlpktrule()
605 dis = mcs_reg_read(mcs, reg); in mcs_free_ctrlpktrule()
607 mcs_reg_write(mcs, reg, dis); in mcs_free_ctrlpktrule()
614 u64 reg, enb; in mcs_ctrlpktrule_write() local
624 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_RULE_ETYPE_CFGX(idx) : in mcs_ctrlpktrule_write()
627 mcs_reg_write(mcs, reg, req->data0); in mcs_ctrlpktrule_write()
634 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_RULE_DAX(idx) : in mcs_ctrlpktrule_write()
637 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
645 reg = MCSX_PEX_RX_SLAVE_RULE_DA_RANGE_MINX(idx); in mcs_ctrlpktrule_write()
646 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
647 reg = MCSX_PEX_RX_SLAVE_RULE_DA_RANGE_MAXX(idx); in mcs_ctrlpktrule_write()
648 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
650 reg = MCSX_PEX_TX_SLAVE_RULE_DA_RANGE_MINX(idx); in mcs_ctrlpktrule_write()
651 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
652 reg = MCSX_PEX_TX_SLAVE_RULE_DA_RANGE_MAXX(idx); in mcs_ctrlpktrule_write()
653 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
664 reg = MCSX_PEX_RX_SLAVE_RULE_COMBO_MINX(idx); in mcs_ctrlpktrule_write()
665 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
666 reg = MCSX_PEX_RX_SLAVE_RULE_COMBO_MAXX(idx); in mcs_ctrlpktrule_write()
667 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
668 reg = MCSX_PEX_RX_SLAVE_RULE_COMBO_ETX(idx); in mcs_ctrlpktrule_write()
669 mcs_reg_write(mcs, reg, req->data2); in mcs_ctrlpktrule_write()
671 reg = MCSX_PEX_TX_SLAVE_RULE_COMBO_MINX(idx); in mcs_ctrlpktrule_write()
672 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
673 reg = MCSX_PEX_TX_SLAVE_RULE_COMBO_MAXX(idx); in mcs_ctrlpktrule_write()
674 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
675 reg = MCSX_PEX_TX_SLAVE_RULE_COMBO_ETX(idx); in mcs_ctrlpktrule_write()
676 mcs_reg_write(mcs, reg, req->data2); in mcs_ctrlpktrule_write()
684 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_RULE_MAC : in mcs_ctrlpktrule_write()
687 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
691 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_RULE_ENABLE : MCSX_PEX_TX_SLAVE_RULE_ENABLE; in mcs_ctrlpktrule_write()
693 enb = mcs_reg_read(mcs, reg); in mcs_ctrlpktrule_write()
695 mcs_reg_write(mcs, reg, enb); in mcs_ctrlpktrule_write()
879 int sa, reg; in mcs_rx_pn_thresh_reached_handler() local
883 for (reg = 0; reg < (mcs->hw->sa_entries / 64); reg++) { in mcs_rx_pn_thresh_reached_handler()
887 intr = mcs_reg_read(mcs, MCSX_CPM_RX_SLAVE_PN_THRESH_REACHEDX(reg)); in mcs_rx_pn_thresh_reached_handler()
894 event.sa_id = sa + (reg * 64); in mcs_rx_pn_thresh_reached_handler()
942 u64 val, reg; in cn10kb_mcs_bbe_intr_handler() local
949 reg = (dir == MCS_RX) ? MCSX_BBE_RX_SLAVE_DFIFO_OVERFLOW_0 : in cn10kb_mcs_bbe_intr_handler()
952 reg = (dir == MCS_RX) ? MCSX_BBE_RX_SLAVE_PLFIFO_OVERFLOW_0 : in cn10kb_mcs_bbe_intr_handler()
954 val = mcs_reg_read(mcs, reg); in cn10kb_mcs_bbe_intr_handler()
1267 u64 reg = 0; in mcs_get_port_cfg() local
1273 reg = MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(req->port_id); in mcs_get_port_cfg()
1274 rsp->fifo_skid = mcs_reg_read(mcs, reg) & MCS_PORT_FIFO_SKID_MASK; in mcs_get_port_cfg()
1275 reg = MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(req->port_id); in mcs_get_port_cfg()
1276 rsp->cstm_tag_rel_mode_sel = mcs_reg_read(mcs, reg) & 0x3; in mcs_get_port_cfg()
1280 reg = MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id); in mcs_get_port_cfg()
1281 rsp->cstm_tag_rel_mode_sel = mcs_reg_read(mcs, reg) >> 2; in mcs_get_port_cfg()
1291 u64 reg = 0, val = 0; in mcs_get_custom_tag_cfg() local
1296 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_CUSTOM_TAGX(idx) : in mcs_get_custom_tag_cfg()
1299 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_VLAN_CFGX(idx) : in mcs_get_custom_tag_cfg()
1302 val = mcs_reg_read(mcs, reg); in mcs_get_custom_tag_cfg()
1306 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_ETYPE_ENABLE : in mcs_get_custom_tag_cfg()
1308 rsp->cstm_etype_en = mcs_reg_read(mcs, reg) & 0xFF; in mcs_get_custom_tag_cfg()
1322 u64 reg = MCSX_MCS_TOP_SLAVE_PORT_RESET(port_id); in mcs_reset_port() local
1324 mcs_reg_write(mcs, reg, reset & 0x1); in mcs_reset_port()
1330 u64 reg; in mcs_set_lmac_mode() local
1333 reg = MCSX_MCS_TOP_SLAVE_CHANNEL_CFG(id); in mcs_set_lmac_mode()
1334 mcs_reg_write(mcs, reg, (u64)mode); in mcs_set_lmac_mode()
1335 reg = MCSX_MCS_TOP_SLAVE_CHANNEL_CFG((id + 1)); in mcs_set_lmac_mode()
1336 mcs_reg_write(mcs, reg, (u64)mode); in mcs_set_lmac_mode()
1341 u64 reg; in mcs_pn_threshold_set() local
1344 reg = pn->xpn ? MCSX_CPM_RX_SLAVE_XPN_THRESHOLD : MCSX_CPM_RX_SLAVE_PN_THRESHOLD; in mcs_pn_threshold_set()
1346 reg = pn->xpn ? MCSX_CPM_TX_SLAVE_XPN_THRESHOLD : MCSX_CPM_TX_SLAVE_PN_THRESHOLD; in mcs_pn_threshold_set()
1348 mcs_reg_write(mcs, reg, pn->threshold); in mcs_pn_threshold_set()
1353 u64 reg, val; in cn10kb_mcs_parser_cfg() local
1358 reg = MCSX_PEX_RX_SLAVE_VLAN_CFGX(0); in cn10kb_mcs_parser_cfg()
1359 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1362 reg = MCSX_PEX_TX_SLAVE_VLAN_CFGX(0); in cn10kb_mcs_parser_cfg()
1363 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1368 reg = MCSX_PEX_RX_SLAVE_VLAN_CFGX(1); in cn10kb_mcs_parser_cfg()
1369 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1372 reg = MCSX_PEX_TX_SLAVE_VLAN_CFGX(1); in cn10kb_mcs_parser_cfg()
1373 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1378 u64 reg; in mcs_lmac_init() local
1381 reg = MCSX_PAB_RX_SLAVE_PORT_CFGX(lmac_id); in mcs_lmac_init()
1382 mcs_reg_write(mcs, reg, 0); in mcs_lmac_init()
1385 reg = MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(lmac_id); in mcs_lmac_init()
1386 mcs_reg_write(mcs, reg, 0xe000e); in mcs_lmac_init()
1390 reg = MCSX_PAB_TX_SLAVE_PORT_CFGX(lmac_id); in mcs_lmac_init()
1391 mcs_reg_write(mcs, reg, 0); in mcs_lmac_init()