marvell/octeon_ep/octep_config.h

1 /* SPDX-License-Identifier: GPL-2.0 */
18 /* Minimum input (Tx) requests to be enqueued to ring doorbell */
26 /* Rx Queue: maximum descriptors per ring */
29 /* Rx buffer size: Use page size buffers.
32  * page buffers in consecutive Rx descriptors as fragments.
60 #define CFG_GET_IQ_CFG(cfg)             ((cfg)->iq)
61 #define CFG_GET_IQ_NUM_DESC(cfg)        ((cfg)->iq.num_descs)
62 #define CFG_GET_IQ_INSTR_TYPE(cfg)      ((cfg)->iq.instr_type)
64 #define CFG_GET_IQ_DB_MIN(cfg)          ((cfg)->iq.db_min)
65 #define CFG_GET_IQ_INTR_THRESHOLD(cfg)  ((cfg)->iq.intr_threshold)
67 #define CFG_GET_OQ_NUM_DESC(cfg)          ((cfg)->oq.num_descs)
68 #define CFG_GET_OQ_BUF_SIZE(cfg)          ((cfg)->oq.buf_size)
69 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg)  ((cfg)->oq.refill_threshold)
70 #define CFG_GET_OQ_INTR_PKT(cfg)          ((cfg)->oq.oq_intr_pkt)
71 #define CFG_GET_OQ_INTR_TIME(cfg)         ((cfg)->oq.oq_intr_time)
72 #define CFG_GET_OQ_WMARK(cfg)             ((cfg)->oq.wmark)
74 #define CFG_GET_PORTS_MAX_IO_RINGS(cfg)    ((cfg)->pf_ring_cfg.max_io_rings)
75 #define CFG_GET_PORTS_ACTIVE_IO_RINGS(cfg) ((cfg)->pf_ring_cfg.active_io_rings)
76 #define CFG_GET_PORTS_PF_SRN(cfg)          ((cfg)->pf_ring_cfg.srn)
78 #define CFG_GET_CORE_TICS_PER_US(cfg)     ((cfg)->core_cfg.core_tics_per_us)
79 #define CFG_GET_COPROC_TICS_PER_US(cfg)   ((cfg)->core_cfg.coproc_tics_per_us)
81 #define CFG_GET_MAX_VFS(cfg)        ((cfg)->sriov_cfg.max_vfs)
82 #define CFG_GET_ACTIVE_VFS(cfg)     ((cfg)->sriov_cfg.active_vfs)
83 #define CFG_GET_MAX_RPVF(cfg)       ((cfg)->sriov_cfg.max_rings_per_vf)
84 #define CFG_GET_ACTIVE_RPVF(cfg)    ((cfg)->sriov_cfg.active_rings_per_vf)
85 #define CFG_GET_VF_SRN(cfg)         ((cfg)->sriov_cfg.vf_srn)
87 #define CFG_GET_IOQ_MSIX(cfg)            ((cfg)->msix_cfg.ioq_msix)
88 #define CFG_GET_NON_IOQ_MSIX(cfg)        ((cfg)->msix_cfg.non_ioq_msix)
89 #define CFG_GET_NON_IOQ_MSIX_NAMES(cfg)  ((cfg)->msix_cfg.non_ioq_msix_names)
91 #define CFG_GET_CTRL_MBOX_MEM_ADDR(cfg)  ((cfg)->ctrl_mbox_cfg.barmem_addr)
95 	/* Size of the Input queue (number of commands) */
98 	/* Command size - 32 or 64 bytes */
102 	 * hits the Input queue doorbell.
112 /* Hardware Rx Queue configuration. */
146 /* Tx/Rx configuration */
172 	/* starting ring number of VF's: ring-0 of VF-0 of the PF */
176 /* Octeon MSI-x config. */
210 	/* supported rx offloads OCTEP_ETH_RX_OFFLOAD_* */
231 	/* Input Queue attributes. */
243 	/* MSI-X interrupt config */