Lines Matching +full:armada +full:- +full:7 +full:k +full:- +full:pp22
1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
76 writel(data, priv->swth_base[0] + offset); in mvpp2_write()
81 return readl(priv->swth_base[0] + offset); in mvpp2_read()
86 return readl_relaxed(priv->swth_base[0] + offset); in mvpp2_read_relaxed()
91 return cpu % priv->nthreads; in mvpp2_cpu_to_thread()
96 writel(data, priv->cm3_base + offset); in mvpp2_cm3_write()
101 return readl(priv->cm3_base + offset); in mvpp2_cm3_read()
124 * - per-thread registers, where each thread has its own copy of the
140 * - global registers that must be accessed through a specific thread
141 * window, because they are related to an access to a per-thread
161 writel(data, priv->swth_base[thread] + offset); in mvpp2_thread_write()
167 return readl(priv->swth_base[thread] + offset); in mvpp2_thread_read()
173 writel_relaxed(data, priv->swth_base[thread] + offset); in mvpp2_thread_write_relaxed()
179 return readl_relaxed(priv->swth_base[thread] + offset); in mvpp2_thread_read_relaxed()
185 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_dma_addr_get()
186 return le32_to_cpu(tx_desc->pp21.buf_dma_addr); in mvpp2_txdesc_dma_addr_get()
188 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) & in mvpp2_txdesc_dma_addr_get()
201 if (port->priv->hw_version == MVPP21) { in mvpp2_txdesc_dma_addr_set()
202 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr); in mvpp2_txdesc_dma_addr_set()
203 tx_desc->pp21.packet_offset = offset; in mvpp2_txdesc_dma_addr_set()
207 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK); in mvpp2_txdesc_dma_addr_set()
208 tx_desc->pp22.buf_dma_addr_ptp |= val; in mvpp2_txdesc_dma_addr_set()
209 tx_desc->pp22.packet_offset = offset; in mvpp2_txdesc_dma_addr_set()
216 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_size_get()
217 return le16_to_cpu(tx_desc->pp21.data_size); in mvpp2_txdesc_size_get()
219 return le16_to_cpu(tx_desc->pp22.data_size); in mvpp2_txdesc_size_get()
226 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_size_set()
227 tx_desc->pp21.data_size = cpu_to_le16(size); in mvpp2_txdesc_size_set()
229 tx_desc->pp22.data_size = cpu_to_le16(size); in mvpp2_txdesc_size_set()
236 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_txq_set()
237 tx_desc->pp21.phys_txq = txq; in mvpp2_txdesc_txq_set()
239 tx_desc->pp22.phys_txq = txq; in mvpp2_txdesc_txq_set()
246 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_cmd_set()
247 tx_desc->pp21.command = cpu_to_le32(command); in mvpp2_txdesc_cmd_set()
249 tx_desc->pp22.command = cpu_to_le32(command); in mvpp2_txdesc_cmd_set()
255 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_offset_get()
256 return tx_desc->pp21.packet_offset; in mvpp2_txdesc_offset_get()
258 return tx_desc->pp22.packet_offset; in mvpp2_txdesc_offset_get()
264 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_dma_addr_get()
265 return le32_to_cpu(rx_desc->pp21.buf_dma_addr); in mvpp2_rxdesc_dma_addr_get()
267 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) & in mvpp2_rxdesc_dma_addr_get()
274 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_cookie_get()
275 return le32_to_cpu(rx_desc->pp21.buf_cookie); in mvpp2_rxdesc_cookie_get()
277 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) & in mvpp2_rxdesc_cookie_get()
284 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_size_get()
285 return le16_to_cpu(rx_desc->pp21.data_size); in mvpp2_rxdesc_size_get()
287 return le16_to_cpu(rx_desc->pp22.data_size); in mvpp2_rxdesc_size_get()
293 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_status_get()
294 return le32_to_cpu(rx_desc->pp21.status); in mvpp2_rxdesc_status_get()
296 return le32_to_cpu(rx_desc->pp22.status); in mvpp2_rxdesc_status_get()
301 txq_pcpu->txq_get_index++; in mvpp2_txq_inc_get()
302 if (txq_pcpu->txq_get_index == txq_pcpu->size) in mvpp2_txq_inc_get()
303 txq_pcpu->txq_get_index = 0; in mvpp2_txq_inc_get()
313 txq_pcpu->buffs + txq_pcpu->txq_put_index; in mvpp2_txq_inc_put()
314 tx_buf->type = buf_type; in mvpp2_txq_inc_put()
316 tx_buf->skb = data; in mvpp2_txq_inc_put()
318 tx_buf->xdpf = data; in mvpp2_txq_inc_put()
319 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); in mvpp2_txq_inc_put()
320 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + in mvpp2_txq_inc_put()
322 txq_pcpu->txq_put_index++; in mvpp2_txq_inc_put()
323 if (txq_pcpu->txq_put_index == txq_pcpu->size) in mvpp2_txq_inc_put()
324 txq_pcpu->txq_put_index = 0; in mvpp2_txq_inc_put()
332 if (priv->hw_version >= MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE) in mvpp2_get_nrxqs()
350 return MVPP2_MAX_TCONT + port->id; in mvpp2_egress_port()
366 if (likely(pool->frag_size <= PAGE_SIZE)) in mvpp2_frag_alloc()
367 return netdev_alloc_frag(pool->frag_size); in mvpp2_frag_alloc()
369 return kmalloc(pool->frag_size, GFP_ATOMIC); in mvpp2_frag_alloc()
377 else if (likely(pool->frag_size <= PAGE_SIZE)) in mvpp2_frag_free()
395 return -EINVAL; in mvpp2_bm_pool_create()
400 if (priv->hw_version == MVPP21) in mvpp2_bm_pool_create()
401 bm_pool->size_bytes = 2 * sizeof(u32) * size; in mvpp2_bm_pool_create()
403 bm_pool->size_bytes = 2 * sizeof(u64) * size; in mvpp2_bm_pool_create()
405 bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes, in mvpp2_bm_pool_create()
406 &bm_pool->dma_addr, in mvpp2_bm_pool_create()
408 if (!bm_pool->virt_addr) in mvpp2_bm_pool_create()
409 return -ENOMEM; in mvpp2_bm_pool_create()
411 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, in mvpp2_bm_pool_create()
413 dma_free_coherent(dev, bm_pool->size_bytes, in mvpp2_bm_pool_create()
414 bm_pool->virt_addr, bm_pool->dma_addr); in mvpp2_bm_pool_create()
416 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); in mvpp2_bm_pool_create()
417 return -ENOMEM; in mvpp2_bm_pool_create()
420 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), in mvpp2_bm_pool_create()
421 lower_32_bits(bm_pool->dma_addr)); in mvpp2_bm_pool_create()
422 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); in mvpp2_bm_pool_create()
424 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); in mvpp2_bm_pool_create()
431 if (priv->hw_version == MVPP23) { in mvpp2_bm_pool_create()
439 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_create()
441 bm_pool->size = size; in mvpp2_bm_pool_create()
442 bm_pool->pkt_size = 0; in mvpp2_bm_pool_create()
443 bm_pool->buf_num = 0; in mvpp2_bm_pool_create()
455 bm_pool->buf_size = buf_size; in mvpp2_bm_pool_bufsize_set()
458 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); in mvpp2_bm_pool_bufsize_set()
469 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); in mvpp2_bm_bufs_get_addrs()
472 if (priv->hw_version >= MVPP22) { in mvpp2_bm_bufs_get_addrs()
498 if (buf_num > bm_pool->buf_num) { in mvpp2_bm_bufs_free()
500 bm_pool->id, buf_num); in mvpp2_bm_bufs_free()
501 buf_num = bm_pool->buf_num; in mvpp2_bm_bufs_free()
504 if (priv->percpu_pools) in mvpp2_bm_bufs_free()
505 pp = priv->page_pool[bm_pool->id]; in mvpp2_bm_bufs_free()
517 bm_pool->buf_size, DMA_FROM_DEVICE); in mvpp2_bm_bufs_free()
527 bm_pool->buf_num -= i; in mvpp2_bm_bufs_free()
535 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & in mvpp2_check_hw_buf_num()
537 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & in mvpp2_check_hw_buf_num()
561 bm_pool->id, bm_pool->buf_num); in mvpp2_bm_pool_destroy()
565 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); in mvpp2_bm_pool_destroy()
567 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); in mvpp2_bm_pool_destroy()
569 if (priv->percpu_pools) { in mvpp2_bm_pool_destroy()
570 page_pool_destroy(priv->page_pool[bm_pool->id]); in mvpp2_bm_pool_destroy()
571 priv->page_pool[bm_pool->id] = NULL; in mvpp2_bm_pool_destroy()
574 dma_free_coherent(dev, bm_pool->size_bytes, in mvpp2_bm_pool_destroy()
575 bm_pool->virt_addr, in mvpp2_bm_pool_destroy()
576 bm_pool->dma_addr); in mvpp2_bm_pool_destroy()
585 if (priv->percpu_pools) in mvpp2_bm_pools_init()
591 bm_pool = &priv->bm_pools[i]; in mvpp2_bm_pools_init()
592 bm_pool->id = i; in mvpp2_bm_pools_init()
602 for (i = i - 1; i >= 0; i--) in mvpp2_bm_pools_init()
603 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]); in mvpp2_bm_pools_init()
642 if (priv->percpu_pools) in mvpp2_bm_init()
649 if (priv->percpu_pools) { in mvpp2_bm_init()
650 for (i = 0; i < priv->port_count; i++) { in mvpp2_bm_init()
651 port = priv->port_list[i]; in mvpp2_bm_init()
652 if (port->xdp_prog) { in mvpp2_bm_init()
662 priv->page_pool[i] = in mvpp2_bm_init()
667 if (IS_ERR(priv->page_pool[i])) { in mvpp2_bm_init()
671 page_pool_destroy(priv->page_pool[j]); in mvpp2_bm_init()
672 priv->page_pool[j] = NULL; in mvpp2_bm_init()
674 return PTR_ERR(priv->page_pool[i]); in mvpp2_bm_init()
680 priv->percpu_pools ? "per-cpu" : "shared"); in mvpp2_bm_init()
690 priv->bm_pools = devm_kcalloc(dev, poolnum, in mvpp2_bm_init()
691 sizeof(*priv->bm_pools), GFP_KERNEL); in mvpp2_bm_init()
692 if (!priv->bm_pools) in mvpp2_bm_init()
693 return -ENOMEM; in mvpp2_bm_init()
695 if (priv->hw_version == MVPP23) in mvpp2_bm_init()
727 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_long_pool_set()
729 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_long_pool_set()
734 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_long_pool_set()
737 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
748 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_short_pool_set()
750 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_short_pool_set()
755 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_short_pool_set()
758 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_short_pool_set()
781 dma_addr = dma_map_single(port->dev->dev.parent, data, in mvpp2_buf_alloc()
782 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), in mvpp2_buf_alloc()
784 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { in mvpp2_buf_alloc()
799 int fq = port->first_rxq; in mvpp2_rxq_enable_fc()
802 spin_lock_irqsave(&port->priv->mss_spinlock, flags); in mvpp2_rxq_enable_fc()
805 * If Flow control was enabled, it would be re-enabled. in mvpp2_rxq_enable_fc()
807 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_rxq_enable_fc()
810 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_rxq_enable_fc()
813 for (q = 0; q < port->nrxqs; q++) { in mvpp2_rxq_enable_fc()
817 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val); in mvpp2_rxq_enable_fc()
819 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq)); in mvpp2_rxq_enable_fc()
822 val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq)); in mvpp2_rxq_enable_fc()
834 host_id = port->nqvecs; in mvpp2_rxq_enable_fc()
844 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val); in mvpp2_rxq_enable_fc()
848 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_rxq_enable_fc()
851 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_rxq_enable_fc()
853 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); in mvpp2_rxq_enable_fc()
861 int fq = port->first_rxq; in mvpp2_rxq_disable_fc()
863 spin_lock_irqsave(&port->priv->mss_spinlock, flags); in mvpp2_rxq_disable_fc()
866 * If Flow control was enabled, it would be re-enabled. in mvpp2_rxq_disable_fc()
868 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_rxq_disable_fc()
871 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_rxq_disable_fc()
874 for (q = 0; q < port->nrxqs; q++) { in mvpp2_rxq_disable_fc()
878 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val); in mvpp2_rxq_disable_fc()
880 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq)); in mvpp2_rxq_disable_fc()
887 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val); in mvpp2_rxq_disable_fc()
891 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_rxq_disable_fc()
894 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_rxq_disable_fc()
896 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); in mvpp2_rxq_disable_fc()
907 spin_lock_irqsave(&port->priv->mss_spinlock, flags); in mvpp2_bm_pool_update_fc()
910 * If Flow control were enabled, it would be re-enabled. in mvpp2_bm_pool_update_fc()
912 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_bm_pool_update_fc()
915 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_bm_pool_update_fc()
920 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id)); in mvpp2_bm_pool_update_fc()
921 val |= MSS_BUF_POOL_PORT_OFFS(port->id); in mvpp2_bm_pool_update_fc()
926 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val); in mvpp2_bm_pool_update_fc()
929 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id)); in mvpp2_bm_pool_update_fc()
930 val &= ~MSS_BUF_POOL_PORT_OFFS(port->id); in mvpp2_bm_pool_update_fc()
935 if (!pool->buf_num) { in mvpp2_bm_pool_update_fc()
940 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val); in mvpp2_bm_pool_update_fc()
944 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_bm_pool_update_fc()
947 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_bm_pool_update_fc()
949 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); in mvpp2_bm_pool_update_fc()
958 for (i = 0; i < priv->port_count; i++) { in mvpp2_bm_pool_update_priv_fc()
959 port = priv->port_list[i]; in mvpp2_bm_pool_update_priv_fc()
960 if (port->priv->percpu_pools) { in mvpp2_bm_pool_update_priv_fc()
961 for (j = 0; j < port->nrxqs; j++) in mvpp2_bm_pool_update_priv_fc()
962 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[j], in mvpp2_bm_pool_update_priv_fc()
963 port->tx_fc & en); in mvpp2_bm_pool_update_priv_fc()
965 mvpp2_bm_pool_update_fc(port, port->pool_long, port->tx_fc & en); in mvpp2_bm_pool_update_priv_fc()
966 mvpp2_bm_pool_update_fc(port, port->pool_short, port->tx_fc & en); in mvpp2_bm_pool_update_priv_fc()
995 priv->global_tx_fc = false; in mvpp2_enable_global_fc()
996 return -EOPNOTSUPP; in mvpp2_enable_global_fc()
1004 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_bm_pool_put()
1007 if (test_bit(thread, &port->priv->lock_map)) in mvpp2_bm_pool_put()
1008 spin_lock_irqsave(&port->bm_lock[thread], flags); in mvpp2_bm_pool_put()
1010 if (port->priv->hw_version >= MVPP22) { in mvpp2_bm_pool_put()
1022 mvpp2_thread_write_relaxed(port->priv, thread, in mvpp2_bm_pool_put()
1031 mvpp2_thread_write_relaxed(port->priv, thread, in mvpp2_bm_pool_put()
1033 mvpp2_thread_write_relaxed(port->priv, thread, in mvpp2_bm_pool_put()
1036 if (test_bit(thread, &port->priv->lock_map)) in mvpp2_bm_pool_put()
1037 spin_unlock_irqrestore(&port->bm_lock[thread], flags); in mvpp2_bm_pool_put()
1052 if (port->priv->percpu_pools && in mvpp2_bm_bufs_add()
1053 bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { in mvpp2_bm_bufs_add()
1054 netdev_err(port->dev, in mvpp2_bm_bufs_add()
1055 "attempted to use jumbo frames with per-cpu pools"); in mvpp2_bm_bufs_add()
1059 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); in mvpp2_bm_bufs_add()
1063 (buf_num + bm_pool->buf_num > bm_pool->size)) { in mvpp2_bm_bufs_add()
1064 netdev_err(port->dev, in mvpp2_bm_bufs_add()
1066 buf_num, bm_pool->id); in mvpp2_bm_bufs_add()
1070 if (port->priv->percpu_pools) in mvpp2_bm_bufs_add()
1071 pp = port->priv->page_pool[bm_pool->id]; in mvpp2_bm_bufs_add()
1078 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, in mvpp2_bm_bufs_add()
1083 bm_pool->buf_num += i; in mvpp2_bm_bufs_add()
1085 netdev_dbg(port->dev, in mvpp2_bm_bufs_add()
1087 bm_pool->id, bm_pool->pkt_size, buf_size, total_size); in mvpp2_bm_bufs_add()
1089 netdev_dbg(port->dev, in mvpp2_bm_bufs_add()
1091 bm_pool->id, i, buf_num); in mvpp2_bm_bufs_add()
1101 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; in mvpp2_bm_pool_use()
1104 if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) || in mvpp2_bm_pool_use()
1105 (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) { in mvpp2_bm_pool_use()
1106 netdev_err(port->dev, "Invalid pool %d\n", pool); in mvpp2_bm_pool_use()
1113 if (new_pool->pkt_size == 0) { in mvpp2_bm_pool_use()
1119 pkts_num = new_pool->buf_num; in mvpp2_bm_pool_use()
1121 if (port->priv->percpu_pools) { in mvpp2_bm_pool_use()
1122 if (pool < port->nrxqs) in mvpp2_bm_pool_use()
1130 mvpp2_bm_bufs_free(port->dev->dev.parent, in mvpp2_bm_pool_use()
1131 port->priv, new_pool, pkts_num); in mvpp2_bm_pool_use()
1134 new_pool->pkt_size = pkt_size; in mvpp2_bm_pool_use()
1135 new_pool->frag_size = in mvpp2_bm_pool_use()
1143 new_pool->id, num, pkts_num); in mvpp2_bm_pool_use()
1148 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, in mvpp2_bm_pool_use()
1149 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); in mvpp2_bm_pool_use()
1158 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; in mvpp2_bm_pool_use_percpu()
1161 if (pool > port->nrxqs * 2) { in mvpp2_bm_pool_use_percpu()
1162 netdev_err(port->dev, "Invalid pool %d\n", pool); in mvpp2_bm_pool_use_percpu()
1169 if (new_pool->pkt_size == 0) { in mvpp2_bm_pool_use_percpu()
1175 pkts_num = new_pool->buf_num; in mvpp2_bm_pool_use_percpu()
1179 mvpp2_bm_bufs_free(port->dev->dev.parent, in mvpp2_bm_pool_use_percpu()
1180 port->priv, new_pool, pkts_num); in mvpp2_bm_pool_use_percpu()
1182 new_pool->pkt_size = pkt_size; in mvpp2_bm_pool_use_percpu()
1183 new_pool->frag_size = in mvpp2_bm_pool_use_percpu()
1191 new_pool->id, num, pkts_num); in mvpp2_bm_pool_use_percpu()
1196 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, in mvpp2_bm_pool_use_percpu()
1197 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); in mvpp2_bm_pool_use_percpu()
1209 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool in mvpp2_swf_bm_pool_init_shared()
1210 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool in mvpp2_swf_bm_pool_init_shared()
1212 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { in mvpp2_swf_bm_pool_init_shared()
1220 if (!port->pool_long) { in mvpp2_swf_bm_pool_init_shared()
1221 port->pool_long = in mvpp2_swf_bm_pool_init_shared()
1224 if (!port->pool_long) in mvpp2_swf_bm_pool_init_shared()
1225 return -ENOMEM; in mvpp2_swf_bm_pool_init_shared()
1227 port->pool_long->port_map |= BIT(port->id); in mvpp2_swf_bm_pool_init_shared()
1229 for (rxq = 0; rxq < port->nrxqs; rxq++) in mvpp2_swf_bm_pool_init_shared()
1230 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); in mvpp2_swf_bm_pool_init_shared()
1233 if (!port->pool_short) { in mvpp2_swf_bm_pool_init_shared()
1234 port->pool_short = in mvpp2_swf_bm_pool_init_shared()
1237 if (!port->pool_short) in mvpp2_swf_bm_pool_init_shared()
1238 return -ENOMEM; in mvpp2_swf_bm_pool_init_shared()
1240 port->pool_short->port_map |= BIT(port->id); in mvpp2_swf_bm_pool_init_shared()
1242 for (rxq = 0; rxq < port->nrxqs; rxq++) in mvpp2_swf_bm_pool_init_shared()
1244 port->pool_short->id); in mvpp2_swf_bm_pool_init_shared()
1256 for (i = 0; i < port->nrxqs; i++) { in mvpp2_swf_bm_pool_init_percpu()
1260 return -ENOMEM; in mvpp2_swf_bm_pool_init_percpu()
1262 bm_pool->port_map |= BIT(port->id); in mvpp2_swf_bm_pool_init_percpu()
1263 mvpp2_rxq_short_pool_set(port, i, bm_pool->id); in mvpp2_swf_bm_pool_init_percpu()
1266 for (i = 0; i < port->nrxqs; i++) { in mvpp2_swf_bm_pool_init_percpu()
1267 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs, in mvpp2_swf_bm_pool_init_percpu()
1270 return -ENOMEM; in mvpp2_swf_bm_pool_init_percpu()
1272 bm_pool->port_map |= BIT(port->id); in mvpp2_swf_bm_pool_init_percpu()
1273 mvpp2_rxq_long_pool_set(port, i, bm_pool->id); in mvpp2_swf_bm_pool_init_percpu()
1276 port->pool_long = NULL; in mvpp2_swf_bm_pool_init_percpu()
1277 port->pool_short = NULL; in mvpp2_swf_bm_pool_init_percpu()
1284 if (port->priv->percpu_pools) in mvpp2_swf_bm_pool_init()
1299 * has 7 bits, so the maximum L3 offset is 128. in mvpp2_set_hw_csum()
1301 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { in mvpp2_set_hw_csum()
1302 port->dev->features &= ~csums; in mvpp2_set_hw_csum()
1303 port->dev->hw_features &= ~csums; in mvpp2_set_hw_csum()
1305 port->dev->features |= csums; in mvpp2_set_hw_csum()
1306 port->dev->hw_features |= csums; in mvpp2_set_hw_csum()
1316 if (port->priv->percpu_pools) in mvpp2_bm_update_mtu()
1320 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool in mvpp2_bm_update_mtu()
1321 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool in mvpp2_bm_update_mtu()
1328 if (new_long_pool != port->pool_long->id) { in mvpp2_bm_update_mtu()
1329 if (port->tx_fc) { in mvpp2_bm_update_mtu()
1332 port->pool_short, in mvpp2_bm_update_mtu()
1335 mvpp2_bm_pool_update_fc(port, port->pool_long, in mvpp2_bm_update_mtu()
1340 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, in mvpp2_bm_update_mtu()
1341 port->pool_long->pkt_size); in mvpp2_bm_update_mtu()
1342 port->pool_long->port_map &= ~BIT(port->id); in mvpp2_bm_update_mtu()
1343 port->pool_long = NULL; in mvpp2_bm_update_mtu()
1345 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, in mvpp2_bm_update_mtu()
1346 port->pool_short->pkt_size); in mvpp2_bm_update_mtu()
1347 port->pool_short->port_map &= ~BIT(port->id); in mvpp2_bm_update_mtu()
1348 port->pool_short = NULL; in mvpp2_bm_update_mtu()
1350 port->pkt_size = pkt_size; in mvpp2_bm_update_mtu()
1357 if (port->tx_fc) { in mvpp2_bm_update_mtu()
1359 mvpp2_bm_pool_update_fc(port, port->pool_long, in mvpp2_bm_update_mtu()
1362 mvpp2_bm_pool_update_fc(port, port->pool_short, in mvpp2_bm_update_mtu()
1367 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { in mvpp2_bm_update_mtu()
1368 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); in mvpp2_bm_update_mtu()
1369 dev->hw_features &= ~(NETIF_F_IP_CSUM | in mvpp2_bm_update_mtu()
1372 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; in mvpp2_bm_update_mtu()
1373 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; in mvpp2_bm_update_mtu()
1378 WRITE_ONCE(dev->mtu, mtu); in mvpp2_bm_update_mtu()
1379 dev->wanted_features = dev->features; in mvpp2_bm_update_mtu()
1389 for (i = 0; i < port->nqvecs; i++) in mvpp2_interrupts_enable()
1390 sw_thread_mask |= port->qvecs[i].sw_thread_mask; in mvpp2_interrupts_enable()
1392 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_enable()
1400 for (i = 0; i < port->nqvecs; i++) in mvpp2_interrupts_disable()
1401 sw_thread_mask |= port->qvecs[i].sw_thread_mask; in mvpp2_interrupts_disable()
1403 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_disable()
1409 struct mvpp2_port *port = qvec->port; in mvpp2_qvec_interrupt_enable()
1411 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_qvec_interrupt_enable()
1412 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); in mvpp2_qvec_interrupt_enable()
1417 struct mvpp2_port *port = qvec->port; in mvpp2_qvec_interrupt_disable()
1419 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_qvec_interrupt_disable()
1420 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); in mvpp2_qvec_interrupt_disable()
1434 if (cpu > port->priv->nthreads) in mvpp2_interrupts_mask()
1437 thread = mvpp2_cpu_to_thread(port->priv, cpu); in mvpp2_interrupts_mask()
1439 mvpp2_thread_write(port->priv, thread, in mvpp2_interrupts_mask()
1440 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); in mvpp2_interrupts_mask()
1441 mvpp2_thread_write(port->priv, thread, in mvpp2_interrupts_mask()
1442 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0); in mvpp2_interrupts_mask()
1456 if (cpu >= port->priv->nthreads) in mvpp2_interrupts_unmask()
1459 thread = mvpp2_cpu_to_thread(port->priv, cpu); in mvpp2_interrupts_unmask()
1462 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); in mvpp2_interrupts_unmask()
1463 if (port->has_tx_irqs) in mvpp2_interrupts_unmask()
1466 mvpp2_thread_write(port->priv, thread, in mvpp2_interrupts_unmask()
1467 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); in mvpp2_interrupts_unmask()
1468 mvpp2_thread_write(port->priv, thread, in mvpp2_interrupts_unmask()
1469 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), in mvpp2_interrupts_unmask()
1479 if (port->priv->hw_version == MVPP21) in mvpp2_shared_interrupt_mask_unmask()
1487 for (i = 0; i < port->nqvecs; i++) { in mvpp2_shared_interrupt_mask_unmask()
1488 struct mvpp2_queue_vector *v = port->qvecs + i; in mvpp2_shared_interrupt_mask_unmask()
1490 if (v->type != MVPP2_QUEUE_VECTOR_SHARED) in mvpp2_shared_interrupt_mask_unmask()
1493 mvpp2_thread_write(port->priv, v->sw_thread_id, in mvpp2_shared_interrupt_mask_unmask()
1494 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); in mvpp2_shared_interrupt_mask_unmask()
1495 mvpp2_thread_write(port->priv, v->sw_thread_id, in mvpp2_shared_interrupt_mask_unmask()
1496 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), in mvpp2_shared_interrupt_mask_unmask()
1504 return port->gop_id == 0; in mvpp2_port_supports_xlg()
1509 return !(port->priv->hw_version >= MVPP22 && port->gop_id == 0); in mvpp2_port_supports_rgmii()
1533 struct mvpp2 *priv = port->priv; in mvpp22_gop_init_rgmii()
1536 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); in mvpp22_gop_init_rgmii()
1538 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); in mvpp22_gop_init_rgmii()
1540 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); in mvpp22_gop_init_rgmii()
1541 if (port->gop_id == 2) { in mvpp22_gop_init_rgmii()
1543 } else if (port->gop_id == 3) { in mvpp22_gop_init_rgmii()
1549 * U-Boot does for mvpp2, so it is assumed to be correct. in mvpp22_gop_init_rgmii()
1551 if (port->phy_interface == PHY_INTERFACE_MODE_MII) in mvpp22_gop_init_rgmii()
1556 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); in mvpp22_gop_init_rgmii()
1561 struct mvpp2 *priv = port->priv; in mvpp22_gop_init_sgmii()
1564 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); in mvpp22_gop_init_sgmii()
1567 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); in mvpp22_gop_init_sgmii()
1569 if (port->gop_id > 1) { in mvpp22_gop_init_sgmii()
1570 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); in mvpp22_gop_init_sgmii()
1571 if (port->gop_id == 2) in mvpp22_gop_init_sgmii()
1573 else if (port->gop_id == 3) in mvpp22_gop_init_sgmii()
1575 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); in mvpp22_gop_init_sgmii()
1581 struct mvpp2 *priv = port->priv; in mvpp22_gop_init_10gkr()
1582 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); in mvpp22_gop_init_10gkr()
1583 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); in mvpp22_gop_init_10gkr()
1604 struct mvpp2 *priv = port->priv; in mvpp22_gop_fca_enable_periodic()
1605 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); in mvpp22_gop_fca_enable_periodic()
1617 struct mvpp2 *priv = port->priv; in mvpp22_gop_fca_set_timer()
1618 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); in mvpp22_gop_fca_set_timer()
1635 timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER)) in mvpp22_gop_fca_set_periodic_timer()
1647 struct mvpp2 *priv = port->priv; in mvpp22_gop_init()
1650 if (!priv->sysctrl_base) in mvpp22_gop_init()
1678 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); in mvpp22_gop_init()
1679 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | in mvpp22_gop_init()
1680 GENCONF_PORT_CTRL1_EN(port->gop_id); in mvpp22_gop_init()
1681 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); in mvpp22_gop_init()
1683 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); in mvpp22_gop_init()
1685 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); in mvpp22_gop_init()
1687 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); in mvpp22_gop_init()
1689 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); in mvpp22_gop_init()
1697 netdev_err(port->dev, "Invalid port configuration\n"); in mvpp22_gop_init()
1698 return -EINVAL; in mvpp22_gop_init()
1705 if (phy_interface_mode_is_rgmii(port->phy_interface) || in mvpp22_gop_unmask_irq()
1706 phy_interface_mode_is_8023z(port->phy_interface) || in mvpp22_gop_unmask_irq()
1707 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { in mvpp22_gop_unmask_irq()
1709 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_unmask_irq()
1711 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_unmask_irq()
1716 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_unmask_irq()
1717 if (mvpp2_is_xlg(port->phy_interface)) in mvpp22_gop_unmask_irq()
1721 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_unmask_irq()
1730 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_mask_irq()
1733 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_mask_irq()
1736 if (phy_interface_mode_is_rgmii(port->phy_interface) || in mvpp22_gop_mask_irq()
1737 phy_interface_mode_is_8023z(port->phy_interface) || in mvpp22_gop_mask_irq()
1738 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { in mvpp22_gop_mask_irq()
1739 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_mask_irq()
1741 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_mask_irq()
1749 mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK, in mvpp22_gop_setup_irq()
1753 if (port->phylink || in mvpp22_gop_setup_irq()
1754 phy_interface_mode_is_rgmii(port->phy_interface) || in mvpp22_gop_setup_irq()
1755 phy_interface_mode_is_8023z(port->phy_interface) || in mvpp22_gop_setup_irq()
1756 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { in mvpp22_gop_setup_irq()
1757 val = readl(port->base + MVPP22_GMAC_INT_MASK); in mvpp22_gop_setup_irq()
1759 writel(val, port->base + MVPP22_GMAC_INT_MASK); in mvpp22_gop_setup_irq()
1763 val = readl(port->base + MVPP22_XLG_INT_MASK); in mvpp22_gop_setup_irq()
1765 writel(val, port->base + MVPP22_XLG_INT_MASK); in mvpp22_gop_setup_irq()
1767 mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK, in mvpp22_gop_setup_irq()
1783 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1790 if (!port->comphy) in mvpp22_comphy_init()
1793 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, interface); in mvpp22_comphy_init()
1797 return phy_power_on(port->comphy); in mvpp22_comphy_init()
1805 mvpp2_is_xlg(port->phy_interface)) { in mvpp2_port_enable()
1806 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()
1809 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()
1811 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
1814 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
1823 mvpp2_is_xlg(port->phy_interface)) { in mvpp2_port_disable()
1824 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()
1826 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()
1829 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
1831 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
1839 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & in mvpp2_port_periodic_xon_disable()
1841 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_periodic_xon_disable()
1850 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
1852 if (state->speed == 1000) in mvpp2_port_loopback_set()
1857 if (phy_interface_mode_is_8023z(state->interface) || in mvpp2_port_loopback_set()
1858 state->interface == PHY_INTERFACE_MODE_SGMII) in mvpp2_port_loopback_set()
1863 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
1887 val = readl(port->stats_base + counter->offset); in mvpp2_read_count()
1888 if (counter->reg_is_64b) in mvpp2_read_count()
1889 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; in mvpp2_read_count()
2005 for (q = 0; q < port->ntxqs; q++) { in mvpp2_ethtool_get_strings()
2013 for (q = 0; q < port->nrxqs; q++) { in mvpp2_ethtool_get_strings()
2046 cpu_stats = per_cpu_ptr(port->stats, cpu); in mvpp2_get_xdp_stats()
2048 start = u64_stats_fetch_begin(&cpu_stats->syncp); in mvpp2_get_xdp_stats()
2049 xdp_redirect = cpu_stats->xdp_redirect; in mvpp2_get_xdp_stats()
2050 xdp_pass = cpu_stats->xdp_pass; in mvpp2_get_xdp_stats()
2051 xdp_drop = cpu_stats->xdp_drop; in mvpp2_get_xdp_stats()
2052 xdp_xmit = cpu_stats->xdp_xmit; in mvpp2_get_xdp_stats()
2053 xdp_xmit_err = cpu_stats->xdp_xmit_err; in mvpp2_get_xdp_stats()
2054 xdp_tx = cpu_stats->xdp_tx; in mvpp2_get_xdp_stats()
2055 xdp_tx_err = cpu_stats->xdp_tx_err; in mvpp2_get_xdp_stats()
2056 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start)); in mvpp2_get_xdp_stats()
2058 xdp_stats->xdp_redirect += xdp_redirect; in mvpp2_get_xdp_stats()
2059 xdp_stats->xdp_pass += xdp_pass; in mvpp2_get_xdp_stats()
2060 xdp_stats->xdp_drop += xdp_drop; in mvpp2_get_xdp_stats()
2061 xdp_stats->xdp_xmit += xdp_xmit; in mvpp2_get_xdp_stats()
2062 xdp_stats->xdp_xmit_err += xdp_xmit_err; in mvpp2_get_xdp_stats()
2063 xdp_stats->xdp_tx += xdp_tx; in mvpp2_get_xdp_stats()
2064 xdp_stats->xdp_tx_err += xdp_tx_err; in mvpp2_get_xdp_stats()
2075 pstats = port->ethtool_stats; in mvpp2_read_stats()
2081 *pstats++ += mvpp2_read(port->priv, in mvpp2_read_stats()
2083 4 * port->id); in mvpp2_read_stats()
2085 for (q = 0; q < port->ntxqs; q++) in mvpp2_read_stats()
2087 *pstats++ += mvpp2_read_index(port->priv, in mvpp2_read_stats()
2088 MVPP22_CTRS_TX_CTR(port->id, q), in mvpp2_read_stats()
2092 * driver's. We need to add the port->first_rxq offset. in mvpp2_read_stats()
2094 for (q = 0; q < port->nrxqs; q++) in mvpp2_read_stats()
2096 *pstats++ += mvpp2_read_index(port->priv, in mvpp2_read_stats()
2097 port->first_rxq + q, in mvpp2_read_stats()
2106 switch (s->offset) { in mvpp2_read_stats()
2138 mutex_lock(&port->gather_stats_lock); in mvpp2_gather_hw_statistics()
2145 cancel_delayed_work(&port->stats_work); in mvpp2_gather_hw_statistics()
2146 queue_delayed_work(port->priv->stats_queue, &port->stats_work, in mvpp2_gather_hw_statistics()
2149 mutex_unlock(&port->gather_stats_lock); in mvpp2_gather_hw_statistics()
2160 mvpp2_gather_hw_statistics(&port->stats_work.work); in mvpp2_ethtool_get_stats()
2162 mutex_lock(&port->gather_stats_lock); in mvpp2_ethtool_get_stats()
2163 memcpy(data, port->ethtool_stats, in mvpp2_ethtool_get_stats()
2164 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs)); in mvpp2_ethtool_get_stats()
2165 mutex_unlock(&port->gather_stats_lock); in mvpp2_ethtool_get_stats()
2173 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs); in mvpp2_ethtool_get_sset_count()
2175 return -EOPNOTSUPP; in mvpp2_ethtool_get_sset_count()
2182 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | in mvpp2_mac_reset_assert()
2184 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_mac_reset_assert()
2186 if (port->priv->hw_version >= MVPP22 && port->gop_id == 0) { in mvpp2_mac_reset_assert()
2187 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & in mvpp2_mac_reset_assert()
2189 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_mac_reset_assert()
2195 struct mvpp2 *priv = port->priv; in mvpp22_pcs_reset_assert()
2199 if (port->priv->hw_version == MVPP21 || port->gop_id != 0) in mvpp22_pcs_reset_assert()
2202 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); in mvpp22_pcs_reset_assert()
2203 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); in mvpp22_pcs_reset_assert()
2217 struct mvpp2 *priv = port->priv; in mvpp22_pcs_reset_deassert()
2221 if (port->priv->hw_version == MVPP21 || port->gop_id != 0) in mvpp22_pcs_reset_deassert()
2224 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); in mvpp22_pcs_reset_deassert()
2225 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); in mvpp22_pcs_reset_deassert()
2251 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2253 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << in mvpp2_gmac_max_rx_size_set()
2255 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2263 val = readl(port->base + MVPP22_XLG_CTRL1_REG); in mvpp2_xlg_max_rx_size_set()
2265 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << in mvpp2_xlg_max_rx_size_set()
2267 writel(val, port->base + MVPP22_XLG_CTRL1_REG); in mvpp2_xlg_max_rx_size_set()
2275 if (port->priv->hw_version == MVPP21) { in mvpp2_defaults_set()
2277 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
2280 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); in mvpp2_defaults_set()
2281 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
2286 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set()
2288 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); in mvpp2_defaults_set()
2290 /* Set TXQ scheduling to Round-Robin */ in mvpp2_defaults_set()
2291 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); in mvpp2_defaults_set()
2295 mvpp2_write(port->priv, in mvpp2_defaults_set()
2301 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, in mvpp2_defaults_set()
2302 port->priv->tclk / USEC_PER_SEC); in mvpp2_defaults_set()
2303 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); in mvpp2_defaults_set()
2307 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); in mvpp2_defaults_set()
2309 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_defaults_set()
2312 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), in mvpp2_defaults_set()
2317 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { in mvpp2_defaults_set()
2318 queue = port->rxqs[lrxq]->id; in mvpp2_defaults_set()
2319 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_defaults_set()
2322 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_defaults_set()
2335 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { in mvpp2_ingress_enable()
2336 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_enable()
2337 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_enable()
2339 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_enable()
2348 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { in mvpp2_ingress_disable()
2349 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_disable()
2350 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_disable()
2352 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_disable()
2357 * - HW starts take descriptors from DRAM
2367 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_egress_enable()
2368 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_egress_enable()
2370 if (txq->descs) in mvpp2_egress_enable()
2374 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable()
2375 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); in mvpp2_egress_enable()
2379 * - HW doesn't take descriptors from DRAM
2388 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable()
2389 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & in mvpp2_egress_disable()
2392 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, in mvpp2_egress_disable()
2399 netdev_warn(port->dev, in mvpp2_egress_disable()
2410 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); in mvpp2_egress_disable()
2420 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); in mvpp2_rxq_received()
2437 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); in mvpp2_rxq_status_update()
2444 int rx_desc = rxq->next_desc_to_proc; in mvpp2_rxq_next_desc_get()
2446 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); in mvpp2_rxq_next_desc_get()
2447 prefetch(rxq->descs + rxq->next_desc_to_proc); in mvpp2_rxq_next_desc_get()
2448 return rxq->descs + rx_desc; in mvpp2_rxq_next_desc_get()
2460 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_offset_set()
2467 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_offset_set()
2476 int tx_desc = txq->next_desc_to_proc; in mvpp2_txq_next_desc_get()
2478 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); in mvpp2_txq_next_desc_get()
2479 return txq->descs + tx_desc; in mvpp2_txq_next_desc_get()
2489 /* aggregated access - relevant TXQ number is written in TX desc */ in mvpp2_aggr_txq_pend_desc_add()
2490 mvpp2_thread_write(port->priv, in mvpp2_aggr_txq_pend_desc_add()
2491 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), in mvpp2_aggr_txq_pend_desc_add()
2504 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { in mvpp2_aggr_desc_num_check()
2507 mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_aggr_desc_num_check()
2508 u32 val = mvpp2_read_relaxed(port->priv, in mvpp2_aggr_desc_num_check()
2511 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; in mvpp2_aggr_desc_num_check()
2513 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) in mvpp2_aggr_desc_num_check()
2514 return -ENOMEM; in mvpp2_aggr_desc_num_check()
2528 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_txq_alloc_reserved_desc()
2529 struct mvpp2 *priv = port->priv; in mvpp2_txq_alloc_reserved_desc()
2532 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; in mvpp2_txq_alloc_reserved_desc()
2551 if (txq_pcpu->reserved_num >= num) in mvpp2_txq_reserved_desc_num_proc()
2560 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_txq_reserved_desc_num_proc()
2563 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread); in mvpp2_txq_reserved_desc_num_proc()
2564 desc_count += txq_pcpu_aux->count; in mvpp2_txq_reserved_desc_num_proc()
2565 desc_count += txq_pcpu_aux->reserved_num; in mvpp2_txq_reserved_desc_num_proc()
2568 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); in mvpp2_txq_reserved_desc_num_proc()
2572 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK))) in mvpp2_txq_reserved_desc_num_proc()
2573 return -ENOMEM; in mvpp2_txq_reserved_desc_num_proc()
2575 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req); in mvpp2_txq_reserved_desc_num_proc()
2578 if (txq_pcpu->reserved_num < num) in mvpp2_txq_reserved_desc_num_proc()
2579 return -ENOMEM; in mvpp2_txq_reserved_desc_num_proc()
2588 if (txq->next_desc_to_proc == 0) in mvpp2_txq_desc_put()
2589 txq->next_desc_to_proc = txq->last_desc - 1; in mvpp2_txq_desc_put()
2591 txq->next_desc_to_proc--; in mvpp2_txq_desc_put()
2629 * Per-thread access
2641 val = mvpp2_thread_read_relaxed(port->priv, in mvpp2_txq_sent_desc_proc()
2642 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), in mvpp2_txq_sent_desc_proc()
2643 MVPP2_TXQ_SENT_REG(txq->id)); in mvpp2_txq_sent_desc_proc()
2658 if (smp_processor_id() >= port->priv->nthreads) in mvpp2_txq_sent_counter_clear()
2661 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_txq_sent_counter_clear()
2662 int id = port->txqs[queue]->id; in mvpp2_txq_sent_counter_clear()
2664 mvpp2_thread_read(port->priv, in mvpp2_txq_sent_counter_clear()
2665 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), in mvpp2_txq_sent_counter_clear()
2676 mtu = port->pkt_size * 8; in mvpp2_txp_max_tx_size_set()
2685 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set()
2688 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); in mvpp2_txp_max_tx_size_set()
2691 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); in mvpp2_txp_max_tx_size_set()
2694 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); in mvpp2_txp_max_tx_size_set()
2700 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_txp_max_tx_size_set()
2703 for (txq = 0; txq < port->ntxqs; txq++) { in mvpp2_txp_max_tx_size_set()
2704 val = mvpp2_read(port->priv, in mvpp2_txp_max_tx_size_set()
2712 mvpp2_write(port->priv, in mvpp2_txp_max_tx_size_set()
2719 /* Set the number of non-occupied descriptors threshold */
2725 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_set_rxq_free_tresh()
2727 val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG); in mvpp2_set_rxq_free_tresh()
2730 mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val); in mvpp2_set_rxq_free_tresh()
2739 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_rx_pkts_coal_set()
2741 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) in mvpp2_rx_pkts_coal_set()
2742 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; in mvpp2_rx_pkts_coal_set()
2744 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rx_pkts_coal_set()
2745 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG, in mvpp2_rx_pkts_coal_set()
2746 rxq->pkts_coal); in mvpp2_rx_pkts_coal_set()
2758 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) in mvpp2_tx_pkts_coal_set()
2759 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; in mvpp2_tx_pkts_coal_set()
2761 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); in mvpp2_tx_pkts_coal_set()
2762 /* PKT-coalescing registers are per-queue + per-thread */ in mvpp2_tx_pkts_coal_set()
2764 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_tx_pkts_coal_set()
2765 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); in mvpp2_tx_pkts_coal_set()
2791 unsigned long freq = port->priv->tclk; in mvpp2_rx_time_coal_set()
2792 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); in mvpp2_rx_time_coal_set()
2795 rxq->time_coal = in mvpp2_rx_time_coal_set()
2798 /* re-evaluate to get actual register value */ in mvpp2_rx_time_coal_set()
2799 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); in mvpp2_rx_time_coal_set()
2802 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); in mvpp2_rx_time_coal_set()
2807 unsigned long freq = port->priv->tclk; in mvpp2_tx_time_coal_set()
2808 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); in mvpp2_tx_time_coal_set()
2811 port->tx_time_coal = in mvpp2_tx_time_coal_set()
2814 /* re-evaluate to get actual register value */ in mvpp2_tx_time_coal_set()
2815 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); in mvpp2_tx_time_coal_set()
2818 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); in mvpp2_tx_time_coal_set()
2835 txq_pcpu->buffs + txq_pcpu->txq_get_index; in mvpp2_txq_bufs_free()
2837 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) && in mvpp2_txq_bufs_free()
2838 tx_buf->type != MVPP2_TYPE_XDP_TX) in mvpp2_txq_bufs_free()
2839 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, in mvpp2_txq_bufs_free()
2840 tx_buf->size, DMA_TO_DEVICE); in mvpp2_txq_bufs_free()
2841 if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb) in mvpp2_txq_bufs_free()
2842 dev_kfree_skb_any(tx_buf->skb); in mvpp2_txq_bufs_free()
2843 else if (tx_buf->type == MVPP2_TYPE_XDP_TX || in mvpp2_txq_bufs_free()
2844 tx_buf->type == MVPP2_TYPE_XDP_NDO) in mvpp2_txq_bufs_free()
2845 xdp_return_frame_bulk(tx_buf->xdpf, &bq); in mvpp2_txq_bufs_free()
2857 int queue = fls(cause) - 1; in mvpp2_get_rx_queue()
2859 return port->rxqs[queue]; in mvpp2_get_rx_queue()
2865 int queue = fls(cause) - 1; in mvpp2_get_tx_queue()
2867 return port->txqs[queue]; in mvpp2_get_tx_queue()
2874 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); in mvpp2_txq_done()
2877 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id())) in mvpp2_txq_done()
2878 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); in mvpp2_txq_done()
2885 txq_pcpu->count -= tx_done; in mvpp2_txq_done()
2888 if (txq_pcpu->count <= txq_pcpu->wake_threshold) in mvpp2_txq_done()
2904 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); in mvpp2_tx_done()
2906 if (txq_pcpu->count) { in mvpp2_tx_done()
2908 tx_todo += txq_pcpu->count; in mvpp2_tx_done()
2911 cause &= ~(1 << txq->log_id); in mvpp2_tx_done()
2926 aggr_txq->descs = dma_alloc_coherent(&pdev->dev, in mvpp2_aggr_txq_init()
2928 &aggr_txq->descs_dma, GFP_KERNEL); in mvpp2_aggr_txq_init()
2929 if (!aggr_txq->descs) in mvpp2_aggr_txq_init()
2930 return -ENOMEM; in mvpp2_aggr_txq_init()
2932 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; in mvpp2_aggr_txq_init()
2935 aggr_txq->next_desc_to_proc = mvpp2_read(priv, in mvpp2_aggr_txq_init()
2941 if (priv->hw_version == MVPP21) in mvpp2_aggr_txq_init()
2942 txq_dma = aggr_txq->descs_dma; in mvpp2_aggr_txq_init()
2944 txq_dma = aggr_txq->descs_dma >> in mvpp2_aggr_txq_init()
2958 struct mvpp2 *priv = port->priv; in mvpp2_rxq_init()
2963 rxq->size = port->rx_ring_size; in mvpp2_rxq_init()
2966 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, in mvpp2_rxq_init()
2967 rxq->size * MVPP2_DESC_ALIGNED_SIZE, in mvpp2_rxq_init()
2968 &rxq->descs_dma, GFP_KERNEL); in mvpp2_rxq_init()
2969 if (!rxq->descs) in mvpp2_rxq_init()
2970 return -ENOMEM; in mvpp2_rxq_init()
2972 rxq->last_desc = rxq->size - 1; in mvpp2_rxq_init()
2974 /* Zero occupied and non-occupied counters - direct access */ in mvpp2_rxq_init()
2975 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_init()
2977 /* Set Rx descriptors queue starting address - indirect access */ in mvpp2_rxq_init()
2978 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_rxq_init()
2979 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_init()
2980 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_init()
2981 rxq_dma = rxq->descs_dma; in mvpp2_rxq_init()
2983 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; in mvpp2_rxq_init()
2984 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); in mvpp2_rxq_init()
2985 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); in mvpp2_rxq_init()
2986 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0); in mvpp2_rxq_init()
2990 mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM); in mvpp2_rxq_init()
3000 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); in mvpp2_rxq_init()
3002 if (priv->percpu_pools) { in mvpp2_rxq_init()
3003 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->logic_rxq, 0); in mvpp2_rxq_init()
3007 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->logic_rxq, 0); in mvpp2_rxq_init()
3012 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_short, in mvpp2_rxq_init()
3014 priv->page_pool[rxq->logic_rxq]); in mvpp2_rxq_init()
3018 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_long, in mvpp2_rxq_init()
3020 priv->page_pool[rxq->logic_rxq + in mvpp2_rxq_init()
3021 port->nrxqs]); in mvpp2_rxq_init()
3029 xdp_rxq_info_unreg_mem_model(&rxq->xdp_rxq_short); in mvpp2_rxq_init()
3031 xdp_rxq_info_unreg(&rxq->xdp_rxq_long); in mvpp2_rxq_init()
3033 xdp_rxq_info_unreg(&rxq->xdp_rxq_short); in mvpp2_rxq_init()
3035 dma_free_coherent(port->dev->dev.parent, in mvpp2_rxq_init()
3036 rxq->size * MVPP2_DESC_ALIGNED_SIZE, in mvpp2_rxq_init()
3037 rxq->descs, rxq->descs_dma); in mvpp2_rxq_init()
3047 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rxq_drop_pkts()
3063 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); in mvpp2_rxq_drop_pkts()
3072 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_short)) in mvpp2_rxq_deinit()
3073 xdp_rxq_info_unreg(&rxq->xdp_rxq_short); in mvpp2_rxq_deinit()
3075 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_long)) in mvpp2_rxq_deinit()
3076 xdp_rxq_info_unreg(&rxq->xdp_rxq_long); in mvpp2_rxq_deinit()
3080 if (rxq->descs) in mvpp2_rxq_deinit()
3081 dma_free_coherent(port->dev->dev.parent, in mvpp2_rxq_deinit()
3082 rxq->size * MVPP2_DESC_ALIGNED_SIZE, in mvpp2_rxq_deinit()
3083 rxq->descs, in mvpp2_rxq_deinit()
3084 rxq->descs_dma); in mvpp2_rxq_deinit()
3086 rxq->descs = NULL; in mvpp2_rxq_deinit()
3087 rxq->last_desc = 0; in mvpp2_rxq_deinit()
3088 rxq->next_desc_to_proc = 0; in mvpp2_rxq_deinit()
3089 rxq->descs_dma = 0; in mvpp2_rxq_deinit()
3094 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_deinit()
3095 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_rxq_deinit()
3096 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_deinit()
3097 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0); in mvpp2_rxq_deinit()
3098 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0); in mvpp2_rxq_deinit()
3111 txq->size = port->tx_ring_size; in mvpp2_txq_init()
3114 txq->descs = dma_alloc_coherent(port->dev->dev.parent, in mvpp2_txq_init()
3115 txq->size * MVPP2_DESC_ALIGNED_SIZE, in mvpp2_txq_init()
3116 &txq->descs_dma, GFP_KERNEL); in mvpp2_txq_init()
3117 if (!txq->descs) in mvpp2_txq_init()
3118 return -ENOMEM; in mvpp2_txq_init()
3120 txq->last_desc = txq->size - 1; in mvpp2_txq_init()
3122 /* Set Tx descriptors queue starting address - indirect access */ in mvpp2_txq_init()
3123 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_txq_init()
3124 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_init()
3125 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, in mvpp2_txq_init()
3126 txq->descs_dma); in mvpp2_txq_init()
3127 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, in mvpp2_txq_init()
3128 txq->size & MVPP2_TXQ_DESC_SIZE_MASK); in mvpp2_txq_init()
3129 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0); in mvpp2_txq_init()
3130 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG, in mvpp2_txq_init()
3131 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); in mvpp2_txq_init()
3132 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_init()
3134 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); in mvpp2_txq_init()
3142 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + in mvpp2_txq_init()
3143 (txq->log_id * desc_per_txq); in mvpp2_txq_init()
3145 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, in mvpp2_txq_init()
3150 /* WRR / EJP configuration - indirect access */ in mvpp2_txq_init()
3152 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
3154 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); in mvpp2_txq_init()
3158 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); in mvpp2_txq_init()
3161 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), in mvpp2_txq_init()
3164 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_txq_init()
3165 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); in mvpp2_txq_init()
3166 txq_pcpu->size = txq->size; in mvpp2_txq_init()
3167 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, in mvpp2_txq_init()
3168 sizeof(*txq_pcpu->buffs), in mvpp2_txq_init()
3170 if (!txq_pcpu->buffs) in mvpp2_txq_init()
3171 return -ENOMEM; in mvpp2_txq_init()
3173 txq_pcpu->count = 0; in mvpp2_txq_init()
3174 txq_pcpu->reserved_num = 0; in mvpp2_txq_init()
3175 txq_pcpu->txq_put_index = 0; in mvpp2_txq_init()
3176 txq_pcpu->txq_get_index = 0; in mvpp2_txq_init()
3177 txq_pcpu->tso_headers = NULL; in mvpp2_txq_init()
3179 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; in mvpp2_txq_init()
3180 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; in mvpp2_txq_init()
3182 txq_pcpu->tso_headers = in mvpp2_txq_init()
3183 dma_alloc_coherent(port->dev->dev.parent, in mvpp2_txq_init()
3184 txq_pcpu->size * TSO_HEADER_SIZE, in mvpp2_txq_init()
3185 &txq_pcpu->tso_headers_dma, in mvpp2_txq_init()
3187 if (!txq_pcpu->tso_headers) in mvpp2_txq_init()
3188 return -ENOMEM; in mvpp2_txq_init()
3201 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_txq_deinit()
3202 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); in mvpp2_txq_deinit()
3203 kfree(txq_pcpu->buffs); in mvpp2_txq_deinit()
3205 if (txq_pcpu->tso_headers) in mvpp2_txq_deinit()
3206 dma_free_coherent(port->dev->dev.parent, in mvpp2_txq_deinit()
3207 txq_pcpu->size * TSO_HEADER_SIZE, in mvpp2_txq_deinit()
3208 txq_pcpu->tso_headers, in mvpp2_txq_deinit()
3209 txq_pcpu->tso_headers_dma); in mvpp2_txq_deinit()
3211 txq_pcpu->tso_headers = NULL; in mvpp2_txq_deinit()
3214 if (txq->descs) in mvpp2_txq_deinit()
3215 dma_free_coherent(port->dev->dev.parent, in mvpp2_txq_deinit()
3216 txq->size * MVPP2_DESC_ALIGNED_SIZE, in mvpp2_txq_deinit()
3217 txq->descs, txq->descs_dma); in mvpp2_txq_deinit()
3219 txq->descs = NULL; in mvpp2_txq_deinit()
3220 txq->last_desc = 0; in mvpp2_txq_deinit()
3221 txq->next_desc_to_proc = 0; in mvpp2_txq_deinit()
3222 txq->descs_dma = 0; in mvpp2_txq_deinit()
3225 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0); in mvpp2_txq_deinit()
3228 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_txq_deinit()
3229 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_deinit()
3230 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0); in mvpp2_txq_deinit()
3231 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0); in mvpp2_txq_deinit()
3240 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_txq_clean()
3243 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_clean()
3244 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); in mvpp2_txq_clean()
3246 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
3254 netdev_warn(port->dev, in mvpp2_txq_clean()
3256 port->id, txq->log_id); in mvpp2_txq_clean()
3262 pending = mvpp2_thread_read(port->priv, thread, in mvpp2_txq_clean()
3268 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
3271 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_txq_clean()
3272 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); in mvpp2_txq_clean()
3275 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); in mvpp2_txq_clean()
3278 txq_pcpu->count = 0; in mvpp2_txq_clean()
3279 txq_pcpu->txq_put_index = 0; in mvpp2_txq_clean()
3280 txq_pcpu->txq_get_index = 0; in mvpp2_txq_clean()
3291 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); in mvpp2_cleanup_txqs()
3294 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
3295 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
3297 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_cleanup_txqs()
3298 txq = port->txqs[queue]; in mvpp2_cleanup_txqs()
3305 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
3306 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
3314 for (queue = 0; queue < port->nrxqs; queue++) in mvpp2_cleanup_rxqs()
3315 mvpp2_rxq_deinit(port, port->rxqs[queue]); in mvpp2_cleanup_rxqs()
3317 if (port->tx_fc) in mvpp2_cleanup_rxqs()
3326 for (queue = 0; queue < port->nrxqs; queue++) { in mvpp2_setup_rxqs()
3327 err = mvpp2_rxq_init(port, port->rxqs[queue]); in mvpp2_setup_rxqs()
3332 if (port->tx_fc) in mvpp2_setup_rxqs()
3348 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_setup_txqs()
3349 txq = port->txqs[queue]; in mvpp2_setup_txqs()
3356 netif_set_xps_queue(port->dev, cpumask_of(queue), queue); in mvpp2_setup_txqs()
3359 if (port->has_tx_irqs) { in mvpp2_setup_txqs()
3361 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_setup_txqs()
3362 txq = port->txqs[queue]; in mvpp2_setup_txqs()
3375 /* The callback for per-port interrupt */
3382 napi_schedule(&qv->napi); in mvpp2_isr()
3396 ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); in mvpp2_isr_handle_ptp_queue()
3398 ptp_q += MVPP22_PTP_TX_Q1_R0 - MVPP22_PTP_TX_Q0_R0; in mvpp2_isr_handle_ptp_queue()
3400 queue = &port->tx_hwtstamp_queue[nq]; in mvpp2_isr_handle_ptp_queue()
3412 skb = queue->skb[id]; in mvpp2_isr_handle_ptp_queue()
3413 queue->skb[id] = NULL; in mvpp2_isr_handle_ptp_queue()
3417 mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps); in mvpp2_isr_handle_ptp_queue()
3429 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); in mvpp2_isr_handle_ptp()
3440 struct net_device *dev = port->dev; in mvpp2_isr_handle_link()
3442 if (port->phylink) { in mvpp2_isr_handle_link()
3472 val = readl(port->base + MVPP22_XLG_INT_STAT); in mvpp2_isr_handle_xlg()
3474 val = readl(port->base + MVPP22_XLG_STATUS); in mvpp2_isr_handle_xlg()
3476 mvpp2_isr_handle_link(port, &port->pcs_xlg, link); in mvpp2_isr_handle_xlg()
3485 if (phy_interface_mode_is_rgmii(port->phy_interface) || in mvpp2_isr_handle_gmac_internal()
3486 phy_interface_mode_is_8023z(port->phy_interface) || in mvpp2_isr_handle_gmac_internal()
3487 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { in mvpp2_isr_handle_gmac_internal()
3488 val = readl(port->base + MVPP22_GMAC_INT_STAT); in mvpp2_isr_handle_gmac_internal()
3490 val = readl(port->base + MVPP2_GMAC_STATUS0); in mvpp2_isr_handle_gmac_internal()
3492 mvpp2_isr_handle_link(port, &port->pcs_gmac, link); in mvpp2_isr_handle_gmac_internal()
3497 /* Per-port interrupt for link status changes */
3506 mvpp2_is_xlg(port->phy_interface)) { in mvpp2_port_isr()
3508 val = readl(port->base + MVPP22_XLG_EXT_INT_STAT); in mvpp2_port_isr()
3517 val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT); in mvpp2_port_isr()
3536 dev = port_pcpu->dev; in mvpp2_hr_timer_cb()
3541 port_pcpu->timer_scheduled = false; in mvpp2_hr_timer_cb()
3545 cause = (1 << port->ntxqs) - 1; in mvpp2_hr_timer_cb()
3547 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); in mvpp2_hr_timer_cb()
3550 if (tx_todo && !port_pcpu->timer_scheduled) { in mvpp2_hr_timer_cb()
3551 port_pcpu->timer_scheduled = true; in mvpp2_hr_timer_cb()
3552 hrtimer_forward_now(&port_pcpu->tx_done_timer, in mvpp2_hr_timer_cb()
3582 netdev_err(port->dev, in mvpp2_rx_error()
3613 return -ENOMEM; in mvpp2_rx_refill()
3623 if (skb->ip_summed == CHECKSUM_PARTIAL) { in mvpp2_skb_tx_csum()
3632 ip_hdr_len = ip4h->ihl; in mvpp2_skb_tx_csum()
3633 l4_proto = ip4h->protocol; in mvpp2_skb_tx_csum()
3640 l4_proto = ip6h->nexthdr; in mvpp2_skb_tx_csum()
3654 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_xdp_finish_tx()
3660 txq = port->txqs[txq_id]; in mvpp2_xdp_finish_tx()
3661 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); in mvpp2_xdp_finish_tx()
3662 nq = netdev_get_tx_queue(port->dev, txq_id); in mvpp2_xdp_finish_tx()
3663 aggr_txq = &port->priv->aggr_txqs[thread]; in mvpp2_xdp_finish_tx()
3665 txq_pcpu->reserved_num -= nxmit; in mvpp2_xdp_finish_tx()
3666 txq_pcpu->count += nxmit; in mvpp2_xdp_finish_tx()
3667 aggr_txq->count += nxmit; in mvpp2_xdp_finish_tx()
3673 if (txq_pcpu->count >= txq_pcpu->stop_threshold) in mvpp2_xdp_finish_tx()
3677 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) in mvpp2_xdp_finish_tx()
3685 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_xdp_submit_frame()
3696 txq = port->txqs[txq_id]; in mvpp2_xdp_submit_frame()
3697 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); in mvpp2_xdp_submit_frame()
3698 aggr_txq = &port->priv->aggr_txqs[thread]; in mvpp2_xdp_submit_frame()
3709 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_xdp_submit_frame()
3710 mvpp2_txdesc_size_set(port, tx_desc, xdpf->len); in mvpp2_xdp_submit_frame()
3714 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data, in mvpp2_xdp_submit_frame()
3715 xdpf->len, DMA_TO_DEVICE); in mvpp2_xdp_submit_frame()
3717 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { in mvpp2_xdp_submit_frame()
3726 struct page *page = virt_to_page(xdpf->data); in mvpp2_xdp_submit_frame()
3729 sizeof(*xdpf) + xdpf->headroom; in mvpp2_xdp_submit_frame()
3730 dma_sync_single_for_device(port->dev->dev.parent, dma_addr, in mvpp2_xdp_submit_frame()
3731 xdpf->len, DMA_BIDIRECTIONAL); in mvpp2_xdp_submit_frame()
3748 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); in mvpp2_xdp_xmit_back()
3760 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); in mvpp2_xdp_xmit_back()
3764 u64_stats_update_begin(&stats->syncp); in mvpp2_xdp_xmit_back()
3765 stats->tx_bytes += xdpf->len; in mvpp2_xdp_xmit_back()
3766 stats->tx_packets++; in mvpp2_xdp_xmit_back()
3767 stats->xdp_tx++; in mvpp2_xdp_xmit_back()
3768 u64_stats_update_end(&stats->syncp); in mvpp2_xdp_xmit_back()
3770 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len); in mvpp2_xdp_xmit_back()
3772 u64_stats_update_begin(&stats->syncp); in mvpp2_xdp_xmit_back()
3773 stats->xdp_tx_err++; in mvpp2_xdp_xmit_back()
3774 u64_stats_update_end(&stats->syncp); in mvpp2_xdp_xmit_back()
3790 if (unlikely(test_bit(0, &port->state))) in mvpp2_xdp_xmit()
3791 return -ENETDOWN; in mvpp2_xdp_xmit()
3794 return -EINVAL; in mvpp2_xdp_xmit()
3799 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); in mvpp2_xdp_xmit()
3806 nxmit_byte += frames[i]->len; in mvpp2_xdp_xmit()
3813 stats = this_cpu_ptr(port->stats); in mvpp2_xdp_xmit()
3814 u64_stats_update_begin(&stats->syncp); in mvpp2_xdp_xmit()
3815 stats->tx_bytes += nxmit_byte; in mvpp2_xdp_xmit()
3816 stats->tx_packets += nxmit; in mvpp2_xdp_xmit()
3817 stats->xdp_xmit += nxmit; in mvpp2_xdp_xmit()
3818 stats->xdp_xmit_err += num_frame - nxmit; in mvpp2_xdp_xmit()
3819 u64_stats_update_end(&stats->syncp); in mvpp2_xdp_xmit()
3833 len = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM; in mvpp2_run_xdp()
3837 sync = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM; in mvpp2_run_xdp()
3842 stats->xdp_pass++; in mvpp2_run_xdp()
3846 err = xdp_do_redirect(port->dev, xdp, prog); in mvpp2_run_xdp()
3849 page = virt_to_head_page(xdp->data); in mvpp2_run_xdp()
3853 stats->xdp_redirect++; in mvpp2_run_xdp()
3859 page = virt_to_head_page(xdp->data); in mvpp2_run_xdp()
3864 bpf_warn_invalid_xdp_action(port->dev, prog, act); in mvpp2_run_xdp()
3867 trace_xdp_exception(port->dev, prog, act); in mvpp2_run_xdp()
3870 page = virt_to_head_page(xdp->data); in mvpp2_run_xdp()
3873 stats->xdp_drop++; in mvpp2_run_xdp()
3893 phys_addr_next = le32_to_cpu(buff_hdr->next_phys_addr); in mvpp2_buff_hdr_pool_put()
3894 dma_addr_next = le32_to_cpu(buff_hdr->next_dma_addr); in mvpp2_buff_hdr_pool_put()
3896 if (port->priv->hw_version >= MVPP22) { in mvpp2_buff_hdr_pool_put()
3897 phys_addr_next |= ((u64)buff_hdr->next_phys_addr_high << 32); in mvpp2_buff_hdr_pool_put()
3898 dma_addr_next |= ((u64)buff_hdr->next_dma_addr_high << 32); in mvpp2_buff_hdr_pool_put()
3906 } while (!MVPP2_B_HDR_INFO_IS_LAST(le16_to_cpu(buff_hdr->info))); in mvpp2_buff_hdr_pool_put()
3913 struct net_device *dev = port->dev; in mvpp2_rx()
3922 xdp_prog = READ_ONCE(port->xdp_prog); in mvpp2_rx()
3924 /* Get number of received packets and clamp the to-do */ in mvpp2_rx()
3925 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rx()
3950 rx_bytes -= MVPP2_MH_SIZE; in mvpp2_rx()
3955 bm_pool = &port->priv->bm_pools[pool]; in mvpp2_rx()
3957 if (port->priv->percpu_pools) { in mvpp2_rx()
3958 pp = port->priv->page_pool[pool]; in mvpp2_rx()
3964 dma_sync_single_for_cpu(dev->dev.parent, dma_addr, in mvpp2_rx()
3983 if (bm_pool->frag_size > PAGE_SIZE) in mvpp2_rx()
3986 frag_size = bm_pool->frag_size; in mvpp2_rx()
3991 if (bm_pool->pkt_size == MVPP2_BM_SHORT_PKT_SIZE) in mvpp2_rx()
3992 xdp_rxq = &rxq->xdp_rxq_short; in mvpp2_rx()
3994 xdp_rxq = &rxq->xdp_rxq_long; in mvpp2_rx()
4007 netdev_err(port->dev, "failed to refill BM pools\n"); in mvpp2_rx()
4022 netdev_warn(port->dev, "skb build failed\n"); in mvpp2_rx()
4030 timestamp = le32_to_cpu(rx_desc->pp22.timestamp); in mvpp2_rx()
4031 mvpp22_tai_tstamp(port->priv->tai, timestamp, in mvpp2_rx()
4037 netdev_err(port->dev, "failed to refill BM pools\n"); in mvpp2_rx()
4045 dma_unmap_single_attrs(dev->dev.parent, dma_addr, in mvpp2_rx()
4046 bm_pool->buf_size, DMA_FROM_DEVICE, in mvpp2_rx()
4054 skb->ip_summed = mvpp2_rx_csum(port, rx_status); in mvpp2_rx()
4055 skb->protocol = eth_type_trans(skb, dev); in mvpp2_rx()
4061 dev->stats.rx_errors++; in mvpp2_rx()
4074 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); in mvpp2_rx()
4076 u64_stats_update_begin(&stats->syncp); in mvpp2_rx()
4077 stats->rx_packets += ps.rx_packets; in mvpp2_rx()
4078 stats->rx_bytes += ps.rx_bytes; in mvpp2_rx()
4080 stats->xdp_redirect += ps.xdp_redirect; in mvpp2_rx()
4081 stats->xdp_pass += ps.xdp_pass; in mvpp2_rx()
4082 stats->xdp_drop += ps.xdp_drop; in mvpp2_rx()
4083 u64_stats_update_end(&stats->syncp); in mvpp2_rx()
4088 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); in mvpp2_rx()
4097 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in tx_desc_unmap_put()
4098 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); in tx_desc_unmap_put()
4105 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, in tx_desc_unmap_put()
4114 if (port->priv->hw_version >= MVPP22) in mvpp2_txdesc_clear_ptp()
4115 desc->pp22.ptp_descriptor &= in mvpp2_txdesc_clear_ptp()
4128 if (port->priv->hw_version == MVPP21 || in mvpp2_tx_hw_tstamp()
4129 port->tx_hwtstamp_type == HWTSTAMP_TX_OFF) in mvpp2_tx_hw_tstamp()
4140 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in mvpp2_tx_hw_tstamp()
4144 queue = &port->tx_hwtstamp_queue[0]; in mvpp2_tx_hw_tstamp()
4153 mtype = hdr->tsmt & 15; in mvpp2_tx_hw_tstamp()
4157 queue = &port->tx_hwtstamp_queue[1]; in mvpp2_tx_hw_tstamp()
4163 i = queue->next; in mvpp2_tx_hw_tstamp()
4164 queue->next = (i + 1) & 31; in mvpp2_tx_hw_tstamp()
4165 if (queue->skb[i]) in mvpp2_tx_hw_tstamp()
4166 dev_kfree_skb_any(queue->skb[i]); in mvpp2_tx_hw_tstamp()
4167 queue->skb[i] = skb_get(skb); in mvpp2_tx_hw_tstamp()
4172 * 3:0 - PTPAction in mvpp2_tx_hw_tstamp()
4173 * 6:4 - PTPPacketFormat in mvpp2_tx_hw_tstamp()
4174 * 7 - PTP_CF_WraparoundCheckEn in mvpp2_tx_hw_tstamp()
4175 * 9:8 - IngressTimestampSeconds[1:0] in mvpp2_tx_hw_tstamp()
4176 * 10 - Reserved in mvpp2_tx_hw_tstamp()
4177 * 11 - MACTimestampingEn in mvpp2_tx_hw_tstamp()
4178 * 17:12 - PTP_TimestampQueueEntryID[5:0] in mvpp2_tx_hw_tstamp()
4179 * 18 - PTPTimestampQueueSelect in mvpp2_tx_hw_tstamp()
4180 * 19 - UDPChecksumUpdateEn in mvpp2_tx_hw_tstamp()
4181 * 27:20 - TimestampOffset in mvpp2_tx_hw_tstamp()
4182 * PTP, NTPTransmit, OWAMP/TWAMP - L3 to PTP header in mvpp2_tx_hw_tstamp()
4183 * NTPTs, Y.1731 - L3 to timestamp entry in mvpp2_tx_hw_tstamp()
4184 * 35:28 - UDP Checksum Offset in mvpp2_tx_hw_tstamp()
4188 tx_desc->pp22.ptp_descriptor &= in mvpp2_tx_hw_tstamp()
4190 tx_desc->pp22.ptp_descriptor |= in mvpp2_tx_hw_tstamp()
4192 tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL); in mvpp2_tx_hw_tstamp()
4193 tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40); in mvpp2_tx_hw_tstamp()
4203 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_tx_frag_process()
4204 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); in mvpp2_tx_frag_process()
4209 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in mvpp2_tx_frag_process()
4210 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in mvpp2_tx_frag_process()
4215 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_tx_frag_process()
4218 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, in mvpp2_tx_frag_process()
4221 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { in mvpp2_tx_frag_process()
4228 if (i == (skb_shinfo(skb)->nr_frags - 1)) { in mvpp2_tx_frag_process()
4245 for (i = i - 1; i >= 0; i--) { in mvpp2_tx_frag_process()
4246 tx_desc = txq->descs + i; in mvpp2_tx_frag_process()
4250 return -ENOMEM; in mvpp2_tx_frag_process()
4265 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_tso_put_hdr()
4268 addr = txq_pcpu->tso_headers_dma + in mvpp2_tso_put_hdr()
4269 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; in mvpp2_tso_put_hdr()
4290 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_tso_put_data()
4293 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, in mvpp2_tso_put_data()
4295 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { in mvpp2_tso_put_data()
4297 return -ENOMEM; in mvpp2_tso_put_data()
4333 len = skb->len - hdr_sz; in mvpp2_tx_tso()
4335 int left = min_t(int, skb_shinfo(skb)->gso_size, len); in mvpp2_tx_tso()
4336 char *hdr = txq_pcpu->tso_headers + in mvpp2_tx_tso()
4337 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; in mvpp2_tx_tso()
4339 len -= left; in mvpp2_tx_tso()
4347 left -= sz; in mvpp2_tx_tso()
4360 for (i = descs - 1; i >= 0; i--) { in mvpp2_tx_tso()
4361 struct mvpp2_tx_desc *tx_desc = txq->descs + i; in mvpp2_tx_tso()
4381 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_tx()
4384 txq = port->txqs[txq_id]; in mvpp2_tx()
4385 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); in mvpp2_tx()
4386 aggr_txq = &port->priv->aggr_txqs[thread]; in mvpp2_tx()
4388 if (test_bit(thread, &port->priv->lock_map)) in mvpp2_tx()
4389 spin_lock_irqsave(&port->tx_lock[thread], flags); in mvpp2_tx()
4395 frags = skb_shinfo(skb)->nr_frags + 1; in mvpp2_tx()
4406 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) || in mvpp2_tx()
4409 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_tx()
4412 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, in mvpp2_tx()
4414 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { in mvpp2_tx()
4444 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread); in mvpp2_tx()
4447 txq_pcpu->reserved_num -= frags; in mvpp2_tx()
4448 txq_pcpu->count += frags; in mvpp2_tx()
4449 aggr_txq->count += frags; in mvpp2_tx()
4455 if (txq_pcpu->count >= txq_pcpu->stop_threshold) in mvpp2_tx()
4458 u64_stats_update_begin(&stats->syncp); in mvpp2_tx()
4459 stats->tx_packets++; in mvpp2_tx()
4460 stats->tx_bytes += skb->len; in mvpp2_tx()
4461 u64_stats_update_end(&stats->syncp); in mvpp2_tx()
4463 dev->stats.tx_dropped++; in mvpp2_tx()
4468 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) in mvpp2_tx()
4472 if (!port->has_tx_irqs && txq_pcpu->count <= frags && in mvpp2_tx()
4473 txq_pcpu->count > 0) { in mvpp2_tx()
4474 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread); in mvpp2_tx()
4476 if (!port_pcpu->timer_scheduled) { in mvpp2_tx()
4477 port_pcpu->timer_scheduled = true; in mvpp2_tx()
4478 hrtimer_start(&port_pcpu->tx_done_timer, in mvpp2_tx()
4484 if (test_bit(thread, &port->priv->lock_map)) in mvpp2_tx()
4485 spin_unlock_irqrestore(&port->tx_lock[thread], flags); in mvpp2_tx()
4504 struct mvpp2_port *port = netdev_priv(napi->dev); in mvpp2_poll()
4506 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_poll()
4512 * Bits 0-15: each bit indicates received packets on the Rx queue in mvpp2_poll()
4515 * Bits 16-23: each bit indicates transmitted packets on the Tx queue in mvpp2_poll()
4520 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id, in mvpp2_poll()
4521 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); in mvpp2_poll()
4525 mvpp2_cause_error(port->dev, cause_misc); in mvpp2_poll()
4528 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); in mvpp2_poll()
4529 mvpp2_thread_write(port->priv, thread, in mvpp2_poll()
4530 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), in mvpp2_poll()
4534 if (port->has_tx_irqs) { in mvpp2_poll()
4538 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); in mvpp2_poll()
4544 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); in mvpp2_poll()
4545 cause_rx <<= qv->first_rxq; in mvpp2_poll()
4546 cause_rx |= qv->pending_cause_rx; in mvpp2_poll()
4557 budget -= count; in mvpp2_poll()
4563 cause_rx &= ~(1 << rxq->logic_rxq); in mvpp2_poll()
4573 qv->pending_cause_rx = cause_rx; in mvpp2_poll()
4597 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); in mvpp22_mode_reconfigure()
4605 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); in mvpp22_mode_reconfigure()
4621 for (i = 0; i < port->nqvecs; i++) in mvpp2_start_dev()
4622 napi_enable(&port->qvecs[i].napi); in mvpp2_start_dev()
4627 if (port->priv->hw_version >= MVPP22) in mvpp2_start_dev()
4628 mvpp22_mode_reconfigure(port, port->phy_interface); in mvpp2_start_dev()
4630 if (port->phylink) { in mvpp2_start_dev()
4631 phylink_start(port->phylink); in mvpp2_start_dev()
4636 netif_tx_start_all_queues(port->dev); in mvpp2_start_dev()
4638 clear_bit(0, &port->state); in mvpp2_start_dev()
4646 set_bit(0, &port->state); in mvpp2_stop_dev()
4651 for (i = 0; i < port->nqvecs; i++) in mvpp2_stop_dev()
4652 napi_disable(&port->qvecs[i].napi); in mvpp2_stop_dev()
4654 if (port->phylink) in mvpp2_stop_dev()
4655 phylink_stop(port->phylink); in mvpp2_stop_dev()
4656 phy_power_off(port->comphy); in mvpp2_stop_dev()
4662 u16 new_rx_pending = ring->rx_pending; in mvpp2_check_ringparam_valid()
4663 u16 new_tx_pending = ring->tx_pending; in mvpp2_check_ringparam_valid()
4665 if (ring->rx_pending == 0 || ring->tx_pending == 0) in mvpp2_check_ringparam_valid()
4666 return -EINVAL; in mvpp2_check_ringparam_valid()
4668 if (ring->rx_pending > MVPP2_MAX_RXD_MAX) in mvpp2_check_ringparam_valid()
4670 else if (ring->rx_pending < MSS_THRESHOLD_START) in mvpp2_check_ringparam_valid()
4672 else if (!IS_ALIGNED(ring->rx_pending, 16)) in mvpp2_check_ringparam_valid()
4673 new_rx_pending = ALIGN(ring->rx_pending, 16); in mvpp2_check_ringparam_valid()
4675 if (ring->tx_pending > MVPP2_MAX_TXD_MAX) in mvpp2_check_ringparam_valid()
4677 else if (!IS_ALIGNED(ring->tx_pending, 32)) in mvpp2_check_ringparam_valid()
4678 new_tx_pending = ALIGN(ring->tx_pending, 32); in mvpp2_check_ringparam_valid()
4686 if (ring->rx_pending != new_rx_pending) { in mvpp2_check_ringparam_valid()
4688 ring->rx_pending, new_rx_pending); in mvpp2_check_ringparam_valid()
4689 ring->rx_pending = new_rx_pending; in mvpp2_check_ringparam_valid()
4692 if (ring->tx_pending != new_tx_pending) { in mvpp2_check_ringparam_valid()
4694 ring->tx_pending, new_tx_pending); in mvpp2_check_ringparam_valid()
4695 ring->tx_pending = new_tx_pending; in mvpp2_check_ringparam_valid()
4705 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp21_get_mac_address()
4706 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); in mvpp21_get_mac_address()
4707 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); in mvpp21_get_mac_address()
4720 for (i = 0; i < port->nqvecs; i++) { in mvpp2_irqs_init()
4721 struct mvpp2_queue_vector *qv = port->qvecs + i; in mvpp2_irqs_init()
4723 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { in mvpp2_irqs_init()
4724 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL); in mvpp2_irqs_init()
4725 if (!qv->mask) { in mvpp2_irqs_init()
4726 err = -ENOMEM; in mvpp2_irqs_init()
4730 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); in mvpp2_irqs_init()
4733 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); in mvpp2_irqs_init()
4737 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { in mvpp2_irqs_init()
4741 if (mvpp2_cpu_to_thread(port->priv, cpu) == in mvpp2_irqs_init()
4742 qv->sw_thread_id) in mvpp2_irqs_init()
4743 cpumask_set_cpu(cpu, qv->mask); in mvpp2_irqs_init()
4746 irq_set_affinity_hint(qv->irq, qv->mask); in mvpp2_irqs_init()
4752 for (i = 0; i < port->nqvecs; i++) { in mvpp2_irqs_init()
4753 struct mvpp2_queue_vector *qv = port->qvecs + i; in mvpp2_irqs_init()
4755 irq_set_affinity_hint(qv->irq, NULL); in mvpp2_irqs_init()
4756 kfree(qv->mask); in mvpp2_irqs_init()
4757 qv->mask = NULL; in mvpp2_irqs_init()
4758 free_irq(qv->irq, qv); in mvpp2_irqs_init()
4768 for (i = 0; i < port->nqvecs; i++) { in mvpp2_irqs_deinit()
4769 struct mvpp2_queue_vector *qv = port->qvecs + i; in mvpp2_irqs_deinit()
4771 irq_set_affinity_hint(qv->irq, NULL); in mvpp2_irqs_deinit()
4772 kfree(qv->mask); in mvpp2_irqs_deinit()
4773 qv->mask = NULL; in mvpp2_irqs_deinit()
4774 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); in mvpp2_irqs_deinit()
4775 free_irq(qv->irq, qv); in mvpp2_irqs_deinit()
4782 !(port->flags & MVPP2_F_LOOPBACK); in mvpp22_rss_is_supported()
4788 struct mvpp2 *priv = port->priv; in mvpp2_open()
4799 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); in mvpp2_open()
4804 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); in mvpp2_open()
4818 netdev_err(port->dev, "cannot allocate Rx queues\n"); in mvpp2_open()
4824 netdev_err(port->dev, "cannot allocate Tx queues\n"); in mvpp2_open()
4830 netdev_err(port->dev, "cannot init IRQs\n"); in mvpp2_open()
4834 if (port->phylink) { in mvpp2_open()
4835 err = phylink_fwnode_phy_connect(port->phylink, port->fwnode, 0); in mvpp2_open()
4837 netdev_err(port->dev, "could not attach PHY (%d)\n", in mvpp2_open()
4845 if (priv->hw_version >= MVPP22 && port->port_irq) { in mvpp2_open()
4846 err = request_irq(port->port_irq, mvpp2_port_isr, 0, in mvpp2_open()
4847 dev->name, port); in mvpp2_open()
4849 netdev_err(port->dev, in mvpp2_open()
4851 port->port_irq); in mvpp2_open()
4858 netif_carrier_off(port->dev); in mvpp2_open()
4862 port->port_irq = 0; in mvpp2_open()
4866 netdev_err(port->dev, in mvpp2_open()
4868 err = -ENOENT; in mvpp2_open()
4879 queue_delayed_work(priv->stats_queue, &port->stats_work, in mvpp2_open()
4905 if (port->phylink) in mvpp2_stop()
4906 phylink_disconnect_phy(port->phylink); in mvpp2_stop()
4907 if (port->port_irq) in mvpp2_stop()
4908 free_irq(port->port_irq, port); in mvpp2_stop()
4911 if (!port->has_tx_irqs) { in mvpp2_stop()
4912 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_stop()
4913 port_pcpu = per_cpu_ptr(port->pcpu, thread); in mvpp2_stop()
4915 hrtimer_cancel(&port_pcpu->tx_done_timer); in mvpp2_stop()
4916 port_pcpu->timer_scheduled = false; in mvpp2_stop()
4922 cancel_delayed_work_sync(&port->stats_work); in mvpp2_stop()
4937 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); in mvpp2_prs_mac_da_accept_list()
4947 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) in mvpp2_set_rx_promisc()
4952 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_promisc()
4955 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_promisc()
4966 if (dev->flags & IFF_PROMISC) { in mvpp2_set_rx_mode()
4974 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) in mvpp2_set_rx_mode()
4975 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_mode()
4978 if (dev->flags & IFF_ALLMULTI) { in mvpp2_set_rx_mode()
4979 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_mode()
4985 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) in mvpp2_set_rx_mode()
4986 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_mode()
4995 if (!is_valid_ether_addr(addr->sa_data)) in mvpp2_set_mac_address()
4996 return -EADDRNOTAVAIL; in mvpp2_set_mac_address()
4998 err = mvpp2_prs_update_mac_da(dev, addr->sa_data); in mvpp2_set_mac_address()
5001 mvpp2_prs_update_mac_da(dev, dev->dev_addr); in mvpp2_set_mac_address()
5012 bool change_percpu = (percpu != priv->percpu_pools); in mvpp2_bm_switch_buffers()
5017 for (i = 0; i < priv->port_count; i++) { in mvpp2_bm_switch_buffers()
5018 port = priv->port_list[i]; in mvpp2_bm_switch_buffers()
5019 status[i] = netif_running(port->dev); in mvpp2_bm_switch_buffers()
5021 mvpp2_stop(port->dev); in mvpp2_bm_switch_buffers()
5025 if (priv->percpu_pools) in mvpp2_bm_switch_buffers()
5026 numbufs = port->nrxqs * 2; in mvpp2_bm_switch_buffers()
5032 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]); in mvpp2_bm_switch_buffers()
5034 devm_kfree(port->dev->dev.parent, priv->bm_pools); in mvpp2_bm_switch_buffers()
5035 priv->percpu_pools = percpu; in mvpp2_bm_switch_buffers()
5036 mvpp2_bm_init(port->dev->dev.parent, priv); in mvpp2_bm_switch_buffers()
5038 for (i = 0; i < priv->port_count; i++) { in mvpp2_bm_switch_buffers()
5039 port = priv->port_list[i]; in mvpp2_bm_switch_buffers()
5040 if (percpu && port->ntxqs >= num_possible_cpus() * 2) in mvpp2_bm_switch_buffers()
5041 xdp_set_features_flag(port->dev, in mvpp2_bm_switch_buffers()
5046 xdp_clear_features_flag(port->dev); in mvpp2_bm_switch_buffers()
5050 mvpp2_open(port->dev); in mvpp2_bm_switch_buffers()
5063 struct mvpp2 *priv = port->priv; in mvpp2_change_mtu()
5072 if (port->xdp_prog && mtu > MVPP2_MAX_RX_BUF_SIZE) { in mvpp2_change_mtu()
5075 return -EINVAL; in mvpp2_change_mtu()
5079 if (priv->percpu_pools) { in mvpp2_change_mtu()
5087 for (i = 0; i < priv->port_count; i++) in mvpp2_change_mtu()
5088 if (priv->port_list[i] != port && in mvpp2_change_mtu()
5089 MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) > in mvpp2_change_mtu()
5097 dev_info(port->dev->dev.parent, in mvpp2_change_mtu()
5098 "all ports have a low MTU, switching to per-cpu buffers"); in mvpp2_change_mtu()
5110 mvpp2_bm_update_mtu(dev, dev->mtu); in mvpp2_change_mtu()
5112 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); in mvpp2_change_mtu()
5127 struct mvpp2 *priv = port->priv; in mvpp2_check_pagepool_dma()
5128 int err = -1, i; in mvpp2_check_pagepool_dma()
5130 if (!priv->percpu_pools) in mvpp2_check_pagepool_dma()
5133 if (!priv->page_pool[0]) in mvpp2_check_pagepool_dma()
5134 return -ENOMEM; in mvpp2_check_pagepool_dma()
5136 for (i = 0; i < priv->port_count; i++) { in mvpp2_check_pagepool_dma()
5137 port = priv->port_list[i]; in mvpp2_check_pagepool_dma()
5138 if (port->xdp_prog) { in mvpp2_check_pagepool_dma()
5145 if (priv->page_pool[0]->p.dma_dir != dma_dir) in mvpp2_check_pagepool_dma()
5165 cpu_stats = per_cpu_ptr(port->stats, cpu); in mvpp2_get_stats64()
5167 start = u64_stats_fetch_begin(&cpu_stats->syncp); in mvpp2_get_stats64()
5168 rx_packets = cpu_stats->rx_packets; in mvpp2_get_stats64()
5169 rx_bytes = cpu_stats->rx_bytes; in mvpp2_get_stats64()
5170 tx_packets = cpu_stats->tx_packets; in mvpp2_get_stats64()
5171 tx_bytes = cpu_stats->tx_bytes; in mvpp2_get_stats64()
5172 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start)); in mvpp2_get_stats64()
5174 stats->rx_packets += rx_packets; in mvpp2_get_stats64()
5175 stats->rx_bytes += rx_bytes; in mvpp2_get_stats64()
5176 stats->tx_packets += tx_packets; in mvpp2_get_stats64()
5177 stats->tx_bytes += tx_bytes; in mvpp2_get_stats64()
5180 stats->rx_errors = dev->stats.rx_errors; in mvpp2_get_stats64()
5181 stats->rx_dropped = dev->stats.rx_dropped; in mvpp2_get_stats64()
5182 stats->tx_dropped = dev->stats.tx_dropped; in mvpp2_get_stats64()
5191 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) in mvpp2_set_ts_config()
5192 return -EFAULT; in mvpp2_set_ts_config()
5196 return -ERANGE; in mvpp2_set_ts_config()
5198 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); in mvpp2_set_ts_config()
5213 mvpp22_tai_start(port->priv->tai); in mvpp2_set_ts_config()
5221 port->rx_hwtstamp = true; in mvpp2_set_ts_config()
5223 port->rx_hwtstamp = false; in mvpp2_set_ts_config()
5235 mvpp22_tai_stop(port->priv->tai); in mvpp2_set_ts_config()
5237 port->tx_hwtstamp_type = config.tx_type; in mvpp2_set_ts_config()
5239 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) in mvpp2_set_ts_config()
5240 return -EFAULT; in mvpp2_set_ts_config()
5251 config.tx_type = port->tx_hwtstamp_type; in mvpp2_get_ts_config()
5252 config.rx_filter = port->rx_hwtstamp ? in mvpp2_get_ts_config()
5255 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) in mvpp2_get_ts_config()
5256 return -EFAULT; in mvpp2_get_ts_config()
5266 if (!port->hwtstamp) in mvpp2_ethtool_get_ts_info()
5267 return -EOPNOTSUPP; in mvpp2_ethtool_get_ts_info()
5269 info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai); in mvpp2_ethtool_get_ts_info()
5270 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | in mvpp2_ethtool_get_ts_info()
5274 info->tx_types = BIT(HWTSTAMP_TX_OFF) | in mvpp2_ethtool_get_ts_info()
5276 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | in mvpp2_ethtool_get_ts_info()
5288 if (port->hwtstamp) in mvpp2_ioctl()
5293 if (port->hwtstamp) in mvpp2_ioctl()
5298 if (!port->phylink) in mvpp2_ioctl()
5299 return -ENOTSUPP; in mvpp2_ioctl()
5301 return phylink_mii_ioctl(port->phylink, ifr, cmd); in mvpp2_ioctl()
5311 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", in mvpp2_vlan_rx_add_vid()
5312 MVPP2_PRS_VLAN_FILT_MAX - 1); in mvpp2_vlan_rx_add_vid()
5327 netdev_features_t changed = dev->features ^ features; in mvpp2_set_features()
5355 struct bpf_prog *prog = bpf->prog, *old_prog; in mvpp2_xdp_setup()
5356 bool running = netif_running(port->dev); in mvpp2_xdp_setup()
5357 bool reset = !prog != !port->xdp_prog; in mvpp2_xdp_setup()
5359 if (port->dev->mtu > MVPP2_MAX_RX_BUF_SIZE) { in mvpp2_xdp_setup()
5360 NL_SET_ERR_MSG_MOD(bpf->extack, "MTU too large for XDP"); in mvpp2_xdp_setup()
5361 return -EOPNOTSUPP; in mvpp2_xdp_setup()
5364 if (!port->priv->percpu_pools) { in mvpp2_xdp_setup()
5365 NL_SET_ERR_MSG_MOD(bpf->extack, "Per CPU Pools required for XDP"); in mvpp2_xdp_setup()
5366 return -EOPNOTSUPP; in mvpp2_xdp_setup()
5369 if (port->ntxqs < num_possible_cpus() * 2) { in mvpp2_xdp_setup()
5370 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU"); in mvpp2_xdp_setup()
5371 return -EOPNOTSUPP; in mvpp2_xdp_setup()
5376 mvpp2_stop(port->dev); in mvpp2_xdp_setup()
5378 old_prog = xchg(&port->xdp_prog, prog); in mvpp2_xdp_setup()
5388 mvpp2_open(port->dev); in mvpp2_xdp_setup()
5400 switch (xdp->command) { in mvpp2_xdp()
5404 return -EINVAL; in mvpp2_xdp()
5414 if (!port->phylink) in mvpp2_ethtool_nway_reset()
5415 return -ENOTSUPP; in mvpp2_ethtool_nway_reset()
5417 return phylink_ethtool_nway_reset(port->phylink); in mvpp2_ethtool_nway_reset()
5430 for (queue = 0; queue < port->nrxqs; queue++) { in mvpp2_ethtool_set_coalesce()
5431 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_ethtool_set_coalesce()
5433 rxq->time_coal = c->rx_coalesce_usecs; in mvpp2_ethtool_set_coalesce()
5434 rxq->pkts_coal = c->rx_max_coalesced_frames; in mvpp2_ethtool_set_coalesce()
5439 if (port->has_tx_irqs) { in mvpp2_ethtool_set_coalesce()
5440 port->tx_time_coal = c->tx_coalesce_usecs; in mvpp2_ethtool_set_coalesce()
5444 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_ethtool_set_coalesce()
5445 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_ethtool_set_coalesce()
5447 txq->done_pkts_coal = c->tx_max_coalesced_frames; in mvpp2_ethtool_set_coalesce()
5449 if (port->has_tx_irqs) in mvpp2_ethtool_set_coalesce()
5465 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; in mvpp2_ethtool_get_coalesce()
5466 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; in mvpp2_ethtool_get_coalesce()
5467 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; in mvpp2_ethtool_get_coalesce()
5468 c->tx_coalesce_usecs = port->tx_time_coal; in mvpp2_ethtool_get_coalesce()
5475 strscpy(drvinfo->driver, MVPP2_DRIVER_NAME, in mvpp2_ethtool_get_drvinfo()
5476 sizeof(drvinfo->driver)); in mvpp2_ethtool_get_drvinfo()
5477 strscpy(drvinfo->version, MVPP2_DRIVER_VERSION, in mvpp2_ethtool_get_drvinfo()
5478 sizeof(drvinfo->version)); in mvpp2_ethtool_get_drvinfo()
5479 strscpy(drvinfo->bus_info, dev_name(&dev->dev), in mvpp2_ethtool_get_drvinfo()
5480 sizeof(drvinfo->bus_info)); in mvpp2_ethtool_get_drvinfo()
5491 ring->rx_max_pending = MVPP2_MAX_RXD_MAX; in mvpp2_ethtool_get_ringparam()
5492 ring->tx_max_pending = MVPP2_MAX_TXD_MAX; in mvpp2_ethtool_get_ringparam()
5493 ring->rx_pending = port->rx_ring_size; in mvpp2_ethtool_get_ringparam()
5494 ring->tx_pending = port->tx_ring_size; in mvpp2_ethtool_get_ringparam()
5504 u16 prev_rx_ring_size = port->rx_ring_size; in mvpp2_ethtool_set_ringparam()
5505 u16 prev_tx_ring_size = port->tx_ring_size; in mvpp2_ethtool_set_ringparam()
5513 port->rx_ring_size = ring->rx_pending; in mvpp2_ethtool_set_ringparam()
5514 port->tx_ring_size = ring->tx_pending; in mvpp2_ethtool_set_ringparam()
5525 port->rx_ring_size = ring->rx_pending; in mvpp2_ethtool_set_ringparam()
5526 port->tx_ring_size = ring->tx_pending; in mvpp2_ethtool_set_ringparam()
5531 port->rx_ring_size = prev_rx_ring_size; in mvpp2_ethtool_set_ringparam()
5532 ring->rx_pending = prev_rx_ring_size; in mvpp2_ethtool_set_ringparam()
5540 port->tx_ring_size = prev_tx_ring_size; in mvpp2_ethtool_set_ringparam()
5541 ring->tx_pending = prev_tx_ring_size; in mvpp2_ethtool_set_ringparam()
5565 if (!port->phylink) in mvpp2_ethtool_get_pause_param()
5568 phylink_ethtool_get_pauseparam(port->phylink, pause); in mvpp2_ethtool_get_pause_param()
5576 if (!port->phylink) in mvpp2_ethtool_set_pause_param()
5577 return -ENOTSUPP; in mvpp2_ethtool_set_pause_param()
5579 return phylink_ethtool_set_pauseparam(port->phylink, pause); in mvpp2_ethtool_set_pause_param()
5587 if (!port->phylink) in mvpp2_ethtool_get_link_ksettings()
5588 return -ENOTSUPP; in mvpp2_ethtool_get_link_ksettings()
5590 return phylink_ethtool_ksettings_get(port->phylink, cmd); in mvpp2_ethtool_get_link_ksettings()
5598 if (!port->phylink) in mvpp2_ethtool_set_link_ksettings()
5599 return -ENOTSUPP; in mvpp2_ethtool_set_link_ksettings()
5601 return phylink_ethtool_ksettings_set(port->phylink, cmd); in mvpp2_ethtool_set_link_ksettings()
5611 return -EOPNOTSUPP; in mvpp2_ethtool_get_rxnfc()
5613 switch (info->cmd) { in mvpp2_ethtool_get_rxnfc()
5618 info->data = port->nrxqs; in mvpp2_ethtool_get_rxnfc()
5621 info->rule_cnt = port->n_rfs_rules; in mvpp2_ethtool_get_rxnfc()
5628 if (loc == info->rule_cnt) { in mvpp2_ethtool_get_rxnfc()
5629 ret = -EMSGSIZE; in mvpp2_ethtool_get_rxnfc()
5633 if (port->rfs_rules[i]) in mvpp2_ethtool_get_rxnfc()
5638 return -ENOTSUPP; in mvpp2_ethtool_get_rxnfc()
5651 return -EOPNOTSUPP; in mvpp2_ethtool_set_rxnfc()
5653 switch (info->cmd) { in mvpp2_ethtool_set_rxnfc()
5664 return -EOPNOTSUPP; in mvpp2_ethtool_set_rxnfc()
5680 u32 rss_context = rxfh->rss_context; in mvpp2_ethtool_get_rxfh()
5684 return -EOPNOTSUPP; in mvpp2_ethtool_get_rxfh()
5686 return -EINVAL; in mvpp2_ethtool_get_rxfh()
5688 rxfh->hfunc = ETH_RSS_HASH_CRC32; in mvpp2_ethtool_get_rxfh()
5690 if (rxfh->indir) in mvpp2_ethtool_get_rxfh()
5692 rxfh->indir); in mvpp2_ethtool_get_rxfh()
5703 if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && in mvpp2_ethtool_rxfh_okay()
5704 rxfh->hfunc != ETH_RSS_HASH_CRC32) in mvpp2_ethtool_rxfh_okay()
5707 if (rxfh->key) in mvpp2_ethtool_rxfh_okay()
5722 return -EOPNOTSUPP; in mvpp2_create_rxfh_context()
5724 ctx->hfunc = ETH_RSS_HASH_CRC32; in mvpp2_create_rxfh_context()
5726 ret = mvpp22_port_rss_ctx_create(port, rxfh->rss_context); in mvpp2_create_rxfh_context()
5730 if (!rxfh->indir) in mvpp2_create_rxfh_context()
5731 ret = mvpp22_port_rss_ctx_indir_get(port, rxfh->rss_context, in mvpp2_create_rxfh_context()
5734 ret = mvpp22_port_rss_ctx_indir_set(port, rxfh->rss_context, in mvpp2_create_rxfh_context()
5735 rxfh->indir); in mvpp2_create_rxfh_context()
5748 return -EOPNOTSUPP; in mvpp2_modify_rxfh_context()
5750 if (rxfh->indir) in mvpp2_modify_rxfh_context()
5751 ret = mvpp22_port_rss_ctx_indir_set(port, rxfh->rss_context, in mvpp2_modify_rxfh_context()
5752 rxfh->indir); in mvpp2_modify_rxfh_context()
5821 * had a single IRQ defined per-port.
5826 struct mvpp2_queue_vector *v = &port->qvecs[0]; in mvpp2_simple_queue_vectors_init()
5828 v->first_rxq = 0; in mvpp2_simple_queue_vectors_init()
5829 v->nrxqs = port->nrxqs; in mvpp2_simple_queue_vectors_init()
5830 v->type = MVPP2_QUEUE_VECTOR_SHARED; in mvpp2_simple_queue_vectors_init()
5831 v->sw_thread_id = 0; in mvpp2_simple_queue_vectors_init()
5832 v->sw_thread_mask = *cpumask_bits(cpu_online_mask); in mvpp2_simple_queue_vectors_init()
5833 v->port = port; in mvpp2_simple_queue_vectors_init()
5834 v->irq = irq_of_parse_and_map(port_node, 0); in mvpp2_simple_queue_vectors_init()
5835 if (v->irq <= 0) in mvpp2_simple_queue_vectors_init()
5836 return -EINVAL; in mvpp2_simple_queue_vectors_init()
5837 netif_napi_add(port->dev, &v->napi, mvpp2_poll); in mvpp2_simple_queue_vectors_init()
5839 port->nqvecs = 1; in mvpp2_simple_queue_vectors_init()
5847 struct mvpp2 *priv = port->priv; in mvpp2_multi_queue_vectors_init()
5853 port->nqvecs = priv->nthreads + 1; in mvpp2_multi_queue_vectors_init()
5856 port->nqvecs = priv->nthreads; in mvpp2_multi_queue_vectors_init()
5860 for (i = 0; i < port->nqvecs; i++) { in mvpp2_multi_queue_vectors_init()
5863 v = port->qvecs + i; in mvpp2_multi_queue_vectors_init()
5865 v->port = port; in mvpp2_multi_queue_vectors_init()
5866 v->type = MVPP2_QUEUE_VECTOR_PRIVATE; in mvpp2_multi_queue_vectors_init()
5867 v->sw_thread_id = i; in mvpp2_multi_queue_vectors_init()
5868 v->sw_thread_mask = BIT(i); in mvpp2_multi_queue_vectors_init()
5870 if (port->flags & MVPP2_F_DT_COMPAT) in mvpp2_multi_queue_vectors_init()
5871 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); in mvpp2_multi_queue_vectors_init()
5876 v->first_rxq = i; in mvpp2_multi_queue_vectors_init()
5877 v->nrxqs = 1; in mvpp2_multi_queue_vectors_init()
5879 i == (port->nqvecs - 1)) { in mvpp2_multi_queue_vectors_init()
5880 v->first_rxq = 0; in mvpp2_multi_queue_vectors_init()
5881 v->nrxqs = port->nrxqs; in mvpp2_multi_queue_vectors_init()
5882 v->type = MVPP2_QUEUE_VECTOR_SHARED; in mvpp2_multi_queue_vectors_init()
5884 if (port->flags & MVPP2_F_DT_COMPAT) in mvpp2_multi_queue_vectors_init()
5885 strscpy(irqname, "rx-shared", sizeof(irqname)); in mvpp2_multi_queue_vectors_init()
5889 v->irq = of_irq_get_byname(port_node, irqname); in mvpp2_multi_queue_vectors_init()
5891 v->irq = fwnode_irq_get(port->fwnode, i); in mvpp2_multi_queue_vectors_init()
5892 if (v->irq <= 0) { in mvpp2_multi_queue_vectors_init()
5893 ret = -EINVAL; in mvpp2_multi_queue_vectors_init()
5897 netif_napi_add(port->dev, &v->napi, mvpp2_poll); in mvpp2_multi_queue_vectors_init()
5903 for (i = 0; i < port->nqvecs; i++) in mvpp2_multi_queue_vectors_init()
5904 irq_dispose_mapping(port->qvecs[i].irq); in mvpp2_multi_queue_vectors_init()
5911 if (port->has_tx_irqs) in mvpp2_queue_vectors_init()
5921 for (i = 0; i < port->nqvecs; i++) in mvpp2_queue_vectors_deinit()
5922 irq_dispose_mapping(port->qvecs[i].irq); in mvpp2_queue_vectors_deinit()
5928 struct mvpp2 *priv = port->priv; in mvpp2_rx_irqs_setup()
5932 if (priv->hw_version == MVPP21) { in mvpp2_rx_irqs_setup()
5933 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), in mvpp2_rx_irqs_setup()
5934 port->nrxqs); in mvpp2_rx_irqs_setup()
5939 for (i = 0; i < port->nqvecs; i++) { in mvpp2_rx_irqs_setup()
5940 struct mvpp2_queue_vector *qv = port->qvecs + i; in mvpp2_rx_irqs_setup()
5942 if (!qv->nrxqs) in mvpp2_rx_irqs_setup()
5945 val = qv->sw_thread_id; in mvpp2_rx_irqs_setup()
5946 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; in mvpp2_rx_irqs_setup()
5949 val = qv->first_rxq; in mvpp2_rx_irqs_setup()
5950 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; in mvpp2_rx_irqs_setup()
5958 struct device *dev = port->dev->dev.parent; in mvpp2_port_init()
5959 struct mvpp2 *priv = port->priv; in mvpp2_port_init()
5965 if (port->first_rxq + port->nrxqs > in mvpp2_port_init()
5966 MVPP2_MAX_PORTS * priv->max_port_rxqs) in mvpp2_port_init()
5967 return -EINVAL; in mvpp2_port_init()
5969 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ) in mvpp2_port_init()
5970 return -EINVAL; in mvpp2_port_init()
5976 if (mvpp2_is_xlg(port->phy_interface)) { in mvpp2_port_init()
5977 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_init()
5980 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_init()
5982 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_init()
5985 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_init()
5988 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; in mvpp2_port_init()
5990 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), in mvpp2_port_init()
5992 if (!port->txqs) in mvpp2_port_init()
5993 return -ENOMEM; in mvpp2_port_init()
5998 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_port_init()
5999 int queue_phy_id = mvpp2_txq_phys(port->id, queue); in mvpp2_port_init()
6004 err = -ENOMEM; in mvpp2_port_init()
6008 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); in mvpp2_port_init()
6009 if (!txq->pcpu) { in mvpp2_port_init()
6010 err = -ENOMEM; in mvpp2_port_init()
6014 txq->id = queue_phy_id; in mvpp2_port_init()
6015 txq->log_id = queue; in mvpp2_port_init()
6016 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; in mvpp2_port_init()
6017 for (thread = 0; thread < priv->nthreads; thread++) { in mvpp2_port_init()
6018 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); in mvpp2_port_init()
6019 txq_pcpu->thread = thread; in mvpp2_port_init()
6022 port->txqs[queue] = txq; in mvpp2_port_init()
6025 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), in mvpp2_port_init()
6027 if (!port->rxqs) { in mvpp2_port_init()
6028 err = -ENOMEM; in mvpp2_port_init()
6033 for (queue = 0; queue < port->nrxqs; queue++) { in mvpp2_port_init()
6039 err = -ENOMEM; in mvpp2_port_init()
6043 rxq->id = port->first_rxq + queue; in mvpp2_port_init()
6044 rxq->port = port->id; in mvpp2_port_init()
6045 rxq->logic_rxq = queue; in mvpp2_port_init()
6047 port->rxqs[queue] = rxq; in mvpp2_port_init()
6053 for (queue = 0; queue < port->nrxqs; queue++) { in mvpp2_port_init()
6054 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_port_init()
6056 rxq->size = port->rx_ring_size; in mvpp2_port_init()
6057 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; in mvpp2_port_init()
6058 rxq->time_coal = MVPP2_RX_COAL_USEC; in mvpp2_port_init()
6074 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); in mvpp2_port_init()
6083 memset(port->ethtool_stats, 0, in mvpp2_port_init()
6084 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64)); in mvpp2_port_init()
6089 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_port_init()
6090 if (!port->txqs[queue]) in mvpp2_port_init()
6092 free_percpu(port->txqs[queue]->pcpu); in mvpp2_port_init()
6100 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2", in mvpp22_port_has_legacy_tx_irqs()
6101 "tx-cpu3" }; in mvpp22_port_has_legacy_tx_irqs()
6105 if (of_property_match_string(port_node, "interrupt-names", in mvpp22_port_has_legacy_tx_irqs()
6114 * - PPv2.1: there are no such interrupts.
6115 * - PPv2.2 and PPv2.3:
6116 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
6117 * - The new ones have: "hifX" with X in [0..8]
6132 if (priv->hw_version == MVPP21) in mvpp2_port_has_irqs()
6140 if (of_property_match_string(port_node, "interrupt-names", in mvpp2_port_has_irqs()
6163 if (priv->hw_version == MVPP21) { in mvpp2_port_copy_mac_addr()
6174 if (ret == -EPROBE_DEFER) in mvpp2_port_copy_mac_addr()
6209 if (port->phy_interface == PHY_INTERFACE_MODE_5GBASER) in mvpp2_xlg_pcs_get_state()
6210 state->speed = SPEED_5000; in mvpp2_xlg_pcs_get_state()
6212 state->speed = SPEED_10000; in mvpp2_xlg_pcs_get_state()
6213 state->duplex = 1; in mvpp2_xlg_pcs_get_state()
6214 state->an_complete = 1; in mvpp2_xlg_pcs_get_state()
6216 val = readl(port->base + MVPP22_XLG_STATUS); in mvpp2_xlg_pcs_get_state()
6217 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); in mvpp2_xlg_pcs_get_state()
6219 state->pause = 0; in mvpp2_xlg_pcs_get_state()
6220 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_pcs_get_state()
6222 state->pause |= MLO_PAUSE_TX; in mvpp2_xlg_pcs_get_state()
6224 state->pause |= MLO_PAUSE_RX; in mvpp2_xlg_pcs_get_state()
6245 * Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ... in mvpp2_gmac_pcs_validate()
6246 * When <PortType> = 1 (1000BASE-X) this field must be set to 1. in mvpp2_gmac_pcs_validate()
6248 if (phy_interface_mode_is_8023z(state->interface) && in mvpp2_gmac_pcs_validate()
6249 !phylink_test(state->advertising, Autoneg)) in mvpp2_gmac_pcs_validate()
6250 return -EINVAL; in mvpp2_gmac_pcs_validate()
6261 val = readl(port->base + MVPP2_GMAC_STATUS0); in mvpp2_gmac_pcs_get_state()
6263 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); in mvpp2_gmac_pcs_get_state()
6264 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); in mvpp2_gmac_pcs_get_state()
6265 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); in mvpp2_gmac_pcs_get_state()
6267 switch (port->phy_interface) { in mvpp2_gmac_pcs_get_state()
6269 state->speed = SPEED_1000; in mvpp2_gmac_pcs_get_state()
6272 state->speed = SPEED_2500; in mvpp2_gmac_pcs_get_state()
6276 state->speed = SPEED_1000; in mvpp2_gmac_pcs_get_state()
6278 state->speed = SPEED_100; in mvpp2_gmac_pcs_get_state()
6280 state->speed = SPEED_10; in mvpp2_gmac_pcs_get_state()
6283 state->pause = 0; in mvpp2_gmac_pcs_get_state()
6285 state->pause |= MLO_PAUSE_RX; in mvpp2_gmac_pcs_get_state()
6287 state->pause |= MLO_PAUSE_TX; in mvpp2_gmac_pcs_get_state()
6337 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_config()
6341 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_config()
6350 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_an_restart()
6353 port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_an_restart()
6355 port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_an_restart()
6370 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_xlg_config()
6373 mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG, in mvpp2_xlg_config()
6381 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_config()
6392 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_config()
6393 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_gmac_config()
6394 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); in mvpp2_gmac_config()
6400 if (phy_interface_mode_is_8023z(state->interface)) { in mvpp2_gmac_config()
6406 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { in mvpp2_gmac_config()
6412 } else if (phy_interface_mode_is_rgmii(state->interface)) { in mvpp2_gmac_config()
6421 /* Phy or fixed speed - no in-band AN, nothing to do, leave the in mvpp2_gmac_config()
6422 * configured speed, duplex and flow control as-is. in mvpp2_gmac_config()
6424 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { in mvpp2_gmac_config()
6425 /* SGMII in-band mode receives the speed and duplex from in mvpp2_gmac_config()
6427 } else if (phy_interface_mode_is_8023z(state->interface)) { in mvpp2_gmac_config()
6437 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_config()
6439 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_gmac_config()
6441 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); in mvpp2_gmac_config()
6454 return &port->pcs_xlg; in mvpp2_select_pcs()
6456 return &port->pcs_gmac; in mvpp2_select_pcs()
6465 if (mvpp2_is_xlg(interface) && port->gop_id != 0) { in mvpp2_mac_prepare()
6466 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name); in mvpp2_mac_prepare()
6467 return -EINVAL; in mvpp2_mac_prepare()
6470 if (port->phy_interface != interface || in mvpp2_mac_prepare()
6473 * in-band mode to ensure we do not change the configuration in mvpp2_mac_prepare()
6478 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, in mvpp2_mac_prepare()
6484 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_mac_prepare()
6493 if (port->phy_interface != interface) { in mvpp2_mac_prepare()
6495 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, in mvpp2_mac_prepare()
6499 if (port->priv->hw_version >= MVPP22) { in mvpp2_mac_prepare()
6502 phy_power_off(port->comphy); in mvpp2_mac_prepare()
6518 if (mvpp2_is_xlg(state->interface)) in mvpp2_mac_config()
6520 else if (phy_interface_mode_is_rgmii(state->interface) || in mvpp2_mac_config()
6521 phy_interface_mode_is_8023z(state->interface) || in mvpp2_mac_config()
6522 state->interface == PHY_INTERFACE_MODE_SGMII) in mvpp2_mac_config()
6525 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) in mvpp2_mac_config()
6534 if (port->priv->hw_version >= MVPP22 && in mvpp2_mac_finish()
6535 port->phy_interface != interface) { in mvpp2_mac_finish()
6536 port->phy_interface = interface; in mvpp2_mac_finish()
6544 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, in mvpp2_mac_finish()
6547 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_mac_finish()
6554 /* Allow the link to come up if in in-band mode, otherwise the in mvpp2_mac_finish()
6559 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_mac_finish()
6563 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, in mvpp2_mac_finish()
6589 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_mac_link_up()
6607 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, in mvpp2_mac_link_up()
6625 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG, in mvpp2_mac_link_up()
6630 if (port->priv->global_tx_fc) { in mvpp2_mac_link_up()
6631 port->tx_fc = tx_pause; in mvpp2_mac_link_up()
6636 if (port->priv->percpu_pools) { in mvpp2_mac_link_up()
6637 for (i = 0; i < port->nrxqs; i++) in mvpp2_mac_link_up()
6638 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], tx_pause); in mvpp2_mac_link_up()
6640 mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause); in mvpp2_mac_link_up()
6641 mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause); in mvpp2_mac_link_up()
6643 if (port->priv->hw_version == MVPP23) in mvpp2_mac_link_up()
6644 mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause); in mvpp2_mac_link_up()
6651 netif_tx_wake_all_queues(port->dev); in mvpp2_mac_link_up()
6662 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_mac_link_down()
6665 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_mac_link_down()
6667 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_mac_link_down()
6670 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_mac_link_down()
6674 netif_tx_stop_all_queues(port->dev); in mvpp2_mac_link_down()
6690 /* Work-around for ACPI */
6698 .interface = port->phy_interface, in mvpp2_acpi_start()
6702 pcs = mvpp2_select_pcs(&port->phylink_config, port->phy_interface); in mvpp2_acpi_start()
6704 mvpp2_mac_prepare(&port->phylink_config, MLO_AN_INBAND, in mvpp2_acpi_start()
6705 port->phy_interface); in mvpp2_acpi_start()
6706 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state); in mvpp2_acpi_start()
6707 pcs->ops->pcs_config(pcs, PHYLINK_PCS_NEG_INBAND_ENABLED, in mvpp2_acpi_start()
6708 port->phy_interface, state.advertising, in mvpp2_acpi_start()
6710 mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND, in mvpp2_acpi_start()
6711 port->phy_interface); in mvpp2_acpi_start()
6712 mvpp2_mac_link_up(&port->phylink_config, NULL, in mvpp2_acpi_start()
6713 MLO_AN_INBAND, port->phy_interface, in mvpp2_acpi_start()
6725 return (!fwnode_property_present(port_fwnode, "phy-handle") && in mvpp2_use_acpi_compat_mode()
6727 !fwnode_get_named_child_node(port_fwnode, "fixed-link")); in mvpp2_use_acpi_compat_mode()
6752 dev_err(&pdev->dev, in mvpp2_port_probe()
6754 return -EINVAL; in mvpp2_port_probe()
6762 return -ENOMEM; in mvpp2_port_probe()
6766 dev_err(&pdev->dev, "incorrect phy mode\n"); in mvpp2_port_probe()
6772 * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT. in mvpp2_port_probe()
6773 * Existing usage of 10GBASE-KR is not correct; no backplane in mvpp2_port_probe()
6775 * 10GBASE-KR. in mvpp2_port_probe()
6781 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); in mvpp2_port_probe()
6783 if (PTR_ERR(comphy) == -EPROBE_DEFER) { in mvpp2_port_probe()
6784 err = -EPROBE_DEFER; in mvpp2_port_probe()
6791 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { in mvpp2_port_probe()
6792 err = -EINVAL; in mvpp2_port_probe()
6793 dev_err(&pdev->dev, "missing port-id value\n"); in mvpp2_port_probe()
6797 dev->tx_queue_len = MVPP2_MAX_TXD_MAX; in mvpp2_port_probe()
6798 dev->watchdog_timeo = 5 * HZ; in mvpp2_port_probe()
6799 dev->netdev_ops = &mvpp2_netdev_ops; in mvpp2_port_probe()
6800 dev->ethtool_ops = &mvpp2_eth_tool_ops; in mvpp2_port_probe()
6803 port->dev = dev; in mvpp2_port_probe()
6804 port->fwnode = port_fwnode; in mvpp2_port_probe()
6805 port->ntxqs = ntxqs; in mvpp2_port_probe()
6806 port->nrxqs = nrxqs; in mvpp2_port_probe()
6807 port->priv = priv; in mvpp2_port_probe()
6808 port->has_tx_irqs = has_tx_irqs; in mvpp2_port_probe()
6809 port->flags = flags; in mvpp2_port_probe()
6816 port->port_irq = of_irq_get_byname(port_node, "link"); in mvpp2_port_probe()
6818 port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); in mvpp2_port_probe()
6819 if (port->port_irq == -EPROBE_DEFER) { in mvpp2_port_probe()
6820 err = -EPROBE_DEFER; in mvpp2_port_probe()
6823 if (port->port_irq <= 0) in mvpp2_port_probe()
6825 port->port_irq = 0; in mvpp2_port_probe()
6828 port->flags |= MVPP2_F_LOOPBACK; in mvpp2_port_probe()
6830 port->id = id; in mvpp2_port_probe()
6831 if (priv->hw_version == MVPP21) in mvpp2_port_probe()
6832 port->first_rxq = port->id * port->nrxqs; in mvpp2_port_probe()
6834 port->first_rxq = port->id * priv->max_port_rxqs; in mvpp2_port_probe()
6836 port->of_node = port_node; in mvpp2_port_probe()
6837 port->phy_interface = phy_mode; in mvpp2_port_probe()
6838 port->comphy = comphy; in mvpp2_port_probe()
6840 if (priv->hw_version == MVPP21) { in mvpp2_port_probe()
6841 port->base = devm_platform_ioremap_resource(pdev, 2 + id); in mvpp2_port_probe()
6842 if (IS_ERR(port->base)) { in mvpp2_port_probe()
6843 err = PTR_ERR(port->base); in mvpp2_port_probe()
6847 port->stats_base = port->priv->lms_base + in mvpp2_port_probe()
6849 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; in mvpp2_port_probe()
6851 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", in mvpp2_port_probe()
6852 &port->gop_id)) { in mvpp2_port_probe()
6853 err = -EINVAL; in mvpp2_port_probe()
6854 dev_err(&pdev->dev, "missing gop-port-id value\n"); in mvpp2_port_probe()
6858 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); in mvpp2_port_probe()
6859 port->stats_base = port->priv->iface_base + in mvpp2_port_probe()
6861 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; in mvpp2_port_probe()
6866 if (priv->tai) in mvpp2_port_probe()
6867 port->hwtstamp = true; in mvpp2_port_probe()
6870 /* Alloc per-cpu and ethtool stats */ in mvpp2_port_probe()
6871 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); in mvpp2_port_probe()
6872 if (!port->stats) { in mvpp2_port_probe()
6873 err = -ENOMEM; in mvpp2_port_probe()
6877 port->ethtool_stats = devm_kcalloc(&pdev->dev, in mvpp2_port_probe()
6880 if (!port->ethtool_stats) { in mvpp2_port_probe()
6881 err = -ENOMEM; in mvpp2_port_probe()
6885 mutex_init(&port->gather_stats_lock); in mvpp2_port_probe()
6886 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); in mvpp2_port_probe()
6892 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; in mvpp2_port_probe()
6893 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; in mvpp2_port_probe()
6894 SET_NETDEV_DEV(dev, &pdev->dev); in mvpp2_port_probe()
6898 dev_err(&pdev->dev, "failed to init port %d\n", id); in mvpp2_port_probe()
6907 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); in mvpp2_port_probe()
6908 if (!port->pcpu) { in mvpp2_port_probe()
6909 err = -ENOMEM; in mvpp2_port_probe()
6913 if (!port->has_tx_irqs) { in mvpp2_port_probe()
6914 for (thread = 0; thread < priv->nthreads; thread++) { in mvpp2_port_probe()
6915 port_pcpu = per_cpu_ptr(port->pcpu, thread); in mvpp2_port_probe()
6917 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, in mvpp2_port_probe()
6919 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; in mvpp2_port_probe()
6920 port_pcpu->timer_scheduled = false; in mvpp2_port_probe()
6921 port_pcpu->dev = dev; in mvpp2_port_probe()
6927 dev->features = features | NETIF_F_RXCSUM; in mvpp2_port_probe()
6928 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | in mvpp2_port_probe()
6932 dev->hw_features |= NETIF_F_RXHASH; in mvpp2_port_probe()
6933 dev->features |= NETIF_F_NTUPLE; in mvpp2_port_probe()
6936 if (!port->priv->percpu_pools) in mvpp2_port_probe()
6937 mvpp2_set_hw_csum(port, port->pool_long->id); in mvpp2_port_probe()
6938 else if (port->ntxqs >= num_possible_cpus() * 2) in mvpp2_port_probe()
6939 dev->xdp_features = NETDEV_XDP_ACT_BASIC | in mvpp2_port_probe()
6943 dev->vlan_features |= features; in mvpp2_port_probe()
6946 dev->priv_flags |= IFF_UNICAST_FLT; in mvpp2_port_probe()
6948 /* MTU range: 68 - 9704 */ in mvpp2_port_probe()
6949 dev->min_mtu = ETH_MIN_MTU; in mvpp2_port_probe()
6950 /* 9704 == 9728 - 20 and rounding to 8 */ in mvpp2_port_probe()
6951 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; in mvpp2_port_probe()
6952 device_set_node(&dev->dev, port_fwnode); in mvpp2_port_probe()
6953 dev->dev_port = port->id; in mvpp2_port_probe()
6955 port->pcs_gmac.ops = &mvpp2_phylink_gmac_pcs_ops; in mvpp2_port_probe()
6956 port->pcs_gmac.neg_mode = true; in mvpp2_port_probe()
6957 port->pcs_xlg.ops = &mvpp2_phylink_xlg_pcs_ops; in mvpp2_port_probe()
6958 port->pcs_xlg.neg_mode = true; in mvpp2_port_probe()
6961 port->phylink_config.dev = &dev->dev; in mvpp2_port_probe()
6962 port->phylink_config.type = PHYLINK_NETDEV; in mvpp2_port_probe()
6963 port->phylink_config.mac_capabilities = in mvpp2_port_probe()
6966 if (port->priv->global_tx_fc) in mvpp2_port_probe()
6967 port->phylink_config.mac_capabilities |= in mvpp2_port_probe()
6976 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6978 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6980 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6983 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6986 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6989 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6993 port->phylink_config.mac_capabilities |= in mvpp2_port_probe()
6996 port->phylink_config.mac_capabilities |= in mvpp2_port_probe()
6999 port->phylink_config.mac_capabilities |= in mvpp2_port_probe()
7004 phy_interface_set_rgmii(port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7006 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7014 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7016 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7018 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7020 /* No COMPHY, with only 2500BASE-X mode supported */ in mvpp2_port_probe()
7022 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7025 /* No COMPHY, we can switch between 1000BASE-X and SGMII in mvpp2_port_probe()
7028 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7030 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7033 phylink = phylink_create(&port->phylink_config, port_fwnode, in mvpp2_port_probe()
7039 port->phylink = phylink; in mvpp2_port_probe()
7041 dev_warn(&pdev->dev, "Use link irqs for port#%d. FW update required\n", port->id); in mvpp2_port_probe()
7042 port->phylink = NULL; in mvpp2_port_probe()
7045 /* Cycle the comphy to power it down, saving 270mW per port - in mvpp2_port_probe()
7049 if (port->comphy) { in mvpp2_port_probe()
7050 err = mvpp22_comphy_init(port, port->phy_interface); in mvpp2_port_probe()
7052 phy_power_off(port->comphy); in mvpp2_port_probe()
7057 dev_err(&pdev->dev, "failed to register netdev\n"); in mvpp2_port_probe()
7060 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); in mvpp2_port_probe()
7062 priv->port_list[priv->port_count++] = port; in mvpp2_port_probe()
7067 if (port->phylink) in mvpp2_port_probe()
7068 phylink_destroy(port->phylink); in mvpp2_port_probe()
7070 free_percpu(port->pcpu); in mvpp2_port_probe()
7072 for (i = 0; i < port->ntxqs; i++) in mvpp2_port_probe()
7073 free_percpu(port->txqs[i]->pcpu); in mvpp2_port_probe()
7075 free_percpu(port->stats); in mvpp2_port_probe()
7077 if (port->port_irq) in mvpp2_port_probe()
7078 irq_dispose_mapping(port->port_irq); in mvpp2_port_probe()
7091 unregister_netdev(port->dev); in mvpp2_port_remove()
7092 if (port->phylink) in mvpp2_port_remove()
7093 phylink_destroy(port->phylink); in mvpp2_port_remove()
7094 free_percpu(port->pcpu); in mvpp2_port_remove()
7095 free_percpu(port->stats); in mvpp2_port_remove()
7096 for (i = 0; i < port->ntxqs; i++) in mvpp2_port_remove()
7097 free_percpu(port->txqs[i]->pcpu); in mvpp2_port_remove()
7099 if (port->port_irq) in mvpp2_port_remove()
7100 irq_dispose_mapping(port->port_irq); in mvpp2_port_remove()
7101 free_netdev(port->dev); in mvpp2_port_remove()
7121 for (i = 0; i < dram->num_cs; i++) { in mvpp2_conf_mbus_windows()
7122 const struct mbus_dram_window *cs = dram->cs + i; in mvpp2_conf_mbus_windows()
7125 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | in mvpp2_conf_mbus_windows()
7126 dram->mbus_dram_target_id); in mvpp2_conf_mbus_windows()
7129 (cs->size - 1) & 0xffff0000); in mvpp2_conf_mbus_windows()
7178 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX); in mvpp22_rx_fifo_init()
7200 size_remainder -= size; in mvpp22_rx_fifo_init()
7201 remaining_ports_count--; in mvpp22_rx_fifo_init()
7216 /* Port 0: maximum speed -10Gb/s port in mvpp23_rx_fifo_fc_set_tresh()
7218 * Port 1: maximum speed -5Gb/s port in mvpp23_rx_fifo_fc_set_tresh()
7220 * Port 2: maximum speed -1Gb/s port in mvpp23_rx_fifo_fc_set_tresh()
7225 for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) { in mvpp23_rx_fifo_fc_set_tresh()
7284 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX); in mvpp22_tx_fifo_init()
7303 size_remainder -= size; in mvpp22_tx_fifo_init()
7304 remaining_ports_count--; in mvpp22_tx_fifo_init()
7376 if (priv->hw_version >= MVPP22) in mvpp2_init()
7380 if (priv->hw_version == MVPP21) { in mvpp2_init()
7381 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); in mvpp2_init()
7383 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); in mvpp2_init()
7385 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); in mvpp2_init()
7387 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); in mvpp2_init()
7391 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS, in mvpp2_init()
7392 sizeof(*priv->aggr_txqs), in mvpp2_init()
7394 if (!priv->aggr_txqs) in mvpp2_init()
7395 return -ENOMEM; in mvpp2_init()
7398 priv->aggr_txqs[i].id = i; in mvpp2_init()
7399 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; in mvpp2_init()
7400 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); in mvpp2_init()
7406 if (priv->hw_version == MVPP21) { in mvpp2_init()
7411 if (priv->hw_version == MVPP23) in mvpp2_init()
7415 if (priv->hw_version == MVPP21) in mvpp2_init()
7417 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); in mvpp2_init()
7423 err = mvpp2_bm_init(&pdev->dev, priv); in mvpp2_init()
7446 if (has_acpi_companion(&pdev->dev)) in mvpp2_get_sram()
7447 dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n"); in mvpp2_get_sram()
7449 dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n"); in mvpp2_get_sram()
7453 base = devm_ioremap_resource(&pdev->dev, res); in mvpp2_get_sram()
7457 priv->cm3_base = base; in mvpp2_get_sram()
7469 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in mvpp2_probe()
7471 return -ENOMEM; in mvpp2_probe()
7473 priv->hw_version = (unsigned long)device_get_match_data(&pdev->dev); in mvpp2_probe()
7478 if (priv->hw_version == MVPP21) in mvpp2_probe()
7485 if (priv->hw_version == MVPP21) { in mvpp2_probe()
7486 priv->lms_base = devm_platform_ioremap_resource(pdev, 1); in mvpp2_probe()
7487 if (IS_ERR(priv->lms_base)) in mvpp2_probe()
7488 return PTR_ERR(priv->lms_base); in mvpp2_probe()
7492 dev_err(&pdev->dev, "Invalid resource\n"); in mvpp2_probe()
7493 return -EINVAL; in mvpp2_probe()
7495 if (has_acpi_companion(&pdev->dev)) { in mvpp2_probe()
7497 * the ACPI, it can already appear as 'in-use' in mvpp2_probe()
7506 priv->iface_base = devm_ioremap_resource(&pdev->dev, res); in mvpp2_probe()
7507 if (IS_ERR(priv->iface_base)) in mvpp2_probe()
7508 return PTR_ERR(priv->iface_base); in mvpp2_probe()
7513 dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n"); in mvpp2_probe()
7516 if (priv->cm3_base) in mvpp2_probe()
7517 priv->global_tx_fc = true; in mvpp2_probe()
7520 if (priv->hw_version >= MVPP22 && dev_of_node(&pdev->dev)) { in mvpp2_probe()
7521 priv->sysctrl_base = in mvpp2_probe()
7522 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in mvpp2_probe()
7523 "marvell,system-controller"); in mvpp2_probe()
7524 if (IS_ERR(priv->sysctrl_base)) in mvpp2_probe()
7530 priv->sysctrl_base = NULL; in mvpp2_probe()
7533 if (priv->hw_version >= MVPP22 && in mvpp2_probe()
7535 priv->percpu_pools = 1; in mvpp2_probe()
7540 priv->nthreads = min_t(unsigned int, num_present_cpus(), in mvpp2_probe()
7543 shared = num_present_cpus() - priv->nthreads; in mvpp2_probe()
7545 bitmap_set(&priv->lock_map, 0, in mvpp2_probe()
7551 addr_space_sz = (priv->hw_version == MVPP21 ? in mvpp2_probe()
7553 priv->swth_base[i] = base + i * addr_space_sz; in mvpp2_probe()
7556 if (priv->hw_version == MVPP21) in mvpp2_probe()
7557 priv->max_port_rxqs = 8; in mvpp2_probe()
7559 priv->max_port_rxqs = 32; in mvpp2_probe()
7561 if (dev_of_node(&pdev->dev)) { in mvpp2_probe()
7562 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); in mvpp2_probe()
7563 if (IS_ERR(priv->pp_clk)) in mvpp2_probe()
7564 return PTR_ERR(priv->pp_clk); in mvpp2_probe()
7565 err = clk_prepare_enable(priv->pp_clk); in mvpp2_probe()
7569 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); in mvpp2_probe()
7570 if (IS_ERR(priv->gop_clk)) { in mvpp2_probe()
7571 err = PTR_ERR(priv->gop_clk); in mvpp2_probe()
7574 err = clk_prepare_enable(priv->gop_clk); in mvpp2_probe()
7578 if (priv->hw_version >= MVPP22) { in mvpp2_probe()
7579 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); in mvpp2_probe()
7580 if (IS_ERR(priv->mg_clk)) { in mvpp2_probe()
7581 err = PTR_ERR(priv->mg_clk); in mvpp2_probe()
7585 err = clk_prepare_enable(priv->mg_clk); in mvpp2_probe()
7589 priv->mg_core_clk = devm_clk_get_optional(&pdev->dev, "mg_core_clk"); in mvpp2_probe()
7590 if (IS_ERR(priv->mg_core_clk)) { in mvpp2_probe()
7591 err = PTR_ERR(priv->mg_core_clk); in mvpp2_probe()
7595 err = clk_prepare_enable(priv->mg_core_clk); in mvpp2_probe()
7600 priv->axi_clk = devm_clk_get_optional(&pdev->dev, "axi_clk"); in mvpp2_probe()
7601 if (IS_ERR(priv->axi_clk)) { in mvpp2_probe()
7602 err = PTR_ERR(priv->axi_clk); in mvpp2_probe()
7606 err = clk_prepare_enable(priv->axi_clk); in mvpp2_probe()
7611 priv->tclk = clk_get_rate(priv->pp_clk); in mvpp2_probe()
7613 err = device_property_read_u32(&pdev->dev, "clock-frequency", &priv->tclk); in mvpp2_probe()
7615 dev_err(&pdev->dev, "missing clock-frequency value\n"); in mvpp2_probe()
7620 if (priv->hw_version >= MVPP22) { in mvpp2_probe()
7621 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); in mvpp2_probe()
7629 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); in mvpp2_probe()
7634 /* Map DTS-active ports. Should be done before FIFO mvpp2_init */ in mvpp2_probe()
7635 device_for_each_child_node_scoped(&pdev->dev, port_fwnode) { in mvpp2_probe()
7636 if (!fwnode_property_read_u32(port_fwnode, "port-id", &i)) in mvpp2_probe()
7637 priv->port_map |= BIT(i); in mvpp2_probe()
7641 priv->hw_version = MVPP23; in mvpp2_probe()
7644 spin_lock_init(&priv->mss_spinlock); in mvpp2_probe()
7649 dev_err(&pdev->dev, "failed to initialize controller\n"); in mvpp2_probe()
7653 err = mvpp22_tai_probe(&pdev->dev, priv); in mvpp2_probe()
7658 device_for_each_child_node_scoped(&pdev->dev, port_fwnode) { in mvpp2_probe()
7664 if (priv->port_count == 0) { in mvpp2_probe()
7665 dev_err(&pdev->dev, "no ports enabled\n"); in mvpp2_probe()
7666 err = -ENODEV; in mvpp2_probe()
7671 * packets counters) are 32-bit registers and could overflow quite in mvpp2_probe()
7673 * smallest packets (64B) will overflow a 32-bit counter in less than in mvpp2_probe()
7674 * 30 seconds. Then, use a workqueue to fill 64-bit counters. in mvpp2_probe()
7676 snprintf(priv->queue_name, sizeof(priv->queue_name), in mvpp2_probe()
7677 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), in mvpp2_probe()
7678 priv->port_count > 1 ? "+" : ""); in mvpp2_probe()
7679 priv->stats_queue = create_singlethread_workqueue(priv->queue_name); in mvpp2_probe()
7680 if (!priv->stats_queue) { in mvpp2_probe()
7681 err = -ENOMEM; in mvpp2_probe()
7685 if (priv->global_tx_fc && priv->hw_version >= MVPP22) { in mvpp2_probe()
7688 …dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control… in mvpp2_probe()
7691 mvpp2_dbgfs_init(priv, pdev->name); in mvpp2_probe()
7697 for (i = 0; i < priv->port_count; i++) in mvpp2_probe()
7698 mvpp2_port_remove(priv->port_list[i]); in mvpp2_probe()
7700 clk_disable_unprepare(priv->axi_clk); in mvpp2_probe()
7702 clk_disable_unprepare(priv->mg_core_clk); in mvpp2_probe()
7704 clk_disable_unprepare(priv->mg_clk); in mvpp2_probe()
7706 clk_disable_unprepare(priv->gop_clk); in mvpp2_probe()
7708 clk_disable_unprepare(priv->pp_clk); in mvpp2_probe()
7719 for (i = 0; i < priv->port_count; i++) { in mvpp2_remove()
7720 mutex_destroy(&priv->port_list[i]->gather_stats_lock); in mvpp2_remove()
7721 mvpp2_port_remove(priv->port_list[i]); in mvpp2_remove()
7724 destroy_workqueue(priv->stats_queue); in mvpp2_remove()
7726 if (priv->percpu_pools) in mvpp2_remove()
7730 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; in mvpp2_remove()
7732 mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool); in mvpp2_remove()
7736 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; in mvpp2_remove()
7738 dma_free_coherent(&pdev->dev, in mvpp2_remove()
7740 aggr_txq->descs, in mvpp2_remove()
7741 aggr_txq->descs_dma); in mvpp2_remove()
7744 if (!dev_of_node(&pdev->dev)) in mvpp2_remove()
7747 clk_disable_unprepare(priv->axi_clk); in mvpp2_remove()
7748 clk_disable_unprepare(priv->mg_core_clk); in mvpp2_remove()
7749 clk_disable_unprepare(priv->mg_clk); in mvpp2_remove()
7750 clk_disable_unprepare(priv->pp_clk); in mvpp2_remove()
7751 clk_disable_unprepare(priv->gop_clk); in mvpp2_remove()
7756 .compatible = "marvell,armada-375-pp2",
7760 .compatible = "marvell,armada-7k-pp22",
7798 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");