Lines Matching full:ppv2

3  * Definitions for Marvell PPv2 network controller for Armada 375 SoC.
485 /* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
522 /* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */
526 /* TAI registers, PPv2.2 only, relative to priv->iface_base */
598 /* XPCS registers.PPv2.2 and PPv2.3 */
609 /* FCA registers. PPv2.2 and PPv2.3 */
618 /* XPCS registers. PPv2.2 and PPv2.3 */
625 /* PTP registers. PPv2.2 only */
1034 	/* On PPv2.2 and PPv2.3, each "software thread" can access the base
1041 	/* On PPv2.2 and PPv2.3, some port control registers are located into
1189 	 * of view. This is specific to PPv2.2.
1308 /* HW TX descriptor for PPv2.1 */
1320 /* HW RX descriptor for PPv2.1 */
1336 /* HW TX descriptor for PPv2.2 and PPv2.3 */
1348 /* HW RX descriptor for PPv2.2 and PPv2.3 */