intel/ixgbevf/defines.h

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
33 #define IXGBE_RXDCTL_ENABLE	0x02000000 /* Enable specific Rx Queue */
34 #define IXGBE_TXDCTL_ENABLE	0x02000000 /* Enable specific Tx Queue */
54 #define IXGBE_RXDCTL_ENABLE	0x02000000  /* Enable specific Rx Queue */
60 #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
93 #define IXGBE_RXD_STAT_PIF	0x80    /* passed in-exact filter */
97 #define IXGBE_RXD_STAT_DYNINT	0x800   /* Pkt caused INT via DYNINT */
128 #define IXGBE_RXDADV_STAT_VP		IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
129 #define IXGBE_RXDADV_STAT_MASK		0x000FFFFF /* Stat/NEXTP: bit 0-19 */
131 #define IXGBE_RXDADV_STAT_FCSTAT	0x00000030 /* FCoE Pkt Stat */
136 #define IXGBE_RXDADV_STAT_SECP		0x00020000 /* IPsec/MACsec pkt found */
189 /* Transmit Descriptor - Advanced */
203 /* Receive Descriptor - Advanced */
214 					__le16 pkt_info; /* RSS, Pkt type */
250 #define IXGBE_ADVTXD_DCMD_VLE	IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */
281 #define IXGBE_ERR_INVALID_MAC_ADDR	-1
282 #define IXGBE_ERR_RESET_FAILED		-2
283 #define IXGBE_ERR_INVALID_ARGUMENT	-3
284 #define IXGBE_ERR_CONFIG		-4
285 #define IXGBE_ERR_MBX			-5
286 #define IXGBE_ERR_TIMEOUT		-6
287 #define IXGBE_ERR_PARAM			-7
290 #define IXGBE_TXDCTL_ENABLE		0x02000000 /* Ena specific Tx Queue */
291 #define IXGBE_TXDCTL_SWFLSH		0x04000000 /* Tx Desc. wr-bk flushing */
301 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN	BIT(5)  /* DCA Tx Desc enable */
302 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN	BIT(9)  /* Tx rd Desc Relax Order */
303 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN	BIT(11) /* Tx Desc writeback RO bit */
304 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN	BIT(13) /* Tx rd data Relax Order */