21 	u32    reg           = 0;  in ixgbe_dcb_config_rx_arbiter_82598()  local
26 	reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;  in ixgbe_dcb_config_rx_arbiter_82598()
27 	IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);  in ixgbe_dcb_config_rx_arbiter_82598()
29 	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);  in ixgbe_dcb_config_rx_arbiter_82598()
31 	reg &= ~IXGBE_RMCS_ARBDIS;  in ixgbe_dcb_config_rx_arbiter_82598()
33 	reg |= IXGBE_RMCS_RRM;  in ixgbe_dcb_config_rx_arbiter_82598()
35 	reg |= IXGBE_RMCS_DFP;  in ixgbe_dcb_config_rx_arbiter_82598()
37 	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);  in ixgbe_dcb_config_rx_arbiter_82598()
44 		reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);  in ixgbe_dcb_config_rx_arbiter_82598()
47 			reg |= IXGBE_RT2CR_LSP;  in ixgbe_dcb_config_rx_arbiter_82598()
49 		IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);  in ixgbe_dcb_config_rx_arbiter_82598()
52 	reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);  in ixgbe_dcb_config_rx_arbiter_82598()
53 	reg |= IXGBE_RDRXCTL_RDMTS_1_2;  in ixgbe_dcb_config_rx_arbiter_82598()
54 	reg |= IXGBE_RDRXCTL_MPBEN;  in ixgbe_dcb_config_rx_arbiter_82598()
55 	reg |= IXGBE_RDRXCTL_MCEN;  in ixgbe_dcb_config_rx_arbiter_82598()
56 	IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);  in ixgbe_dcb_config_rx_arbiter_82598()
58 	reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);  in ixgbe_dcb_config_rx_arbiter_82598()
60 	reg &= ~IXGBE_RXCTRL_DMBYPS;  in ixgbe_dcb_config_rx_arbiter_82598()
61 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);  in ixgbe_dcb_config_rx_arbiter_82598()
79 	u32    reg, max_credits;  in ixgbe_dcb_config_tx_desc_arbiter_82598()  local
82 	reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);  in ixgbe_dcb_config_tx_desc_arbiter_82598()
85 	reg &= ~IXGBE_DPMCS_ARBDIS;  in ixgbe_dcb_config_tx_desc_arbiter_82598()
86 	reg |= IXGBE_DPMCS_TSOEF;  in ixgbe_dcb_config_tx_desc_arbiter_82598()
89 	reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);  in ixgbe_dcb_config_tx_desc_arbiter_82598()
91 	IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);  in ixgbe_dcb_config_tx_desc_arbiter_82598()
96 		reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;  in ixgbe_dcb_config_tx_desc_arbiter_82598()
97 		reg |= refill[i];  in ixgbe_dcb_config_tx_desc_arbiter_82598()
98 		reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;  in ixgbe_dcb_config_tx_desc_arbiter_82598()
101 			reg |= IXGBE_TDTQ2TCCR_GSP;  in ixgbe_dcb_config_tx_desc_arbiter_82598()
104 			reg |= IXGBE_TDTQ2TCCR_LSP;  in ixgbe_dcb_config_tx_desc_arbiter_82598()
106 		IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);  in ixgbe_dcb_config_tx_desc_arbiter_82598()
125 	u32 reg;  in ixgbe_dcb_config_tx_data_arbiter_82598()  local
128 	reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);  in ixgbe_dcb_config_tx_data_arbiter_82598()
130 	reg &= ~IXGBE_PDPMCS_ARBDIS;  in ixgbe_dcb_config_tx_data_arbiter_82598()
132 	reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);  in ixgbe_dcb_config_tx_data_arbiter_82598()
134 	IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);  in ixgbe_dcb_config_tx_data_arbiter_82598()
138 		reg = refill[i];  in ixgbe_dcb_config_tx_data_arbiter_82598()
139 		reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;  in ixgbe_dcb_config_tx_data_arbiter_82598()
140 		reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;  in ixgbe_dcb_config_tx_data_arbiter_82598()
143 			reg |= IXGBE_TDPT2TCCR_GSP;  in ixgbe_dcb_config_tx_data_arbiter_82598()
146 			reg |= IXGBE_TDPT2TCCR_LSP;  in ixgbe_dcb_config_tx_data_arbiter_82598()
148 		IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);  in ixgbe_dcb_config_tx_data_arbiter_82598()
152 	reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);  in ixgbe_dcb_config_tx_data_arbiter_82598()
153 	reg |= IXGBE_DTXCTL_ENDBUBD;  in ixgbe_dcb_config_tx_data_arbiter_82598()
154 	IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);  in ixgbe_dcb_config_tx_data_arbiter_82598()
168 	u32 fcrtl, reg;  in ixgbe_dcb_config_pfc_82598()  local
172 	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);  in ixgbe_dcb_config_pfc_82598()
173 	reg &= ~IXGBE_RMCS_TFCE_802_3X;  in ixgbe_dcb_config_pfc_82598()
174 	reg |= IXGBE_RMCS_TFCE_PRIORITY;  in ixgbe_dcb_config_pfc_82598()
175 	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);  in ixgbe_dcb_config_pfc_82598()
178 	reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);  in ixgbe_dcb_config_pfc_82598()
179 	reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);  in ixgbe_dcb_config_pfc_82598()
182 		reg |= IXGBE_FCTRL_RPFCE;  in ixgbe_dcb_config_pfc_82598()
184 	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);  in ixgbe_dcb_config_pfc_82598()
195 		reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;  in ixgbe_dcb_config_pfc_82598()
197 		IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);  in ixgbe_dcb_config_pfc_82598()
201 	reg = hw->fc.pause_time * 0x00010001;  in ixgbe_dcb_config_pfc_82598()
203 		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);  in ixgbe_dcb_config_pfc_82598()
221 	u32 reg = 0;  in ixgbe_dcb_config_tc_stats_82598()  local
225 	/* Receive Queues stats setting -  8 queues per statistics reg */  in ixgbe_dcb_config_tc_stats_82598()
227 		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));  in ixgbe_dcb_config_tc_stats_82598()
228 		reg |= ((0x1010101) * j);  in ixgbe_dcb_config_tc_stats_82598()
229 		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);  in ixgbe_dcb_config_tc_stats_82598()
230 		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));  in ixgbe_dcb_config_tc_stats_82598()
231 		reg |= ((0x1010101) * j);  in ixgbe_dcb_config_tc_stats_82598()
232 		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);  in ixgbe_dcb_config_tc_stats_82598()
234 	/* Transmit Queues stats setting -  4 queues per statistics reg */  in ixgbe_dcb_config_tc_stats_82598()
236 		reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));  in ixgbe_dcb_config_tc_stats_82598()
237 		reg |= ((0x1010101) * i);  in ixgbe_dcb_config_tc_stats_82598()
238 		IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);  in ixgbe_dcb_config_tc_stats_82598()