Lines Matching +full:half +full:- +full:duplex +full:- +full:capable
1 /* SPDX-License-Identifier: GPL-2.0 */
90 /* Loop limit on how long we wait for auto-negotiation to complete */
137 #define IGC_CTRL_FRCDPX 0x00001000 /* Force Duplex */
161 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
162 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
163 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
164 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
172 /* 1000BASE-T Control Register */
176 /* 1000BASE-T Status Register */
223 #define IGC_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
239 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
288 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
334 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
406 #define IGC_DTXMXPKTSZ_DEFAULT 0x98 /* 9728-byte Jumbo frames */
595 #define IGC_PTM_STAT_ADJUST_CYC BIT(5) /* 1588 timer adjusted during non-1st PTM cycle */
601 /* GPY211 - I225 defines */
614 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
615 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
619 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
640 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
641 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
659 /* EEE Link-Partner Ability */
664 #define IGC_N0_QUEUE -1
695 /* Minimum time for 100BASE-T where no data will be transmit following move out