Lines Matching +full:0 +full:x40900000
13 #define IGC_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */
14 #define IGC_CTRL_EXT_SDP3_DIR 0x00000800 /* SDP3 Data direction */
15 #define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
19 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
22 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
23 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
24 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
25 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
26 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_FLX0 BIT(16) /* Flexible Filter 0 Enable */
39 #define IGC_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
42 #define IGC_WUS_EX 0x00000004 /* Directed Exact */
43 #define IGC_WUS_ARPD 0x00000020 /* Directed ARP Request */
44 #define IGC_WUS_IPV4 0x00000040 /* Directed IPv4 */
45 #define IGC_WUS_IPV6 0x00000080 /* Directed IPv6 */
46 #define IGC_WUS_NSD 0x00000400 /* Directed IPv6 Neighbor Solicitation */
57 #define IGC_WUPL_MASK 0x00000FFF
97 #define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004
99 #define IGC_STATUS_GIO_MASTER_ENABLE 0x00080000
108 #define IGC_RAH_RAH_MASK 0x0000FFFF
109 #define IGC_RAH_ASEL_MASK 0x00030000
111 #define IGC_RAH_QSEL_MASK 0x000C0000
114 #define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */
120 #define IGC_SUCCESS 0
132 #define IGC_CTRL_RST 0x04000000 /* Global reset */
134 #define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */
135 #define IGC_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
136 #define IGC_CTRL_FRCSPD 0x00000800 /* Force Speed */
137 #define IGC_CTRL_FRCDPX 0x00001000 /* Force Duplex */
138 #define IGC_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
140 #define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
141 #define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
143 #define IGC_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */
144 #define IGC_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */
147 #define MAX_JUMBO_FRAME_SIZE 0x2600
150 #define IGC_PBA_34K 0x0022
153 #define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
154 #define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
157 #define IGC_SWFW_EEP_SM 0x1
158 #define IGC_SWFW_PHY0_SM 0x2
161 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
162 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
163 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
164 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
165 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
166 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
169 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
170 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
173 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
174 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
177 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
180 #define STANDARD_AN_REG_MASK 0x0007 /* MMD */
182 #define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */
187 #define IGC_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
188 #define IGC_EECD_REQ 0x00000040 /* NVM Access Request */
189 #define IGC_EECD_GNT 0x00000080 /* NVM Access Grant */
190 /* NVM Addressing bits based on type 0=small, 1=large */
191 #define IGC_EECD_ADDR_BITS 0x00000400
193 #define IGC_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
195 #define IGC_EECD_FLUPD_I225 0x00800000 /* Update FLASH */
196 #define IGC_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done*/
197 #define IGC_EECD_FLASH_DETECTED_I225 0x00080000 /* FLASH detected */
206 #define IGC_NVM_POLL_READ 0 /* Flag for polling for read complete */
210 #define NVM_CHECKSUM_REG 0x003F
212 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
213 #define NVM_SUM 0xBABA
223 #define IGC_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
224 #define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
225 #define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
227 #define IGC_STATUS_TXOFF 0x00000010 /* transmission paused */
228 #define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
229 #define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
230 #define IGC_STATUS_SPEED_2500 0x00400000 /* Speed 2.5Gb/s */
240 #define ADVERTISE_10_HALF 0x0001
241 #define ADVERTISE_10_FULL 0x0002
242 #define ADVERTISE_100_HALF 0x0004
243 #define ADVERTISE_100_FULL 0x0008
244 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
245 #define ADVERTISE_1000_FULL 0x0020
246 #define ADVERTISE_2500_HALF 0x0040 /* Not used, just FYI */
247 #define ADVERTISE_2500_FULL 0x0080
256 #define IGC_ICR_TXDW BIT(0) /* Transmit desc written back */
260 #define IGC_ICR_RXDMT0 BIT(4) /* Rx desc min. threshold (0) */
262 #define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
288 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
289 #define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */
295 #define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
296 #define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
297 #define IGC_IVAR_VALID 0x80
298 #define IGC_GPIE_NSICR 0x00000001
299 #define IGC_GPIE_MSIX_MODE 0x00000010
300 #define IGC_GPIE_EIAME 0x40000000
301 #define IGC_GPIE_PBA 0x80000000
304 #define IGC_RXD_STAT_DD 0x01 /* Descriptor Done */
307 #define IGC_TXD_DTYP_D 0x00100000 /* Data Descriptor */
308 #define IGC_TXD_DTYP_C 0x00000000 /* Context Descriptor */
309 #define IGC_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
310 #define IGC_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
311 #define IGC_TXD_CMD_EOP 0x01000000 /* End of Packet */
312 #define IGC_TXD_CMD_IC 0x04000000 /* Insert Checksum */
313 #define IGC_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
314 #define IGC_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
315 #define IGC_TXD_STAT_DD 0x00000001 /* Descriptor Done */
316 #define IGC_TXD_CMD_TCP 0x01000000 /* TCP packet */
317 #define IGC_TXD_CMD_IP 0x02000000 /* IP packet */
318 #define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
319 #define IGC_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
321 #define IGC_TXD_PTP2_TIMER_1 0x00000020
327 #define IGC_ADVTXD_TSN_CNTX_FIRST 0x00000080
330 #define IGC_TCTL_EN 0x00000002 /* enable Tx */
331 #define IGC_TCTL_PSP 0x00000008 /* pad short packets */
332 #define IGC_TCTL_CT 0x00000ff0 /* collision threshold */
333 #define IGC_TCTL_COLD 0x003ff000 /* collision distance */
334 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
337 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
338 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
339 #define FLOW_CONTROL_TYPE 0x8808
341 #define IGC_FCRTL_XONE 0x80000000
344 #define IGC_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
345 #define IGC_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
348 #define IGC_RCTL_RST 0x00000001 /* Software reset */
349 #define IGC_RCTL_EN 0x00000002 /* enable */
350 #define IGC_RCTL_SBP 0x00000004 /* store bad packet */
351 #define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */
352 #define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */
353 #define IGC_RCTL_LPE 0x00000020 /* long packet enable */
354 #define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
355 #define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
357 #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
358 #define IGC_RCTL_BAM 0x00008000 /* broadcast enable */
361 #define IGC_SRRCTL_TIMESTAMP 0x40000000
362 #define IGC_SRRCTL_TIMER1SEL(timer) (((timer) & 0x3) << 14)
363 #define IGC_SRRCTL_TIMER0SEL(timer) (((timer) & 0x3) << 17)
366 #define IGC_RXD_STAT_EOP 0x02 /* End of Packet */
367 #define IGC_RXD_STAT_IXSM 0x04 /* Ignore checksum */
368 #define IGC_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
369 #define IGC_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
370 #define IGC_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
372 #define IGC_RXDEXT_STATERR_LB 0x00040000
375 #define IGC_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
377 #define IGC_RXDEXT_STATERR_L4E 0x20000000
378 #define IGC_RXDEXT_STATERR_IPE 0x40000000
379 #define IGC_RXDEXT_STATERR_RXE 0x80000000
381 #define IGC_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
382 #define IGC_MRQC_RSS_FIELD_IPV4 0x00020000
383 #define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
384 #define IGC_MRQC_RSS_FIELD_IPV6 0x00100000
385 #define IGC_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
388 #define IGC_RFCTL_IPV6_EX_DIS 0x00010000
389 #define IGC_RFCTL_LEF 0x00040000
391 #define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
394 #define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */
395 #define IGC_RCTL_DPF 0x00400000 /* discard pause frames */
396 #define IGC_RCTL_PMCF 0x00800000 /* pass MAC control frames */
397 #define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
399 #define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
400 #define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
401 #define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
403 #define IGC_TXPBSIZE_TSN 0x04145145 /* 5k bytes buffer for each queue */
405 #define IGC_DTXMXPKTSZ_TSN 0x19 /* 1600 bytes of max TX DMA packet size */
406 #define IGC_DTXMXPKTSZ_DEFAULT 0x98 /* 9728-byte Jumbo frames */
409 #define IGC_RETX_CTL 0x041C
410 #define IGC_RETX_CTL_WATERMARK_MASK 0xF
412 #define IGC_RETX_CTL_QBVFULLEN 0x1000 /* Enable QBV Retry Buffer Full Threshold */
418 #define IGC_TXOFFSET_SPEED_10 0x000034BC
419 #define IGC_TXOFFSET_SPEED_100 0x00000578
420 #define IGC_TXOFFSET_SPEED_1000 0x0000012C
421 #define IGC_TXOFFSET_SPEED_2500 0x00000578
424 #define IGC_TSICR_SYS_WRAP BIT(0) /* SYSTIM Wrap around. */
426 #define IGC_TSICR_TT0 BIT(3) /* Target Time 0 Trigger. */
428 #define IGC_TSICR_AUTT0 BIT(5) /* Auxiliary Timestamp 0 Taken. */
433 #define IGC_FTQF_VF_BP 0x00008000
434 #define IGC_FTQF_1588_TIME_STAMP 0x08000000
435 #define IGC_FTQF_MASK 0xF0000000
436 #define IGC_FTQF_MASK_PROTO_BP 0x10000000
439 #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
440 #define IGC_TSYNCRXCTL_TYPE_L2_V2 0x00
441 #define IGC_TSYNCRXCTL_TYPE_L4_V1 0x02
442 #define IGC_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
443 #define IGC_TSYNCRXCTL_TYPE_ALL 0x08
444 #define IGC_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
445 #define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
446 #define IGC_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */
447 #define IGC_TSYNCRXCTL_RXSYNSIG 0x00000400 /* Sample RX tstamp in PHY sop */
450 #define IGC_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF
451 #define IGC_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00
452 #define IGC_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
455 #define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
456 #define IGC_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */
458 #define IGC_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
461 #define IGC_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
462 #define IGC_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
465 #define IGC_TSYNCTXCTL_TXTT_0 0x00000001 /* Tx timestamp reg 0 valid */
466 #define IGC_TSYNCTXCTL_TXTT_1 0x00000002 /* Tx timestamp reg 1 valid */
467 #define IGC_TSYNCTXCTL_TXTT_2 0x00000004 /* Tx timestamp reg 2 valid */
468 #define IGC_TSYNCTXCTL_TXTT_3 0x00000008 /* Tx timestamp reg 3 valid */
469 #define IGC_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
470 #define IGC_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */
471 #define IGC_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */
472 #define IGC_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */
473 #define IGC_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */
474 #define IGC_TSYNCTXCTL_TXSYNSIG 0x00000020 /* Sample TX tstamp in PHY sop */
481 #define IGC_AUX_IO_TIMER_SEL_SYSTIM0 (0u << 30) /* Select SYSTIM0 for auxiliary time stamp */
485 #define IGC_TT_IO_TIMER_SEL_SYSTIM0 (0u << 30) /* Select SYSTIM0 for target time stamp */
491 #define IGC_TSAUXC_EN_TT0 BIT(0) /* Enable target time 0. */
493 #define IGC_TSAUXC_EN_CLK0 BIT(2) /* Enable Configurable Frequency Clock 0. */
494 #define IGC_TSAUXC_ST0 BIT(4) /* Start Clock 0 Toggle on Target Time 0. */
497 #define IGC_TSAUXC_EN_TS0 BIT(8) /* Enable hardware timestamp 0. */
499 #define IGC_TSAUXC_EN_TS1 BIT(10) /* Enable hardware timestamp 0. */
509 #define IGC_AUX0_SEL_SDP0 (0u << 0) /* Assign SDP0 to auxiliary time stamp 0. */
510 #define IGC_AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */
511 #define IGC_AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */
512 #define IGC_AUX0_SEL_SDP3 (3u << 0) /* Assign SDP3 to auxiliary time stamp 0. */
513 #define IGC_AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */
514 #define IGC_AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */
519 #define IGC_TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */
521 #define IGC_TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
524 #define IGC_TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */
526 #define IGC_TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
529 #define IGC_TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */
531 #define IGC_TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
534 #define IGC_TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */
536 #define IGC_TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
541 #define IGC_TQAVCTRL_TRANSMIT_MODE_TSN 0x00000001
542 #define IGC_TQAVCTRL_ENHANCED_QAV 0x00000008
543 #define IGC_TQAVCTRL_FUTSCDDIS 0x00000080
545 #define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x00000001
546 #define IGC_TXQCTL_STRICT_CYCLE 0x00000002
547 #define IGC_TXQCTL_STRICT_END 0x00000004
548 #define IGC_TXQCTL_QAV_SEL_MASK 0x000000C0
549 #define IGC_TXQCTL_QAV_SEL_CBS0 0x00000080
550 #define IGC_TXQCTL_QAV_SEL_CBS1 0x000000C0
552 #define IGC_TQAVCC_IDLESLOPE_MASK 0xFFFF
557 #define IGC_TXARB_TXQ_PRIO_0_MASK GENMASK(1, 0)
567 #define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
568 #define IGC_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
574 #define IGC_PTM_CTRL_SHRT_CYC(usec) (((usec) & 0x3f) << 2)
575 #define IGC_PTM_CTRL_PTM_TO(usec) (((usec) & 0xff) << 8)
582 #define IGC_PCIE_DIG_DELAY_DEFAULT 0x01440000
585 #define IGC_PCIE_PHY_DELAY_DEFAULT 0x40900000
587 #define IGC_TIMADJ_ADJUST_METH 0x40000000
590 #define IGC_PTM_STAT_VALID BIT(0) /* PTM Status */
598 #define IGC_PTM_CYCLE_CTRL_CYC_TIME(msec) ((msec) & 0x3ff) /* PTM Cycle Time (msec) */
602 #define GPY_MMD_MASK 0xFFFF0000
604 #define GPY_REG_MASK 0x0000FFFF
606 #define IGC_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
609 #define IGC_FACTPS_MNGCG 0x20000000
610 #define IGC_FWSM_MODE_MASK 0xE
614 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
615 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
618 #define PHY_REVISION_MASK 0xFFFFFFF0
619 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
623 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
624 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
625 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
628 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
629 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
630 #define IGC_PHY_RST_COMP 0x0100 /* Internal PHY reset completion */
634 #define PHY_CONTROL 0x00 /* Control Register */
635 #define PHY_STATUS 0x01 /* Status Register */
636 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
637 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
638 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
639 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
640 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
641 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
644 #define IGC_MDIC_DATA_MASK 0x0000FFFF
645 #define IGC_MDIC_REG_MASK 0x001F0000
647 #define IGC_MDIC_PHY_MASK 0x03E00000
649 #define IGC_MDIC_OP_WRITE 0x04000000
650 #define IGC_MDIC_OP_READ 0x08000000
651 #define IGC_MDIC_READY 0x10000000
652 #define IGC_MDIC_ERROR 0x40000000
655 #define IGC_EEE_2500BT_MASK BIT(0)
660 #define IGC_LP_EEE_2500BT_MASK BIT(0)
670 #define IGC_VLANPQF_VALID(_n) (0x1 << (3 + (_n) * 4))
671 #define IGC_VLANPQF_QUEUE_MASK 0x03
674 #define IGC_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type:1=IPv4 */
675 #define IGC_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet Type of TCP */
676 #define IGC_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
682 #define IGC_IPCNFG_EEE_2_5G_AN 0x00000010 /* IPCNFG EEE Ena 2.5G AN */
683 #define IGC_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */
684 #define IGC_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */
685 #define IGC_EEER_EEE_NEG 0x20000000 /* EEE capability nego */
686 #define IGC_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */
687 #define IGC_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
688 #define IGC_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */
689 #define IGC_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */
692 #define IGC_LTRC_EEEMS_EN 0x00000020 /* Enable EEE LTR max send */
693 #define IGC_RXPBS_SIZE_I225_MASK 0x0000003F /* Rx packet buffer size */
694 #define IGC_TW_SYSTEM_1000_MASK 0x000000FF
698 #define IGC_TW_SYSTEM_100_MASK 0x0000FF00
708 #define IGC_LTRMINV_LTRV_MASK 0x000003FF /* LTR minimum value */
709 #define IGC_LTRMAXV_LTRV_MASK 0x000003FF /* LTR maximum value */
710 #define IGC_LTRMINV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */
712 #define IGC_LTRMAXV_LSNP_REQ 0x00008000 /* LTR Snoop Requirement */