Lines Matching +full:0 +full:x00300000

36 #define IGC_ADVTXD_MAC_TSTAMP	0x00080000 /* IEEE1588 Timestamp packet */
37 #define IGC_ADVTXD_TSTAMP_REG_1	0x00010000 /* Select register 1 for timestamp */
38 #define IGC_ADVTXD_TSTAMP_REG_2	0x00020000 /* Select register 2 for timestamp */
39 #define IGC_ADVTXD_TSTAMP_REG_3	0x00030000 /* Select register 3 for timestamp */
40 #define IGC_ADVTXD_TSTAMP_TIMER_1	0x00010000 /* Select timer 1 for timestamp */
41 #define IGC_ADVTXD_TSTAMP_TIMER_2	0x00020000 /* Select timer 2 for timestamp */
42 #define IGC_ADVTXD_TSTAMP_TIMER_3	0x00030000 /* Select timer 3 for timestamp */
44 #define IGC_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
45 #define IGC_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
46 #define IGC_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
47 #define IGC_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
48 #define IGC_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
49 #define IGC_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
50 #define IGC_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
51 #define IGC_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
89 #define IGC_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
90 #define IGC_TXDCTL_SWFLUSH	0x04000000 /* Transmit Software Flush */
93 #define IGC_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
94 #define IGC_RXDCTL_SWFLUSH		0x04000000 /* Receive Software Flush */
97 #define IGC_SRRCTL_BSIZEPKT_MASK	GENMASK(6, 0)