Lines Matching +full:0 +full:x000fffff
112 TEST_REG = 0,
129 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0)
147 0 : rd32(E1000_STATUS); in igb_get_link_ksettings()
240 /* MDI-X => 2; MDI =>1; Invalid =>0 */ in igb_get_link_ksettings()
257 return 0; in igb_get_link_ksettings()
338 /* fix up the value for auto (3 => 0) as zero is mapped in igb_set_link_ksettings()
355 return 0; in igb_set_link_ksettings()
399 int retval = 0; in igb_set_pauseparam()
435 for (i = 0; i < adapter->num_rx_queues; i++) { in igb_set_pauseparam()
472 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); in igb_get_regs()
477 regs_buff[0] = rd32(E1000_CTRL); in igb_get_regs()
615 for (i = 0; i < 4; i++) in igb_get_regs()
617 for (i = 0; i < 4; i++) in igb_get_regs()
619 for (i = 0; i < 4; i++) in igb_get_regs()
621 for (i = 0; i < 4; i++) in igb_get_regs()
623 for (i = 0; i < 4; i++) in igb_get_regs()
625 for (i = 0; i < 4; i++) in igb_get_regs()
627 for (i = 0; i < 4; i++) in igb_get_regs()
629 for (i = 0; i < 4; i++) in igb_get_regs()
632 for (i = 0; i < 10; i++) in igb_get_regs()
634 for (i = 0; i < 8; i++) in igb_get_regs()
636 for (i = 0; i < 8; i++) in igb_get_regs()
638 for (i = 0; i < 16; i++) in igb_get_regs()
640 for (i = 0; i < 16; i++) in igb_get_regs()
643 for (i = 0; i < 4; i++) in igb_get_regs()
645 for (i = 0; i < 4; i++) in igb_get_regs()
647 for (i = 0; i < 4; i++) in igb_get_regs()
649 for (i = 0; i < 4; i++) in igb_get_regs()
651 for (i = 0; i < 4; i++) in igb_get_regs()
653 for (i = 0; i < 4; i++) in igb_get_regs()
655 for (i = 0; i < 4; i++) in igb_get_regs()
657 for (i = 0; i < 4; i++) in igb_get_regs()
659 for (i = 0; i < 4; i++) in igb_get_regs()
662 for (i = 0; i < 4; i++) in igb_get_regs()
664 for (i = 0; i < 4; i++) in igb_get_regs()
666 for (i = 0; i < 32; i++) in igb_get_regs()
668 for (i = 0; i < 128; i++) in igb_get_regs()
670 for (i = 0; i < 128; i++) in igb_get_regs()
672 for (i = 0; i < 4; i++) in igb_get_regs()
688 for (i = 0; i < 12; i++) in igb_get_regs()
690 for (i = 0; i < 4; i++) in igb_get_regs()
692 for (i = 0; i < 12; i++) in igb_get_regs()
694 for (i = 0; i < 12; i++) in igb_get_regs()
696 for (i = 0; i < 12; i++) in igb_get_regs()
698 for (i = 0; i < 12; i++) in igb_get_regs()
700 for (i = 0; i < 12; i++) in igb_get_regs()
702 for (i = 0; i < 12; i++) in igb_get_regs()
705 for (i = 0; i < 12; i++) in igb_get_regs()
707 for (i = 0; i < 12; i++) in igb_get_regs()
709 for (i = 0; i < 12; i++) in igb_get_regs()
711 for (i = 0; i < 12; i++) in igb_get_regs()
713 for (i = 0; i < 12; i++) in igb_get_regs()
715 for (i = 0; i < 12; i++) in igb_get_regs()
717 for (i = 0; i < 12; i++) in igb_get_regs()
719 for (i = 0; i < 12; i++) in igb_get_regs()
740 int ret_val = 0; in igb_get_eeprom()
743 if (eeprom->len == 0) in igb_get_eeprom()
761 for (i = 0; i < last_word - first_word + 1; i++) { in igb_get_eeprom()
770 for (i = 0; i < last_word - first_word + 1; i++) in igb_get_eeprom()
787 int max_len, first_word, last_word, ret_val = 0; in igb_set_eeprom()
790 if (eeprom->len == 0) in igb_set_eeprom()
816 &eeprom_buff[0]); in igb_set_eeprom()
819 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { in igb_set_eeprom()
830 for (i = 0; i < last_word - first_word + 1; i++) in igb_set_eeprom()
835 for (i = 0; i < last_word - first_word + 1; i++) in igb_set_eeprom()
842 if (ret_val == 0) in igb_set_eeprom()
889 int i, err = 0; in igb_set_ringparam()
906 return 0; in igb_set_ringparam()
913 for (i = 0; i < adapter->num_tx_queues; i++) in igb_set_ringparam()
915 for (i = 0; i < adapter->num_rx_queues; i++) in igb_set_ringparam()
941 for (i = 0; i < adapter->num_tx_queues; i++) { in igb_set_ringparam()
956 for (i = 0; i < adapter->num_tx_queues; i++) { in igb_set_ringparam()
967 for (i = 0; i < adapter->num_rx_queues; i++) { in igb_set_ringparam()
983 for (i = 0; i < adapter->num_rx_queues; i++) { in igb_set_ringparam()
1011 * spaced 0x100 bytes apart, or in contiguous tables. We assume
1029 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1030 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1031 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1032 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1033 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1034 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1036 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1037 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1038 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1039 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1040 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1041 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1042 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1043 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1044 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1045 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1046 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1047 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1048 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1049 0xFFFFFFFF, 0xFFFFFFFF },
1050 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1051 0x900FFFFF, 0xFFFFFFFF },
1052 { E1000_MTA, 0, 128, TABLE32_TEST,
1053 0xFFFFFFFF, 0xFFFFFFFF },
1054 { 0, 0, 0, 0, 0 }
1059 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1060 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1061 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1062 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1063 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1064 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1065 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1066 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1067 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1068 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1070 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1071 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1072 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1073 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1074 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1075 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1076 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1077 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1078 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1079 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1080 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1081 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1082 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1083 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1084 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1085 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1086 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1087 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1088 0xFFFFFFFF, 0xFFFFFFFF },
1089 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1090 0xC3FFFFFF, 0xFFFFFFFF },
1091 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1092 0xFFFFFFFF, 0xFFFFFFFF },
1093 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1094 0xC3FFFFFF, 0xFFFFFFFF },
1095 { E1000_MTA, 0, 128, TABLE32_TEST,
1096 0xFFFFFFFF, 0xFFFFFFFF },
1097 { 0, 0, 0, 0 }
1102 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1103 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1104 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1105 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1106 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1107 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1108 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1109 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1110 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1111 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1113 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1114 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1115 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1116 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1117 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1118 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1119 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1120 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1121 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1122 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1123 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1124 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1125 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1126 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1127 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1128 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1129 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1130 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1131 0xFFFFFFFF, 0xFFFFFFFF },
1132 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1133 0x83FFFFFF, 0xFFFFFFFF },
1134 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1135 0xFFFFFFFF, 0xFFFFFFFF },
1136 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1137 0x83FFFFFF, 0xFFFFFFFF },
1138 { E1000_MTA, 0, 128, TABLE32_TEST,
1139 0xFFFFFFFF, 0xFFFFFFFF },
1140 { 0, 0, 0, 0 }
1145 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1146 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1147 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1148 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1149 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1150 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1151 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1152 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1153 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1154 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1156 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1158 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0,
1161 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1162 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1163 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1164 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
1165 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1166 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1167 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1168 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1169 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1170 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1171 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1172 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1173 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1174 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1175 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1176 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1177 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1178 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1179 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1180 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1181 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1182 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1183 { 0, 0, 0, 0 }
1188 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1189 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1190 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1191 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1192 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1193 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1194 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1196 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1199 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1200 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1201 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1202 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1203 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1204 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1205 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1206 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1207 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1208 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1209 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1210 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1211 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1212 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1213 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1214 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1215 { 0, 0, 0, 0 }
1224 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; in reg_pattern_test()
1225 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { in reg_pattern_test()
1230 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", in reg_pattern_test()
1250 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", in reg_set_and_check()
1263 } while (0)
1269 } while (0)
1282 toggle = 0x7FEFF3FF; in igb_reg_test()
1287 toggle = 0x7FEFF3FF; in igb_reg_test()
1291 toggle = 0x7FEFF3FF; in igb_reg_test()
1295 toggle = 0x7FFFF3FF; in igb_reg_test()
1299 toggle = 0x7FFFF3FF; in igb_reg_test()
1314 "failed STATUS register test got: 0x%08X expected: 0x%08X\n", in igb_reg_test()
1326 for (i = 0; i < test->array_len; i++) { in igb_reg_test()
1365 *data = 0; in igb_reg_test()
1366 return 0; in igb_reg_test()
1373 *data = 0; in igb_eeprom_test()
1380 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) in igb_eeprom_test()
1385 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) in igb_eeprom_test()
1407 u32 mask, ics_mask, i = 0, shared_int = true; in igb_intr_test()
1410 *data = 0; in igb_intr_test()
1414 if (request_irq(adapter->msix_entries[0].vector, in igb_intr_test()
1415 igb_test_intr, 0, netdev->name, adapter)) { in igb_intr_test()
1420 wr32(E1000_EIMS, BIT(0)); in igb_intr_test()
1424 igb_test_intr, 0, netdev->name, adapter)) { in igb_intr_test()
1440 wr32(E1000_IMC, ~0); in igb_intr_test()
1447 ics_mask = 0x37F47EDD; in igb_intr_test()
1450 ics_mask = 0x77D4FBFD; in igb_intr_test()
1453 ics_mask = 0x77DCFED5; in igb_intr_test()
1459 ics_mask = 0x77DCFED5; in igb_intr_test()
1462 ics_mask = 0x7FFFFFFF; in igb_intr_test()
1481 adapter->test_icr = 0; in igb_intr_test()
1484 wr32(E1000_ICR, ~0); in igb_intr_test()
1503 adapter->test_icr = 0; in igb_intr_test()
1506 wr32(E1000_ICR, ~0); in igb_intr_test()
1525 adapter->test_icr = 0; in igb_intr_test()
1528 wr32(E1000_ICR, ~0); in igb_intr_test()
1543 wr32(E1000_IMC, ~0); in igb_intr_test()
1549 free_irq(adapter->msix_entries[0].vector, adapter); in igb_intr_test()
1594 /* set the default queue to queue 0 of PF */ in igb_setup_desc_rings()
1603 return 0; in igb_setup_desc_rings()
1615 igb_write_phy_reg(hw, 29, 0x001F); in igb_phy_disable_receiver()
1616 igb_write_phy_reg(hw, 30, 0x8FFC); in igb_phy_disable_receiver()
1617 igb_write_phy_reg(hw, 29, 0x001A); in igb_phy_disable_receiver()
1618 igb_write_phy_reg(hw, 30, 0x8FF0); in igb_phy_disable_receiver()
1624 u32 ctrl_reg = 0; in igb_integrated_phy_loopback()
1631 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); in igb_integrated_phy_loopback()
1633 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); in igb_integrated_phy_loopback()
1635 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); in igb_integrated_phy_loopback()
1638 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0); in igb_integrated_phy_loopback()
1639 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); in igb_integrated_phy_loopback()
1643 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041); in igb_integrated_phy_loopback()
1650 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); in igb_integrated_phy_loopback()
1673 return 0; in igb_integrated_phy_loopback()
1745 return 0; in igb_setup_loopback_test()
1791 memset(skb->data, 0xFF, frame_size); in igb_create_lbtest_frame()
1793 memset(&skb->data[frame_size], 0xAA, frame_size - 1); in igb_create_lbtest_frame()
1794 skb->data[frame_size + 10] = 0xBE; in igb_create_lbtest_frame()
1795 skb->data[frame_size + 12] = 0xAF; in igb_create_lbtest_frame()
1808 if (data[3] != 0xFF || in igb_check_lbtest_frame()
1809 data[frame_size + 10] != 0xBE || in igb_check_lbtest_frame()
1810 data[frame_size + 12] != 0xAF) in igb_check_lbtest_frame()
1825 u16 rx_ntc, tx_ntc, count = 0; in igb_clean_test_rings()
1863 dma_unmap_len_set(tx_buffer_info, len, 0); in igb_clean_test_rings()
1868 rx_ntc = 0; in igb_clean_test_rings()
1871 tx_ntc = 0; in igb_clean_test_rings()
1892 int ret_val = 0; in igb_run_loopback_test()
1916 for (j = 0; j <= lc; j++) { /* loop count loop */ in igb_run_loopback_test()
1918 good_cnt = 0; in igb_run_loopback_test()
1921 for (i = 0; i < 64; i++) { in igb_run_loopback_test()
1957 *data = 0; in igb_loopback_test()
1964 *data = 0; in igb_loopback_test()
1985 *data = 0; in igb_link_test()
1987 int i = 0; in igb_link_test()
2088 data[TEST_LINK] = 0; in igb_diag_test()
2091 data[TEST_REG] = 0; in igb_diag_test()
2092 data[TEST_EEP] = 0; in igb_diag_test()
2093 data[TEST_IRQ] = 0; in igb_diag_test()
2094 data[TEST_LOOP] = 0; in igb_diag_test()
2105 wol->wolopts = 0; in igb_get_wol()
2140 return wol->wolopts ? -EOPNOTSUPP : 0; in igb_set_wol()
2143 adapter->wol = 0; in igb_set_wol()
2157 return 0; in igb_set_wol()
2161 #define IGB_LED_ON 0
2186 return 0; in igb_set_phys_id()
2213 if (ec->rx_coalesce_usecs == 0) { in igb_set_coalesce()
2232 for (i = 0; i < adapter->num_q_vectors; i++) { in igb_set_coalesce()
2244 return 0; in igb_set_coalesce()
2266 return 0; in igb_get_coalesce()
2274 return 0; in igb_nway_reset()
2304 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { in igb_get_ethtool_stats()
2309 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { in igb_get_ethtool_stats()
2314 for (j = 0; j < adapter->num_tx_queues; j++) { in igb_get_ethtool_stats()
2332 for (j = 0; j < adapter->num_rx_queues; j++) { in igb_get_ethtool_stats()
2358 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) in igb_get_strings()
2360 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) in igb_get_strings()
2362 for (i = 0; i < adapter->num_tx_queues; i++) { in igb_get_strings()
2367 for (i = 0; i < adapter->num_rx_queues; i++) { in igb_get_strings()
2395 return 0; in igb_get_ts_info()
2423 return 0; in igb_get_ts_info()
2476 return 0; in igb_get_ethtool_nfc_entry()
2486 int cnt = 0; in igb_get_ethtool_nfc_all()
2500 return 0; in igb_get_ethtool_nfc_all()
2506 cmd->data = 0; in igb_get_rss_hash_opts()
2542 return 0; in igb_get_rss_hash_opts()
2554 ret = 0; in igb_get_rxnfc()
2558 ret = 0; in igb_get_rxnfc()
2604 case 0: in igb_set_rss_hash_opt()
2619 case 0: in igb_set_rss_hash_opt()
2677 return 0; in igb_set_rss_hash_opt()
2689 for (i = 0; i < MAX_ETYPE_FILTER; ++i) { in igb_rxnfc_write_etype_filter()
2715 return 0; in igb_rxnfc_write_etype_filter()
2743 return 0; in igb_rxnfc_write_vlan_prio_filter()
2767 input->action, 0); in igb_add_filter()
2768 err = min_t(int, err, 0); in igb_add_filter()
2778 err = min_t(int, err, 0); in igb_add_filter()
2838 input->action, 0); in igb_erase_filter()
2840 return 0; in igb_erase_filter()
2870 /* If no input this was a delete, err should be 0 if a rule was in igb_update_ethtool_nfc_entry()
2888 return 0; in igb_update_ethtool_nfc_entry()
2898 int err = 0; in igb_add_ethtool_nfc_entry()
2977 return 0; in igb_add_ethtool_nfc_entry()
3101 return 0; in igb_get_eee()
3119 memset(&eee_curr, 0, sizeof(struct ethtool_keee)); in igb_set_eee()
3184 return 0; in igb_set_eee()
3192 u32 status = 0; in igb_get_module_info()
3211 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) { in igb_get_module_info()
3212 …hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module t… in igb_get_module_info()
3216 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) { in igb_get_module_info()
3226 return 0; in igb_get_module_info()
3234 u32 status = 0; in igb_get_module_eeprom()
3237 int i = 0; in igb_get_module_eeprom()
3239 if (ee->len == 0) in igb_get_module_eeprom()
3251 for (i = 0; i < last_word - first_word + 1; i++) { in igb_get_module_eeprom()
3266 return 0; in igb_get_module_eeprom()
3282 return 0; in igb_get_rxfh()
3283 for (i = 0; i < IGB_RETA_SIZE; i++) in igb_get_rxfh()
3286 return 0; in igb_get_rxfh()
3292 u32 reg = E1000_RETA(0); in igb_write_rss_indir_tbl()
3293 u32 shift = 0; in igb_write_rss_indir_tbl()
3294 int i = 0; in igb_write_rss_indir_tbl()
3310 u32 val = 0; in igb_write_rss_indir_tbl()
3313 for (j = 3; j >= 0; j--) { in igb_write_rss_indir_tbl()
3339 return 0; in igb_set_rxfh()
3354 for (i = 0; i < IGB_RETA_SIZE; i++) in igb_set_rxfh()
3359 for (i = 0; i < IGB_RETA_SIZE; i++) in igb_set_rxfh()
3364 return 0; in igb_set_rxfh()
3394 unsigned int max_combined = 0; in igb_set_channels()
3419 return 0; in igb_set_channels()
3425 u32 priv_flags = 0; in igb_get_priv_flags()
3450 return 0; in igb_set_priv_flags()