intel/igb/e1000_defines.h

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
123 #define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
184 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
185 #define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
186 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
188 #define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
189 #define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
190 #define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
191 #define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
193 /* Reset both PHY ports, through PHYRST_N pin */
194 /* enable link status from external LINK_0 and LINK_1 pins */
198 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */
205 #define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
250 /* BMC external code execution disabled */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
271 /* 1000/H is not supported, nor spec-compliant. */
309 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
318 /* DMA Coalescing BMC-to-OS Watchdog Enable */
501 /* Loop limit on how long we wait for auto-negotiation to complete */
507 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
650 /* PHY Control Register */
656 #define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
661 /* PHY Status Register */
679 /* 1000BASE-T Control Register */
682 #define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
683 					/* 0=Configure PHY as Slave */
687 /* 1000BASE-T Status Register */
692 /* PHY 1000 MII Register/Bit Definitions */
693 /* PHY Registers defined by IEEE */
696 #define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
697 #define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
700 #define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
701 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
812 #define NVM_WORD24_EXT_MDIO         0x0004 /* MDIO accesses routed external */
832 /* NVM Commands - Microwire */
834 /* NVM Commands - SPI */
838 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
866 /* PCI/PCI-X/PCI-EX Config space */
871 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
874 /* Bit definitions for valid PHY IDs. */
876  * E = External
891 #define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
892 #define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
893 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
898 /* M88E1000 PHY Specific Control Register */
904 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
908 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
909  * 0=Normal 10BASE-T Rx Threshold
911 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
914 /* M88E1000 PHY Specific Status Register */
919  * 1 = 50-80M
920  * 2 = 80-110M
921  * 3 = 110-140M
930 /* M88E1000 Extended PHY Specific Control Register */
934  * within 1ms in 1000BASE-T
948 /* Intel i347-AT4 Registers */
950 #define I347AT4_PCDL0                  0x10 /* Pair 0 PHY Cable Diagnostics Length */
951 #define I347AT4_PCDL1                  0x11 /* Pair 1 PHY Cable Diagnostics Length */
952 #define I347AT4_PCDL2                  0x12 /* Pair 2 PHY Cable Diagnostics Length */
953 #define I347AT4_PCDL3                  0x13 /* Pair 3 PHY Cable Diagnostics Length */
954 #define I347AT4_PCDC                   0x15 /* PHY Cable Diagnostics Control */
957 /* i347-AT4 Extended PHY Specific Control Register */
973 /* i347-AT4 PHY Cable Diagnostics Control */
1036 /* Tx Rate-Scheduler Config fields */
1053 /* Fetch Time Delta - bits 31:16