intel/igb/e1000_defines.h

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
271 /* 1000/H is not supported, nor spec-compliant. */
309 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
318 /* DMA Coalescing BMC-to-OS Watchdog Enable */
501 /* Loop limit on how long we wait for auto-negotiation to complete */
642 /* mPHY PCS CLK Register */
643 #define E1000_MPHY_PCS_CLK_REG_OFFSET  0x0004 /* mPHY PCS CLK AFE CSR Offset */
679 /* 1000BASE-T Control Register */
687 /* 1000BASE-T Status Register */
700 #define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
701 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
832 /* NVM Commands - Microwire */
834 /* NVM Commands - SPI */
838 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
866 /* PCI/PCI-X/PCI-EX Config space */
871 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
904 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
908 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
909  * 0=Normal 10BASE-T Rx Threshold
911 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
919  * 1 = 50-80M
920  * 2 = 80-110M
921  * 3 = 110-140M
934  * within 1ms in 1000BASE-T
948 /* Intel i347-AT4 Registers */
957 /* i347-AT4 Extended PHY Specific Control Register */
973 /* i347-AT4 PHY Cable Diagnostics Control */
1001 #define E1000_IPCNFG_EEE_1G_AN       0x00000008  /* EEE Enable 1G AN */
1002 #define E1000_IPCNFG_EEE_100M_AN     0x00000004  /* EEE Enable 100M AN */
1003 #define E1000_EEER_TX_LPI_EN         0x00010000  /* EEE Tx LPI Enable */
1004 #define E1000_EEER_RX_LPI_EN         0x00020000  /* EEE Rx LPI Enable */
1005 #define E1000_EEER_FRC_AN            0x10000000  /* Enable EEE in loopback */
1006 #define E1000_EEER_LPI_FC            0x00040000  /* EEE Enable on FC */
1007 #define E1000_EEE_SU_LPI_CLK_STP     0X00800000  /* EEE LPI Clock Stop */
1008 #define E1000_EEER_EEE_NEG           0x20000000  /* EEE capability nego */
1009 #define E1000_EEE_LP_ADV_ADDR_I350   0x040F      /* EEE LP Advertisement */
1010 #define E1000_EEE_LP_ADV_DEV_I210    7           /* EEE LP Adv Device */
1011 #define E1000_EEE_LP_ADV_ADDR_I210   61          /* EEE LP Adv Register */
1015 #define E1000_M88E1543_EEE_CTRL_1_MS	0x0001     /* EEE Master/Slave */
1019 #define E1000_EEE_ADV_100_SUPPORTED	BIT(1)   /* 100BaseTx EEE Supported */
1020 #define E1000_EEE_ADV_1000_SUPPORTED	BIT(2)   /* 1000BaseT EEE Supported */
1036 /* Tx Rate-Scheduler Config fields */
1053 /* Fetch Time Delta - bits 31:16